CN106788407B - A kind of phaselocked loop for supporting multi-protocols - Google Patents

Abstract

The invention relates to a phase-locked loop supporting multiple protocols, which belongs to the field of integrated circuit design and includes a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider, and the voltage-controlled oscillator has two , set in parallel, and resonate at different frequencies, respectively covering different frequency ranges, only one voltage controlled oscillator is working at the same time; the frequency divider is a multi-mode frequency divider, including multiple frequency division modules with different frequency division ratios , divide the output frequency signal of the working voltage-controlled oscillator, and compare the obtained signal with the reference signal through the frequency and phase detector, and then output the control signal to the voltage-controlled oscillator through the charge pump and low-pass filter. Lock the frequency and phase of the working voltage-controlled oscillator; the phase-locked loop has the characteristics of compact structure, wide coverage frequency range, and supports many operating frequency points. It can output multiple clock frequencies to meet the requirements of high-speed serial interfaces such as Ethernet, Various protocols such as Fiber Channel and RapidIO have requirements on the transmission data rate.

Description

A Phase Locked Loop Supporting Multiple Protocols

technical field

The invention belongs to the technical field of integrated circuit design, in particular to a phase-locked loop supporting multiple protocols.

Background technique

A phase locked loop (Phase Locked Loop, PLL) is a feedback circuit that controls the frequency and phase of a high frequency oscillating signal output by the circuit through an externally input low frequency reference signal. PLL can provide accurate and stable clock signal for other circuits, and plays an important role in wired data transmission and wireless communication.

The basic schematic diagram of PLL is shown in Figure 1, which mainly includes modules such as frequency and phase detector, charge pump, low-pass filter, voltage controlled oscillator (Voltage Controlled Oscillator) and frequency divider. f _REF is the input reference signal, f _OUT is the output signal of the PLL, and f _DIV is the output signal of f _OUT after frequency division by the frequency divider.

There are currently many protocols for high-speed serial data transmission, and each protocol specifies several different data transmission rates. Some applications require a high-speed serial port circuit that can support multiple protocols and multiple data rates. Such a circuit needs a PLL that can provide the required multiple frequencies. At present, some circuits use two PLLs to realize multi-frequency output, so the circuit area is relatively large, and the connection between PLL and other circuits is relatively complicated. Some circuits use a PLL with a fractional frequency division structure to achieve multi-frequency output. At this time, the spurious or noise of the output signal is relatively large, and the signal quality is difficult to guarantee.

Contents of the invention

In order to overcome the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of phase-locked loop that supports multi-protocol, and it supports multiple high-speed serial interface protocols, has a plurality of output frequencies, supports Ethernet, Fiber Channel, RapidIO agreement A variety of data rates specified in, to provide the required clock signal for the transceiver circuit.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A phase-locked loop supporting multiple protocols, including a phase-frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider. There are two voltage-controlled oscillators, which are set in parallel and resonate at Different frequencies cover different frequency ranges, and only one voltage-controlled oscillator is working at the same time; the frequency divider is a multi-mode frequency divider, which includes a plurality of frequency division modules with different frequency division ratios. The output frequency signal f _OUT of the voltage-controlled oscillator is frequency-divided to obtain the signal f _DIV , the signal f _DIV and the reference signal f _REF are compared by a frequency and phase detector, and then output to the voltage-controlled oscillator through a charge pump and a low-pass filter. Control signal to lock the frequency and phase of a working VCO.

The present invention also includes a multiplexer, which selects the output of the working voltage-controlled oscillator and transmits the locked signal.

The present invention also includes a mode control circuit for setting the output frequency, the mode control circuit outputs control signals C ₁ -C ₅ , and C ₁ adjusts the bias current of the charge pump so that the charge pump has correct output at different frequencies; C ₂ and C ₃ set the state of the voltage-controlled oscillator to work or sleep, and adjust the oscillation frequency of the working VCO; C ₄ sets the output source of the multiplexer; C ₅ sets the multi-mode frequency divider frequency division ratio. The control signals C ₁ -C ₅ are unit or multi-bit control signals.

The multi-mode frequency divider includes four frequency division modules, the output frequency signal f _OUT of the voltage-controlled oscillator enters the multi-mode frequency divider, and according to the setting of the control signal C ₅ , f _OUT passes through one of the four frequency division modules Perform frequency division, and then output f _DIV through a multiplexer. The four frequency division modules respectively realize 68/80/82.5/100 frequency division functions.

The 68 frequency division of the frequency division module is realized by cascaded 2 frequency division, 2 frequency division and 8/9 frequency division circuits; the 80 frequency division is realized by cascaded 4 2 frequency division and 1 5 frequency division circuits; 82.5 Frequency division is realized by cascaded divide-by-2, divide-by-2, and 20/21 divide-by-frequency circuits; divide-by-100 is realized by divide-by-2, divide-by-2, divide-by-5, divide-by-5/5 divide-by-circuit circuits.

The frequency division module implements fixed integer or fractional frequency division.

Compared with the prior art, the beneficial effect of the present invention is that only one PLL can support multiple frequencies required by multiple high-speed serial interface protocols. The PLL requires only a fixed external reference input signal. The PLL uses fixed integer and fractional frequency dividers, and the phase noise and spurs of the output signal are small.

Description of drawings

Figure 1 is a schematic diagram of a conventional phase-locked loop.

Figure 2 is a schematic diagram of a phase-locked loop supporting multiple protocols.

Figure 3 is a schematic diagram of a multi-mode frequency divider.

Fig. 4 is a schematic diagram of each frequency division module in the multi-mode frequency divider.

Detailed ways

The preferred embodiments will be described in detail below in conjunction with the accompanying drawings. It should be emphasized that the following description is only exemplary and not intended to limit the scope of the invention and its application.

The circuit structure of PLL of the present invention is as shown in Figure 2, comprises frequency discrimination phase detector, charge pump, low-pass filter, two resonant VCOs at different frequencies, multiplexer and multimode frequency divider, in addition Mode control circuit to set the output frequency. The circuit uses two VCOs, which respectively cover different frequency ranges. In use, only one VCO is working at the same time according to the setting. The multi-mode frequency divider includes multiple frequency division modules with different frequency division ratios to divide the frequency of the working VCO. In particular, it should be noted that each frequency division module in the multi-mode frequency divider implements fixed integer or fractional frequency division, and has good phase noise and spurious characteristics. The output signal f _OUT of the VCO is divided by the multi-mode frequency divider to obtain the signal f _DIV . The f _DIV and the externally input reference signal f _REF are compared by the frequency and phase detector, and then output the control signal to the VCO through the charge pump and the low-pass filter to lock the frequency and phase of the working VCO. The multiplexer selects the output of the working VCO and transmits the locked signal. Since the two VCOs have wide frequency coverage, the multi-mode divider can provide multiple frequency division ratios, so with proper design, it can generate multiple output frequencies required by various protocols. The mode control circuit adjusts other circuits in the PLL to make the PLL work at a set frequency.

The mode control circuit in Fig. 2 outputs control signals C ₁ -C ₅ . C ₁ adjusts the bias current of the charge pump so that the charge pump has the correct output at different frequencies; C ₂ and C ₃ set the state of the VCO (working or dormant), and adjust the oscillation frequency of the working VCO; C ₄ sets Determine the output source of the multiplexer; C ₅ sets the frequency division ratio of the multi-mode frequency divider. It should be noted that C ₁ -C ₅ may be single-bit or multi-bit control signals.

Figure 3 is a schematic diagram of a multi-mode frequency divider. The output f _OUT of the VCO enters the multi-mode frequency divider. According to the setting of the control signal C ₅ , f _OUT is divided by one of the four frequency division modules, and then f _DIV is obtained by outputting through the multiplexer. The four frequency division modules realize 68/80/82.5/100 frequency division functions respectively.

Fig. 4 is an implementation manner of each frequency division module in the multi-mode frequency divider. 68 frequency division is realized by cascaded 2 frequency division, 2 frequency division and 8/9 frequency division circuits; 80 frequency division is realized by cascaded 4 2 frequency division and 1 5 frequency division circuits; 82.5 frequency division is realized by cascaded 2 frequency division, 2 frequency division, 20/21 frequency division circuits; 100 frequency division is realized by cascaded 2 frequency division, 2 frequency division, 5 frequency division/5 frequency division circuits.

Table 1 is the output frequency of the PLL supporting multiple protocols. The input reference signal frequency is 125MHz, and the PLL output signal frequency is 8.5GHz when using 68 frequency division; the PLL output signal frequency is 10.0GHz when using 80 frequency division; the PLL output signal frequency is 10.3125GHz when using 82.5 frequency division; using 100 frequency division When the PLL output signal frequency is 12.5GHz. The four output frequencies of the PLL can be divided by powers of 2 to obtain low-frequency signals. The output of the PLL and its frequency-divided output frequency can support the clock frequency requirements of Ethernet, Fiber Channel, and RapidIO protocols.

Table 1 supports the output frequency of the multi-protocol phase-locked loop

Reference frequency (MHz) Output Frequency(GHz) Frequency division ratio supporting agreement 125 8.5 68 fiber channel 125 10 80 RapidIO 125 10.3125 82.5 Ethernet, RapidIO 125 12.5 100 RapidIO

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (6)

1. a kind of phaselocked loop for supporting multi-protocols, including phase frequency detector, charge pump, low-pass filter, voltage controlled oscillator and point Frequency device, there are two the voltage controlled oscillators, is arranged in parallel, and resonance is covered each by different frequency ranges, together in different frequency One moment only had a voltage controlled oscillator working；The frequency divider is multi-mode frequency divider, contains multiple and different frequency dividing ratios Frequency division module, by the output frequency signal f of the voltage controlled oscillator to work_OUTIt is divided to obtain signal f_DIV, signal f_DIV With reference signal f_REFCompared by phase frequency detector, the control to voltage controlled oscillator is exported using charge pump, low-pass filter Signal locks the frequency and phase of the voltage controlled oscillator to work, which is characterized in that further includes the pattern that output frequency is arranged Control circuit, the mode control circuit output control signal C₁~C₅, C₁Adjust the bias current of charge pump so that in difference Charge pump has correctly output under frequency；C₂And C₃The state of voltage controlled oscillator is set as work or suspend mode, and adjusts work The frequency of oscillation of voltage controlled oscillator；C₄Set the output source of multiple selector；C₅Set the frequency dividing ratio of multi-mode frequency divider.

2. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that further include multiple selector, multichannel choosing The output for selecting the voltage controlled oscillator that device selection is working, the signal after locking is sent out.

3. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that the control signal C₁~C₅It is unit Or multidigit controls signal.

4. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that the multi-mode frequency divider includes four Frequency division module, the output frequency signal f of voltage controlled oscillator_OUTInto multi-mode frequency divider, according to control signal C₅Setting, f_OUT It is divided by one in four frequency division modules, exports to obtain f using multiple selector_DIV, four frequency division modules point 68/80/82.5/100 division function is not realized.

5. supporting the phaselocked loop of multi-protocols according to claim 4, which is characterized in that the frequency division module 68 is divided by cascading 2 frequency dividing, 2 frequency dividing, 8/9 frequency dividing circuit realize；80 frequency dividings are realized by cascade 42 frequency dividings, 15 frequency dividing circuit；82.5 points Frequency is divided by cascade 2,2 frequency dividings, 20/21 frequency dividing circuit are realized；100 frequency dividings are divided by cascade 2,2 divide, 5 divide, 5 points Frequency circuit is realized.

6. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that the frequency division module is realized fixed whole Number or fraction division.