CN106788352A - A kind of electric capacity based on latch is to difference dynamic comparer - Google Patents
A kind of electric capacity based on latch is to difference dynamic comparer Download PDFInfo
- Publication number
- CN106788352A CN106788352A CN201611150150.6A CN201611150150A CN106788352A CN 106788352 A CN106788352 A CN 106788352A CN 201611150150 A CN201611150150 A CN 201611150150A CN 106788352 A CN106788352 A CN 106788352A
- Authority
- CN
- China
- Prior art keywords
- switch
- nmos tube
- termination
- pmos
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a kind of electric capacity based on latch to difference dynamic comparer, belong to the technical field of Digital Analog Hybrid Circuits.Dynamic comparer includes：Latched comparator, controlling switch unit and coupled capacitor unit.Controlling switch unit is entirely only comprising six switches, coupled capacitor unit only includes two electric capacity, the function of difference dynamic comparer is realized with the circuit structure comprising fewer number of electric capacity and switch, while input offset voltage is substantially reduced to coupled capacitor sensitivity, the precision of comparator is improved.
Description
Technical field
The invention discloses a kind of electric capacity based on latch to difference dynamic comparer, belong to the skill of Digital Analog Hybrid Circuits
Art field.
Background technology
In the design of digital-to-analogue mixed signal processing chip, analog-to-digital conversion module is used widely, particularly pipeline organization
Advantage in ADC structures makes main selection in the industry.High-speed comparator as pipeline ADC module core list
Unit, its speed, power consumption, precision and noiseproof feature directly determine the quality of A/D converter with high speed and high precision quality.Based on lock
The electric capacity difference contrast of storage is compared with device because its is low in energy consumption, speed fast, the advantage of high precision is used widely in the adc.
Traditional dynamic latch comparator is as shown in Figure 1.Circuit is by latched comparator 1, controlling switch unit 2 and coupling electricity
Hold the composition of Unit 3.Latched comparator 1 is by the first to fourth PMOS PM1~NMOS tubes of PM4 and first to the 5th NM1~NM5 groups
Into.The grid of the first PMOS PM1 meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；The
The grid of two PMOS PM2 meets negative polarity output mouthful Von, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；
The grid of the 3rd PMOS PM3 meets positive polarity output terminal mouthful Vop, and source electrode connects supply voltage, and drain electrode connects negative polarity output mouthful
Von；The grid of the 4th PMOS PM4 meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets negative polarity output mouthful Von；The
The grid of one NMOS tube NM1 meets negative polarity output mouthful Von, and source electrode connects the drain electrode of the 3rd NMOS tube NM3, and it is defeated that drain electrode connects positive polarity
Exit port Vop；The grid of the second NMOS tube NM2 meets positive polarity output terminal mouthful Vop, and source electrode connects the drain electrode of the 4th NMOS tube NM4, leaks
Pole meets negative polarity output mouthful Von；The grid of the 3rd NMOS tube NM3 meets the first input capacitance Cin1Bottom crown, source electrode connects the 5th
The drain electrode of NMOS tube NM5, drain electrode connects the source electrode of the first NMOS tube NM1；The grid of the 4th NMOS tube NM4 connects the second input capacitance
Cin2Bottom crown, source electrode connects the drain electrode of the 5th NMOS tube NM5, and drain electrode connects the source electrode of the second NMOS tube NM2；5th NMOS tube NM5
Grid meet clock signal CK, source ground, the source electrode and the source electrode of the 4th NMOS tube NM4 of drain electrode and the 3rd NMOS tube NM3
It is connected.
Controlling switch unit 2 is made up of first to the tenth switch K1~K10, a termination negative polarity differential of first switch K1
Signal input port Vin, the first input capacitance of another termination Cin1Top crown；One termination the first input electricity of second switch K2
Hold Cin1Top crown, the other end ground connection；The one second reference voltage signal input port V of termination of the 3rd switch K3ref-, it is another
Terminate the first reference capacitance Cref1Top crown；The one first reference capacitance C of termination of the 4th switch K4ref1Top crown, the other end
Ground connection；The one first reference capacitance C of termination of the 5th switch K5ref1Bottom crown, the other end ground connection；One termination of the 6th switch K6
Positive polarity differential signal input port Vip, the second input capacitance of another termination Cin2Top crown；One termination of the 7th switch K7
Second input capacitance Cin2Top crown, the other end ground connection；The one first reference voltage signal input port of termination of the 8th switch K8
Vref+, the second reference capacitance C of another terminationref2Top crown；The one second reference capacitance C of termination of the 9th switch K9ref2Upper pole
Plate, other end ground connection；The one second reference capacitance C of termination of the tenth switch K10ref2Bottom crown, the other end ground connection.
Coupled capacitor unit 3 is by the first input capacitance Cin1, the second input capacitance Cin2, the first reference capacitance Cref1, second
Reference capacitance Cref2Composition.First input capacitance Cin1Top crown be connected with the tie point of first switch K1 and second switch K2,
Bottom crown connects the grid of the 3rd NMOS tube NM3；Second input capacitance Cin2Top crown and the 6th switch K6 and the 7th switch K7
Tie point is connected, and bottom crown connects the grid of the 4th NMOS tube NM4；First reference capacitance Cref1Top crown and the 3rd switch K3 and
The tie point of the 4th switch K4 is connected, and bottom crown connects the grid of the 3rd NMOS tube NM3；Second reference capacitance Cref2Top crown with
The tie point of the 8th switch K8 and the 9th switch K9 is connected, and bottom crown connects the grid of the 4th NMOS tube NM4.
Traditional latched comparator can realize relatively low power consumption and relatively conversion speed high, but the circuit is maximum
Have the disadvantage mismatch.The factor of the traditional latched comparator mismatch of influence has external factor and internal factor.Internal factor is divided at random
Property and systemic mismatch；The mismatch of the factor such as control signal that external factor primarily inputs and configuration, comprising input clock letter
Number and reference voltage, the mismatch of current reference etc..
As Fig. 1, φ 1 and φ 2 be a pair non-overlapping clock signals, it is assumed that second switch K2, the 4th K4, the 7th K7 and
9th K9 is turned on when φ 1 is high level, and first switch K1, the 3rd switch K3, the 5th switch K5, the 6th switch K6, the 8th open
The switch K10 of K8 and the tenth are closed to be turned on when φ 2 is high level.When φ 1 be low level, φ 2 be high level when, the first input capacitance
The quantity of electric charge at Cin1 two ends is：QCin1=VinCcin1, the quantity of electric charge at the first reference capacitance Cref1 two ends is：QCref1=Vref-
Cref1, can similarly obtain, the quantity of electric charge at the second input capacitance Cin2 two ends is：QCin2=VipCcin2, the second reference capacitance Cref2 two
The quantity of electric charge at end is：QCref2=Vref+Cref2；When φ 2 be low level, φ 1 be high level when, can obtain the 3rd by charge conservation
The grid voltage of NMOS tube NM3 is：The grid voltage of the 4th NMOS tube NM4 is：Ignoring the first input capacitance Cin1With the second input capacitance Cin2Mismatch and the first reference capacitance
Cref1With the second reference capacitance Cref2On the premise of mismatch, it is assumed that Cin1=Cin2=Cin, Cref1=Cref2=Cref, then：Then obtain comparing threshold point voltage and be：
Comparing threshold point can be by adjusting CrefAnd CinValue enter Mobile state adjustment, but note that and compare threshold point
Magnitude of voltage obtained on the premise of capacitance mismatch is ignored, have in practice consider mismatch to performances such as circuit precision
Influence.Another drawback is exactly the controlling switch unit and coupled capacitor unit of the conventional dynamic latched comparator shown in Fig. 1
Employ 4 electric capacity and 10 switches altogether, and electric capacity can occupy sizable area in domain, so directly result in chip into
This rising.
The content of the invention
Goal of the invention of the invention is directed to the deficiency of above-mentioned background technology, there is provided a kind of electric capacity pair based on latch
Difference dynamic comparer, the function of difference dynamic comparer is realized with the circuit structure comprising fewer number of electric capacity and switch,
Solve the technical problem that existing electric capacity has capacitance mismatch to difference dynamic comparer.
The present invention is adopted the following technical scheme that for achieving the above object：
A kind of electric capacity based on latch to difference dynamic comparer, including：
Latched comparator, with in-phase input end, inverting input, clock signal input terminal, positive polarity output terminal and negative
Polarity output terminal,
Controlling switch unit, comprising：Control the sampling of negative polarity differential signal and adjusted according to external reference signal to latch
First subelement of comparator anti-phase input terminal voltage, controls the sampling of positive polarity differential signal and is adjusted according to external reference signal
The second subelement of latched comparator homophase input terminal voltage is saved, and,
Coupled capacitor unit, comprising：The first isolation that the negative polarity differential signal born to its top crown is sampled
The second isolation capacitance that electric capacity, the positive polarity differential signal born to its top crown are sampled, under the first isolation capacitance
Pole plate connects the inverting input of latched comparator, and the bottom crown of the second isolation capacitance connects the in-phase input end of latched comparator.
As the electric capacity based on latch to the further prioritization scheme of difference dynamic comparer, the first of the first subelement
Input termination negative polarity differential signal, second input the first reference voltage signal of termination, the 3rd input termination common mode voltage signal,
The top crown of first, second output the first isolation capacitance of termination, the bottom crown of the 3rd output the first isolation capacitance of termination.
Further, the electric capacity based on latch includes to the first subelement in difference dynamic comparer：First switch,
Second switch, the 3rd switch, the electric current of the first switch flow into termination negative polarity differential signal, and the electric current of second switch is flowed into
Terminate the first reference voltage signal, the electric current of the 3rd switch flows into termination common mode voltage signal, first switch and second switch
Top crown of the electric current outflow end with the first isolation capacitance is connected, under electric current outflow first isolation capacitance of termination of the 3rd switch
Pole plate.
Further, the electric capacity based on latch is in the first subelement of difference dynamic comparer, first, second,
3rd switch is single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
As the electric capacity based on latch to the further prioritization scheme of difference dynamic comparer, the first of the second subelement
Input termination positive polarity differential signal, second input the second reference voltage signal of termination, the 3rd input termination common mode voltage signal,
The top crown of first, second output the second isolation capacitance of termination, the bottom crown of the 3rd output the second isolation capacitance of termination.
Further, the electric capacity based on latch includes to the second subelement in difference dynamic comparer：4th switch,
5th switch, the 6th switch, the electric current of the 4th switch flow into termination positive polarity differential signal, and the electric current of the 5th switch is flowed into
The second reference voltage signal is terminated, the electric current of the 6th switch flows into termination common mode voltage signal, the 4th switch and the 5th switch
Top crown of the electric current outflow end with the second isolation capacitance is connected, under electric current outflow second isolation capacitance of termination of the 6th switch
Pole plate.
Further, the electric capacity based on latch is in the second subelement of difference dynamic comparer, the four, the 5th,
6th switch is single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
As the electric capacity based on latch to the further prioritization scheme of difference dynamic comparer, latched comparator includes：
First to fourth PMOS, the first to the 5th NMOS tube, the grid of the first PMOS, the grid of the 4th PMOS, the 5th NMOS
The grid of pipe and after connecing as the clock signal input terminal of latched comparator, the source electrode of first to fourth PMOS simultaneously connects and is followed by electricity
Source, the drain electrode of the first PMOS, the drain electrode of the second PMOS, the drain electrode of the first NMOS tube, grid, second of the 3rd POMS pipes
The grid of NMOS tube and after connecing as the positive polarity output terminal of latched comparator, the grid of the second PMOS, the first NMOS tube
Grid, the drain electrode of the 3rd PMOS, the drain electrode of the second NMOS tube, the drain electrode of the 4th PMOS connect together and compare as latch
The negative polarity output of device, the source electrode of the first NMOS tube connects the drain electrode of the 3rd NMOS tube, and the source electrode of the second NMOS tube connects the 4th
The drain electrode of NMOS tube, the source electrode of the 3rd NMOS tube is connected with the drain electrode of the source electrode, the 5th NMOS tube of the 4th NMOS tube, and the 3rd
The grid of NMOS tube as latched comparator inverting input, the grid of the 4th NMOS tube is used as the same mutually defeated of latched comparator
Enter end, the source electrode of the 5th NMOS tube connects power supply ground.
The present invention uses above-mentioned technical proposal, has the advantages that：
(1) in dynamic comparer of the present invention, coupled capacitor unit only includes two electric capacity, and controlling switch unit is only
Comprising six switches, realize that external reference signal and differential signal compare to latch by controlling six conductings of switch and shut-off
Compared with the transmission of device input, threshold point voltage is compared by adjusting differential signal reference value and can adjust, reduce capacitance mismatch
Influence to comparing threshold point voltage, improves the comparing precision of comparator, substantially reduces input imbalance to the quick of coupled capacitor
Sense degree；
(2) external reference signal introduces common mode voltage signal so that the voltage of the input of latched comparator two is in common mode
Swung near voltage, be conducive to the steady operation of latched comparator；
(3) coupled capacitor unit is isolated to external reference signal and differential signal, it is to avoid input signal and benchmark
Signal is coupled via the feedthrough of NMOS gate-source capacitances, is conducive to lifting a circuit performance for high speed dynamic comparer.
Brief description of the drawings
Fig. 1 is conventional dynamic latched comparator.
Fig. 2 is electric capacity differential pair dynamic comparer of the present invention based on latch.
Label declaration in figure：1 is latched comparator, and 2 is controlling switch unit, and 3 is coupled capacitor unit, and PM1 to PM4 is
First to fourth PMOS, NM1 to NM5 is the first to the 5th NMOS tube, and K1 to K10 is the first to the tenth switch, Cin1And Cin2
It is the first and second input capacitances, Cref1And Cref2For the first and second reference capacitances, C1 and C2 is the first and second coupling electricity
Hold, φ 1 and φ 2 is a pair non-overlapping clock signals.
Specific embodiment
The technical scheme invented is described in detail below in conjunction with the accompanying drawings.
Comparator of the present invention is as shown in Fig. 2 by latched comparator 1, controlling switch unit 2 and coupled capacitor list
Unit 3 constitutes.Latched comparator 1 is made up of the first to fourth PMOS PM1~NMOS tubes of PM4 and first to the 5th NM1~NM5.
The grid of the first PMOS PM1 meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；Second
The grid of PMOS PM2 meets negative polarity output mouthful Von, and source electrode connects supply voltage, and drain electrode meets positive polarity output terminal mouthful Vop；The
The grid of three PMOS PM3 meets positive polarity output terminal mouthful Vop, and source electrode connects supply voltage, and drain electrode meets negative polarity output mouthful Von；
The grid of the 4th PMOS PM4 meets clock signal CK, and source electrode connects supply voltage, and drain electrode meets negative polarity output mouthful Von；First
The grid of NMOS tube NM1 meets negative polarity output mouthful Von, and source electrode connects the drain electrode of the 3rd NMOS tube NM3, and drain electrode connects positive polarity output
Port Vop；The grid of the second NMOS tube NM2 meets positive polarity output terminal mouthful Vop, and source electrode connects the drain electrode of the 4th NMOS tube NM4, drains
Meet negative polarity output mouthful Von；The grid of the 3rd NMOS tube NM3 connects the bottom crown of the first isolation capacitance C1, and source electrode connects the 5th
The drain electrode of NMOS tube NM5, drain electrode connects the source electrode of the first NMOS tube NM1；The grid of the 4th NMOS tube NM4 meets the second isolation capacitance C2
Bottom crown, source electrode connects the drain electrode of the 5th NMOS tube NM5, and drain electrode connects the source electrode of the second NMOS tube NM2；5th NMOS tube NM5's
Grid meets clock signal CK, and source ground, drain electrode is connected with the source electrode of the 3rd NMOS tube NM3 and the source electrode of the 4th NMOS tube NM4
Connect.Controlling switch unit 2 is made up of first to the 6th switch K1~K6, wherein, a termination negative polarity differential of first switch K1
Signal input port Vin, the top crown of the first isolation capacitance of another termination C1；One first reference voltage of termination of second switch K2
Signal input port Vref+, the top crown of the first isolation capacitance C1 of another termination；The one termination common-mode signal of the 3rd switch K3 is defeated
Inbound port Vcom, the bottom crown of the first isolation capacitance of another termination C1；The one termination positive polarity differential signal input part of the 4th K4
Mouth Vin, the top crown of the second isolation capacitance of another termination C2；The one second reference voltage signal input of termination of the 5th switch K5
Mouth Vref-, the top crown of the second isolation capacitance C2 of another termination；The one termination common-mode signal input port Vcom of the 6th switch K6,
The bottom crown of the first isolation capacitance C1 of another termination.Controlling switch can be separately formed by PMOS or NMOS, also can by PMOS and
The transmission gate of NMOS compositions is constituted.Coupled capacitor unit 3 is made up of the first isolation capacitance C1 and the second isolation capacitance C2, wherein,
The top crown of the first isolation capacitance C1 is connected with the tie point of first switch K1 and second switch K2, and bottom crown connects the 3rd NMOS tube
The grid of NM3；The top crown of the second isolation capacitance C2 is connected with the tie point of the 4th switch K4 and the 5th switch K5, and bottom crown connects
The grid of the 4th NMOS tube NM4.
In Fig. 2, φ 1 and φ 2 and be a pair non-overlapping clock signals, it is assumed that first switch K1 and the 4th K4 are in φ 2
Turned on during for high level, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 lead when φ 1 is high level
It is logical.When φ 1 be high level, φ 2 be low level when, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 lead
Logical, the switches of first switch K1 and the 4th K4 ends, and the first isolation capacitance C1 two ends quantity of electric charge is：Q1=(Vref+-Vcom)C1, second
The isolation capacitance C2 two ends quantity of electric charge is：Q2=(Vref--Vcom)C2；When φ 1 be low level, φ 2 be high level when, second switch
K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 cut-offs, the switch K4 conductings of first switch K1 and the 4th are kept according to electric charge
Perseverance, can obtain C1 bottom crown voltages is：V1=Vcom-(Vref+-Vin), can similarly obtain C2 bottom crown terminal voltages is：V2=
Vcom-(Vref--Vip), two formulas are subtracted each other, and are obtained：
V1-V2=(Vin-Vip)-(Vref+-Vref-),
It is hereby achieved that compare threshold point voltage being：Vip-Vin=Vref--Vref+。
From above formula it can be found that：
(1) compare threshold point voltage unrelated with electric capacity, only have relation with two input reference voltages, compared to tradition
Dynamic latch comparator, the mismatch of electric capacity is unrelated compared with threshold point (influenceing very little in other words) by contrast, and this can greatly improve ratio
Compared with the comparing precision of device.
(2) quantity of MOS switch is reduced to six, and the use of electric capacity is reduced to two, and the electric capacity can be set
Smaller, compared to the domain of traditional circuit, the area that electric capacity is occupied in domain is substantially reduced, and reduces being manufactured into for circuit
This.
(3) by isolation capacitance C1 and C2, input signal and reference signal are isolated, it is to avoid input signal and benchmark
Signal is coupled via the feedthrough of NMOS gate-source capacitances, and in high speed applications, this point is very heavy for the lifting of circuit performance
Want.Additionally, from analysis above it is recognised that the value of V1 and V2 is to be swung near common-mode voltage, this compares for latching
It is very good compared with the steady operation of device.
Above content is the preferred embodiments of the invention, but it cannot be assumed that specific implementation of the invention is confined to
This, it is noted that under the premise without departing from the principles of the invention, simple modifications and modification to circuit are regarded as the present invention
Protection domain.
Claims (8)
1. a kind of electric capacity based on latch is to difference dynamic comparer, it is characterised in that including：
Latched comparator（1）, with in-phase input end, inverting input, clock signal input terminal, positive polarity output terminal and negative pole
Property output end,
Controlling switch unit（2）, comprising：Control the sampling of negative polarity differential signal and ratio is latched according to external reference signal regulation
Compared with the first subelement of device anti-phase input terminal voltage, control the sampling of positive polarity differential signal and adjusted according to external reference signal
Second subelement of latched comparator homophase input terminal voltage, and,
Coupled capacitor unit（3）, comprising：The first isolation electricity that the negative polarity differential signal born to its top crown is sampled
The second isolation capacitance that the positive polarity differential signal for hold, being born to its top crown is sampled, the lower pole of the first isolation capacitance
Plate connects the inverting input of latched comparator, and the bottom crown of the second isolation capacitance connects the in-phase input end of latched comparator.
2. according to claim 1 a kind of electric capacity based on latch to difference dynamic comparer, it is characterised in that described
The first input end of one subelement connects negative polarity differential signal, second input the first reference voltage signal of termination, the 3rd input
Connect common mode voltage signal, the top crown of first, second output the first isolation capacitance of termination, the 3rd output the first isolation capacitance of termination
Bottom crown.
3. according to claim 2 a kind of electric capacity based on latch to difference dynamic comparer, it is characterised in that described
One subelement includes：First switch, second switch, third switch, the electric current of the first switch flows into termination negative polarity differential
Signal, the electric current of second switch flows into the first reference voltage signal of termination, and the electric current of the 3rd switch flows into termination common-mode voltage letter
Number, the top crown of the electric current outflow end of first switch and second switch with the first isolation capacitance is connected, the electric current of the 3rd switch
The bottom crown of outflow the first isolation capacitance of termination.
4. according to claim 3 a kind of electric capacity based on latch to difference dynamic comparer, it is characterised in that described
First, second, third switch is single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
5. according to claim 1 a kind of electric capacity based on latch to difference dynamic comparer, it is characterised in that described
The first input end of two subelements connects positive polarity differential signal, second input the second reference voltage signal of termination, the 3rd input
Connect common mode voltage signal, the top crown of first, second output the second isolation capacitance of termination, the 3rd output the second isolation capacitance of termination
Bottom crown.
6. according to claim 5 a kind of electric capacity based on latch to difference dynamic comparer, it is characterised in that described
Two subelements include：4th switch, the 5th switch, the 6th switch, the electric current of the 4th switch flow into termination positive polarity differential
Signal, the electric current of the 5th switch flows into the second reference voltage signal of termination, and the electric current of the 6th switch flows into termination common-mode voltage letter
Number, the top crown of the 4th switch and the 5th electric current outflow end for switching with the second isolation capacitance is connected, the electric current of the 6th switch
The bottom crown of outflow the second isolation capacitance of termination.
7. according to claim 6 a kind of electric capacity based on latch to difference dynamic comparer, it is characterised in that described
4th, the five, the 6th switches are single PMOS or single NMOS tube or the transmission gate being made up of PMOS and NMOS tube.
8. according to claim 1 a kind of electric capacity based on latch to difference dynamic comparer, it is characterised in that the lock
Deposit comparator（1）Including：First to fourth PMOS, the first to the 5th NMOS tube, the grid of the first PMOS, the 4th PMOS
Grid, the grid of the 5th NMOS tube and after connecing as the clock signal input terminal of latched comparator, first to fourth PMOS
Source electrode and connect and be followed by power supply, the drain electrode of the first PMOS, the drain electrode of the second PMOS, the drain electrode of the first NMOS tube, the 3rd
The grid of POMS pipes, the grid of the second NMOS tube and after connecing as the positive polarity output terminal of latched comparator, the second PMOS
Grid, the grid of the first NMOS tube, the drain electrode of the 3rd PMOS, the drain electrode of the second NMOS tube, the drain electrode of the 4th PMOS simultaneously connect
Together as the negative polarity output of latched comparator, the source electrode of the first NMOS tube connects the drain electrode of the 3rd NMOS tube, second
The source electrode of NMOS tube connects the drain electrode of the 4th NMOS tube, the source electrode of the 3rd NMOS tube and source electrode, the 5th NMOS tube of the 4th NMOS tube
Drain electrode be connected, the grid of the 3rd NMOS tube as latched comparator inverting input, the grid conduct of the 4th NMOS tube
The in-phase input end of latched comparator, the source electrode of the 5th NMOS tube connects power supply ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611150150.6A CN106788352A (en) | 2016-12-14 | 2016-12-14 | A kind of electric capacity based on latch is to difference dynamic comparer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611150150.6A CN106788352A (en) | 2016-12-14 | 2016-12-14 | A kind of electric capacity based on latch is to difference dynamic comparer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106788352A true CN106788352A (en) | 2017-05-31 |
Family
ID=58881096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611150150.6A Pending CN106788352A (en) | 2016-12-14 | 2016-12-14 | A kind of electric capacity based on latch is to difference dynamic comparer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106788352A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
| CN110912542A (en) * | 2019-11-02 | 2020-03-24 | 复旦大学 | A Low-Power Dynamic Bias Comparator |
| WO2023178819A1 (en) * | 2022-03-23 | 2023-09-28 | 长鑫存储技术有限公司 | Comparator circuit, mismatch correction method, and memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201105043A (en) * | 2009-07-16 | 2011-02-01 | Ralink Technology Corp | Comparator for a pipelined analog to digital converter and related signal sampling method |
| CN201766574U (en) * | 2010-08-18 | 2011-03-16 | 中国电子科技集团公司第五十八研究所 | High-speed common mode insensitive charge comparator circuit |
| CN203377849U (en) * | 2013-07-15 | 2014-01-01 | 中国电子科技集团公司第五十八研究所 | High speed offset compensation dynamic comparator |
| CN104113342A (en) * | 2013-11-28 | 2014-10-22 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
| CN206364778U (en) * | 2016-12-14 | 2017-07-28 | 无锡芯响电子科技有限公司 | A kind of electric capacity based on latch is to difference dynamic comparer |
-
2016
- 2016-12-14 CN CN201611150150.6A patent/CN106788352A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201105043A (en) * | 2009-07-16 | 2011-02-01 | Ralink Technology Corp | Comparator for a pipelined analog to digital converter and related signal sampling method |
| CN201766574U (en) * | 2010-08-18 | 2011-03-16 | 中国电子科技集团公司第五十八研究所 | High-speed common mode insensitive charge comparator circuit |
| CN203377849U (en) * | 2013-07-15 | 2014-01-01 | 中国电子科技集团公司第五十八研究所 | High speed offset compensation dynamic comparator |
| CN104113342A (en) * | 2013-11-28 | 2014-10-22 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
| CN206364778U (en) * | 2016-12-14 | 2017-07-28 | 无锡芯响电子科技有限公司 | A kind of electric capacity based on latch is to difference dynamic comparer |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
| CN110912542A (en) * | 2019-11-02 | 2020-03-24 | 复旦大学 | A Low-Power Dynamic Bias Comparator |
| WO2023178819A1 (en) * | 2022-03-23 | 2023-09-28 | 长鑫存储技术有限公司 | Comparator circuit, mismatch correction method, and memory |
| US12218673B2 (en) | 2022-03-23 | 2025-02-04 | Changxin Memory Technologies, Inc. | Comparator circuit, method for correcting mismatch and memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106160743B (en) | A gate voltage bootstrap switch circuit for sample and hold circuit | |
| CN206364778U (en) | A kind of electric capacity based on latch is to difference dynamic comparer | |
| CN105897271B (en) | A kind of high if sampling holding circuit for production line analog-digital converter | |
| CN107370487A (en) | A kind of boot-strapped switch circuit based on NMOS tube | |
| CN208299759U (en) | A kind of automatic calibration circuit of amplifier input offset voltage | |
| CN106788352A (en) | A kind of electric capacity based on latch is to difference dynamic comparer | |
| CN108322199B (en) | Dynamic comparison method | |
| CN101562453A (en) | Analog sampling switch and analog-to-digital converter | |
| CN100490312C (en) | Common mode feedback circuit for switching capacitor system | |
| CN103346765A (en) | Gate-source following sampling switch | |
| CN105071806A (en) | High-linearity input signal buffer applied to high-speed analog-digital converter | |
| CN108957334A (en) | battery sampling system | |
| CN106921391A (en) | System-level error correction SAR analog-digital converters | |
| CN112003619B (en) | Time domain comparator for ultra-low power consumption successive approximation analog-to-digital converter | |
| CN101674085A (en) | Sampling hold circuit applied to analogue-to-digital converter | |
| CN108718197A (en) | A kind of the SAR ADC capacitor arrays and its Switching method of low-power consumption | |
| CN105119601B (en) | A kind of multi-center selection circuit being suitable for A/D converter with high speed and high precision | |
| CN208188303U (en) | battery sampling system | |
| CN106292818A (en) | Be suitable to fully differential generating circuit from reference voltage and the Wireless Telecom Equipment of pipeline ADC | |
| CN110690900B (en) | A Time Domain ADC Full Swing Front-End Circuit | |
| CN102291116B (en) | Turnover type sampling hold circuit | |
| CN204967796U (en) | Be applied to high -speed adc's high linearity incoming signal buffer | |
| CN109245768A (en) | A kind of SAR ADC with sampling with high precision switch | |
| CN113676183B (en) | High-precision low-power-consumption SAR ADC based on two steps | |
| CN209593406U (en) | A Novel Operational Amplifier Circuit Suitable for 12-bit Pipeline ADC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170531 |