CN106783985A - Power device and preparation method thereof - Google Patents

Abstract

The present disclosure provides power devices and fabrication methods thereof. The power device includes: a first device having a plurality of first source regions and a plurality of first trenches, and the plurality of first trenches electrically isolate the plurality of first source regions from each other; at least one second device having a plurality of The second source region has a plurality of second trenches, and the plurality of second trenches electrically isolate the plurality of second source regions from each other, wherein the second device is embedded in the first device and the second trenches of the second device The trench communicates with the corresponding first trench of the first device, and there is a metal spacer region between the second source region of the second device and the first source region of the first device, and there is additional P+ diffusion in the metal spacer region region to act as a resistive isolation between the second device and the first device.

Description

Power device and manufacturing method thereof

technical field

The present disclosure relates to the field of semiconductors, in particular to a power device and a manufacturing method thereof.

Background technique

For power devices, in order to monitor the working status of the device, it is necessary to measure the amount of current conducted by the device quantitatively and timely in full scale to ensure the safety and reliability of the device, especially in the field of automotive electronics. Traditionally, a current sensing device, such as a current mirror device, can be coupled in at an appropriate location within the overall device (called a master device) to provide this measurement. In this case, the current sensing device not only needs to be fully isolated from the main device, but also needs a freewheeling diode to complete its own current discharge.

Contents of the invention

According to an aspect of the present disclosure, a power device is provided, including: a first device, the first device has a plurality of first source regions and a plurality of first trenches, and the plurality of first trenches connect the plurality of first source regions The regions are electrically isolated from each other; at least one second device, the second device has a plurality of second source regions and has a plurality of second trenches, and the plurality of second trenches electrically isolates the plurality of second source regions from each other, wherein the first The second device is embedded in the first device, and the second trench of the second device communicates with the corresponding first trench of the first device, and the second source region of the second device communicates with the first source region of the first device. Between the regions there is a metal spacer region within which there is an additional P+ diffusion region to act as a resistive isolation between the second device and the first device.

According to a second aspect of the present disclosure, there is provided a method for fabricating a power device, comprising: providing a substrate; forming a body region of a first device and a body region of at least one second device on the substrate; A plurality of first trenches for the first device are formed in the body region of the second device, and a plurality of second trenches for the second device are formed in the body region of the second device, wherein the second trenches of the second device and Corresponding first trenches of the first device are connected; a plurality of first source regions for the first device and a plurality of second source regions for the second device are formed, wherein the plurality of first source regions pass through multiple The first trenches are electrically isolated from each other, and the plurality of second source regions are electrically isolated from each other through the plurality of second trenches, wherein there is a gap between the second source region of the second device and the first source region of the first device. A metal spacer region in which an additional P+ diffusion region is formed as a resistive isolation between the second device and the first device.

According to the power device and its manufacturing method of the present disclosure, the first device and the second device are coupled and isolated in a unique manner, and the embedding of the second device is smooth and does not cause structural changes to the first device, so there is no Any adverse effect on the current-voltage performance of the first device. In addition, since the additional P+ diffusion region is included in the metal spacing region, the second device can achieve good resistive isolation from the first device, so that the second device can share the same freewheeling diode as the first device to realize current shedding. put.

Description of drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are schematic and should not be construed as limiting the disclosure in any way, in which:

FIG. 1 is a simplified plan view illustrating a power device according to an exemplary embodiment of the present disclosure;

FIG. 2 is a plan view illustrating a power device according to an exemplary embodiment of the present disclosure;

Fig. 3-Fig. 6 shows the sectional view along A-A, B-B, C-C, D-D in Fig. 2 respectively;

7 is a plan view illustrating a power device according to an exemplary embodiment of the present disclosure;

Fig. 8-Fig. 9 shows the sectional view along E-E, F-F in Fig. 7 respectively;

10 is a plan view illustrating a power device according to an exemplary embodiment of the present disclosure;

Fig. 11-Fig. 12 shows the sectional view along G-G, H-H in Fig. 10 respectively;

13 is a plan view illustrating a power device according to an exemplary embodiment of the present disclosure;

14 is a plan view illustrating a power device according to an exemplary embodiment of the present disclosure;

Fig. 15-Fig. 16 shows the sectional view along I-I, J-J in Fig. 14 respectively;

17 is an equivalent circuit diagram illustrating a power device according to an exemplary embodiment of the present disclosure; and

FIG. 18 is a flowchart illustrating a method of manufacturing a power device according to an exemplary embodiment of the present disclosure.

detailed description

The following detailed description of the embodiments of the present disclosure covers numerous specific details in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only to provide a clearer understanding of the present invention by showing examples of the present invention. The present invention is by no means limited to any specific configuration set forth below, but covers any modifications, substitutions and improvements of related elements and parts without departing from the spirit of the present invention.

The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to limit the invention to any theory expressed or implied by the preceding technical field, background or the following detailed description.

The abbreviations "MOSFET" and "IGBT" are used in this disclosure to refer to Metal Oxide Semiconductor Field Effect Transistor and Insulated Gate Bipolar Transistor, respectively. MOSFETs and IGBTs have conductive gate electrodes, however it should be understood that the conductive material is not necessarily a metallic material, but can be, for example, metal alloys, semi-metals, metal-semiconductor alloys or compounds, doped semiconductors, combinations thereof. In this disclosure, references to "metal", "metal contact" and the like should be broadly interpreted to include the various conductor forms discussed above and are not intended to be limited to metallized conductors only. Non-limiting examples of insulating materials suitable for use in MOSFETs and IGBTs are oxides, nitrides, oxygen nitrogen mixtures, organic insulating materials, and other dielectrics.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present invention. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the size of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help to improve the understanding of the embodiments of the invention.

Ordinal numerals such as "first" and "second" in the description and claims may be used to distinguish between similar elements or steps and not necessarily to describe a specific sequence or sequential order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation or arrangement in sequences other than those illustrated or otherwise described herein . Furthermore, the terms "comprising", "comprising", "having" and variations thereof, are meant to cover non-exclusive inclusions such that a process, method, product or apparatus comprising a series of elements or steps is not necessarily limited to those elements or steps, but may include other elements or steps not explicitly listed or inherent to the process, method, product or apparatus. As used herein, the term "communication" is defined as a direct or indirect electrical or non-electrical connection. As used herein, the terms "substantial" and "substantially" mean sufficient in a practical manner to accomplish the stated purpose and that those minor defects, if any, are not apparent for the stated purpose Impact.

"Additionally" in the specification and claims means other than normal. For example "an additional P+ diffusion region" refers to a diffusion outside the normal active region diffusion and at a concentration higher than the bulk concentration.

As used herein, the term "substrate" may refer to a semiconductor substrate, whether the semiconductor used is single crystal, polycrystalline or amorphous, and includes group IV semiconductors, non-group IV semiconductors, compound semiconductors, and organic and inorganic semiconductors, and may Examples are thin-film structures or laminated structures.

For ease of illustration and without limitation, silicon semiconductors are used herein to describe power devices and methods of making them, but those skilled in the art will understand that other semiconductor materials may also be used. In addition, various device types and/or doped semiconductor regions may be labeled N-type or P-type, but this is for convenience of illustration and not intended to be limiting, and such labels may be "first conductivity type" or "second, instead of the more general description of "opposite conductivity type", where the first conductivity type can be either N-type or P-type, and the second conductivity type can also be P-type or N-type.

According to an aspect of the present invention, a power device is provided, including: a first device, the first device has a plurality of first source regions and a plurality of first trenches, and the plurality of first trenches connect the plurality of first source regions The regions are electrically isolated from each other; at least one second device, the second device has a plurality of second source regions and has a plurality of second trenches, and the plurality of second trenches electrically isolates the plurality of second source regions from each other, wherein the first The second device is embedded in the first device, and the second trench of the second device communicates with the corresponding first trench of the first device, and the second source region of the second device communicates with the first source region of the first device. Between the regions there is a metal spacer region within which there is an additional P+ diffusion region to act as a resistive isolation between the second device and the first device.

Embodiments according to the present invention will be described in more detail below with reference to the accompanying drawings.

FIG. 1 is a simplified plan view illustrating a power device 100 according to an exemplary embodiment of the present disclosure. As shown in FIG. 1 , a power device 100 includes a first device 1 and a second device 2 . In one example, the second device 2 may be a current sensing device, such as a mirror current device. The second device 2 is formed on the same substrate 3 as the first device 1, that is, the second device 2 and the first device 1 are coupled in the same chip, so that the second device 2 and the first device 1 can Under the same conditions (eg temperature). The substrate 3 may be a P+N substrate, whereby the power device 100 may be an insulated gate bipolar transistor (IGBT), or the substrate may be an N+N substrate, whereby the power device 100 may be a metal oxide semiconductor Field Effect Transistors (MOSFETs).

The second device 2 is embedded in the first device 1 , and the second device 2 is electrically isolated from the first device 1 . In essence, the second device 2 has a drain and a gate connected to the first device 1, except that the source region is electrically isolated. The second device 2 is electrically isolated from the first device 1 by a metal spacing region (not shown).

As shown in FIG. 1 , the power device 100 further includes a gate electrode terminal 4 to which each gate of the first device 1 and the second device 2 is connected. Specifically, the polysilicon in each gate trench of the first device 1 and the second device 2 is connected to the gate electrode terminal 4 .

It should be understood that although the second device 2 is shown approximately in the center portion of the first device 1 and only one second device 2 is shown, this is only an example. The second device 2 can be located in any other position of the first device 1 , and more second devices 2 can also be arranged, which depends on the temperature distribution and specific requirements of the chip.

The total effective size area of the second device 2 (ie, the area of the metal source region) is scaled down (CSR) to the total effective size area of the first device 1 in order to obtain a current proportional to the current of the first device 1 . In this way, the current collected by the second device 2 can determine the amount of current conducted by the first device 1 , so as to monitor the state of the first device 1 .

FIG. 2 is a plan view illustrating details of a power device 200 according to an exemplary embodiment of the present disclosure. As shown in FIG. 2 , the power device 200 includes a first device 1 and a second device 2 . The second device 2 is embedded in the first device 1 , and the second device 2 is electrically isolated from the first device 1 by the metal spacing region 5 . As mentioned above, substantially the metal spacer region 5 electrically separates the source region of the second device 2 from the source region of the first device 1 . In FIG. 2 , the area outside the outer dotted line represents the metal 11 of the first device 1 , and the area inside the inner dotted line represents the metal 21 of the second device 2 . More precisely, the uppermost layer of the chip is a metal layer, and the area outside the outer dashed line is covered with the metal of the first device 1 , and the area inside the inner dashed line is covered with the metal of the second device 2 . The area between the two dotted lines is the metal spacing area 5, which separates the metal of the first device 1 from the metal of the second device 2, and accordingly separates the source area of the first device 1 from the source area of the second device 2 open. In the present disclosure, the metal spacing region 5 means that there is a certain distance between the metal 11 of the first device 1 and the metal 21 of the second device 2 . As shown in Figure 2, there is a P+ diffusion region (the area indicated by the shaded part in the metal spacing region 5 among the figures) in the metal spacing region 5, and the P+ diffusion region surrounds the second device 2 so that the second device 2 and the first The device 1 is internally isolated, and this isolation is resistive, that is, the equivalent resistance between the second device 2 and the first device 1 (for example, tens of ohms to thousands of ohms). Furthermore, the second device 2 includes a source metal lead-out portion 7 . The source of the second device 2 is connected to a second device source terminal (not shown in the figure) through the source metal lead portion 7 . In FIG. 2 , the source metal lead-out line portion 7 of the second device 2 is shown at the bottom in the figure, spanning the metal spacer portion on both sides, and its width is L. It should be understood that the arrangement (eg, position and width L) of the source metal lead-out line portion 7 is not limited thereto, but can be designed according to specific requirements. There may also be another P+ diffusion region 6 in the body region below the source metal lead part 7, so that the breakdown voltage of the first device 1 is not affected, especially when the width L of the source metal lead part 7 is greater than When a certain value (for example, 30μm).

Referring next to FIG. 2 , the first device 1 has a plurality of first source regions 12 each with its first metal contact 14 . The first device 1 collects current through these first source regions 12 during operation. Similarly, the second device 2 has a plurality of second source regions 22 , each first source region 22 having its second metal contact 24 . The second device 2 collects current through these second source regions 22 . The current collected by the second device 2 through all the second source regions 22 should be in a predetermined proportional relationship with the current collected by the first device 1 through all the first source regions 12 . By measuring the current collected by the second device 2 , the amount of current conducted by the first device 1 can be determined, and then the state of the first device 1 can be monitored. It should be understood that these source regions 12 and 22 are actually located below the metal layer, which is illustrated hereinafter.

In addition, as shown in FIG. 2 , the first device 1 further includes a plurality of first trenches 13 . In one example, the first groove 13 may be a strip groove. These first trenches 13 electrically isolate the plurality of first source regions 12 of the first device 1 from each other. Similarly, the second device 2 also includes a plurality of second trenches 23 . In one example, the second groove 23 may be a strip groove. These second trenches 23 electrically isolate the plurality of second source regions 22 of the second device 2 from each other. In some embodiments, the second trench 23 of the second device 2 communicates with the corresponding first trench 13 of the first device 1 . In essence, the first trench 13 and the second trench 23 are actually located in the body regions of the first device 1 and the second device 2 respectively, and the first trench 13 and the second trench 23 respectively correspond to the first device 1 The gate of the first device 1 is connected to the gate of the second device 2 , that is, the gate of the first device 1 is connected to the gate of the second device 2 .

In some embodiments, the second source region 22 of the second device 2 corresponds to a corresponding one of the first source regions 12 of the first device 1 . For example, as shown in FIG. 2, the second source region 22-1 corresponds to the first source region 12-1. The second trench 23 of the second device 2 directly communicates with the corresponding first trench 13 of the first device 1 .

In addition, as shown in FIG. 2, although the plurality of second source regions 22 of the second device 2 are separated by second trenches 23, these second source regions 22 are concentratedly arranged, that is, two adjacent second Source regions 22 are not separated from any other source regions. In addition, although six source regions and corresponding metal contacts of the second device 2 are shown in FIG. 2, this is only a schematic diagram, and the second device 2 may have more or fewer source regions and corresponding metal contacts, which Depending on the predetermined ratio CSR of the second device 2 to the first device 1 .

3-6 respectively show cross-sectional views along A-A, B-B, C-C, and D-D in FIG. 2 . Fig. 3 shows a sectional view along A-A in Fig. 2 . Referring back to FIG. 2, the A-A line crosses the metal region of the first device 1 and the metal region of the second device 2, and both ends of the A-A line are located exactly at the source region metal contact 14 of the first device 1 and the source region of the second device 2 metal contact 24 on. As shown in FIG. 3 , the first device 1 and the second device 2 are formed on the same substrate 3 . In one embodiment, the first device 1 and the second device 2 may be formed on a P+N type substrate or an N+N type substrate.

Furthermore, as shown in FIG. 3, on the substrate 3, an active region is formed. The active area is composed of N-type layer and P-type layer. An N+ layer is formed on the P-type layer, and a source region P+ region is formed in the P-type layer and the N+ layer. An oxide layer 10 is deposited above the P+ region of the source region. Both sides of the oxide layer 10 are respectively the source region and the metal 11 of the first device and the source region and the metal 21 of the second device, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by the metal spacing region 5 open. As shown, there is a further P+ diffusion region 6 in the body region below the metal spacer region 5 to resistively isolate the source region 12 of the first device 1 from the source region 22 of the second device 2 . The first device 1 and the second device 2 respectively collect their respective currents via their respective source regions through corresponding metal contacts 14 and 24 along arrows I1 and I2 representing current flow directions.

Fig. 4 shows a sectional view along B-B in Fig. 2 . As shown in the figure, the source region (including P+ region and N+ region) of the first device 1, the P+ diffusion region 6 below the source metal lead-out part 7 of the second device 2, the first trench 13 of the first device 1 are all located on the same substrate 3. Referring back to FIG. 2 , the B-B line crosses the source metal lead-out line part 7 of the second device 2 in the middle, and one end of the B-B line is just located at the source metal contact 14 of the first device 1 on the side of the source metal lead-out line part 7 , and the other end is just located on the source metal contact 14 of the first device 1 on the other side of the source metal lead-out line portion 7 . Since the two ends of the B-B line are just located on the source region metal contact 14 of the first device 1, the first device 1 can pass through the corresponding first metal contact through the first source region 12 on both sides of the source metal lead-out line part 7 respectively. 14 collects the current (as indicated by 11). In addition, an additional P+ diffusion region 6 may be provided below the source metal lead-out portion 7 as shown in the figure. Since there is no metal contact under the source metal lead-out line portion 7 of the second device 2, especially when the width L of the source metal lead-out line portion 7 is greater than a certain value (for example, 30 μm), the area under the source metal lead-out line portion 7 The arrangement of the additional P+ diffusion region 6 can make the breakdown voltage of the first device 1 unaffected. This P+ diffusion region 6 can be formed simultaneously with the further P+ region 6 surrounding the second device 2 . In some embodiments, these additional P+ diffusion regions 6 can be formed together with the P+ diffusion of the voltage guard ring around the first device 1 (not shown in the figure).

Fig. 5 shows a sectional view along C-C in Fig. 2 . Referring back to FIG. 2 , the C-C line crosses the metal 11 of the first device 1 and the metal 21 of the second device 2 , and the C-C line is vertical and crosses the 4 trenches and the additional P+ diffusion region 6 within the metal spacing region 5 . Referring to FIG. 5 , the first device 1 and the second device 2 are formed on the same substrate 3 , and the metal 11 of the first device 1 is electrically isolated from the metal 21 of the second device 2 by the metal spacing region 5 . In the metal spacer region 5 , in particular in the body region below the metal spacer region 5 and below the oxide layer 10 , there is a further P+ diffusion region 6 . In addition, one end of the C-C line enters the metal region of the first device 1 and the other end enters the metal region of the second device 2 as it moves away from the P+ diffusion region 6 in the middle. In the part of the first device 1, there are two trenches 13, and the first metal contact 14 of the first source region 12 exists between the two trenches 13, and the current is collected through the first metal contact 14, as indicated by I1 . On the other hand, in the part of the second device 2, there are also two trenches 23, and there is a second metal contact 24 of the second source region 22 between the two trenches 23, and the current is collected through the second metal contact 24, As indicated by I2. In this way, the first device 1 and the second device 2 respectively collect their own currents along the arrows I1 and I2 that indicate the current flow directions shown in the figure.

FIG. 6 shows a sectional view along D-D in FIG. 2 . As shown in FIG. 2, the D-D line is located in the additional P+ diffusion region 6 and spans the trench. Thus, in the cross-sectional view of Fig. 6, an additional P+ diffusion region 6 is shown straddling the trench 13/23. In some embodiments, the additional P+ diffusion region 6 can be formed simultaneously with the P+ diffusion of the P+ voltage guard ring around the first device 1 (not shown in the figure).

It should be noted that, in the power device according to the embodiment of the present disclosure, the body regions of the second device 2 and the first device 1 except the trenches are all active regions. In this way, the embedding of the second device 2 is smooth and does not cause structural changes to the first device 1 , and therefore does not cause any adverse effects on the current and voltage performance of the first device 1 . In addition, due to the additional P+ diffusion region 6 contained in the metal spacing region 5, the second device 2 can achieve good resistive isolation from the first device 1, so that the second device 2 and the first device 1 can share the same Freewheeling diodes are used to bleed the current.

FIG. 7 is a plan view illustrating a power device 300 according to an exemplary embodiment of the present disclosure. Compared with FIG. 2 , except for the connection mode between the first trench 13 of the first device 1 and the second trench 23 of the second device 2 , other configurations of the power device 300 in FIG. 7 are similar to those of the power device in FIG. 2 200 are of the same structure. Specifically, the power device 300 in FIG. 7 is different from the power device 200 in FIG. 2 in that the first trench 13 of the first device 1 is not directly connected to the second trench 23 of the second device 2, but The communication is via the corresponding polysilicon structure 8 . It should be understood that although it is shown in the figure that each pair of trenches is connected through one polysilicon structure 8, other forms may also be adopted, for example, every two pairs, three pairs... or all trenches are connected through a corresponding number of polysilicon structures 8 connected.

8 and 9 are cross-sectional views along E-E and F-F in FIG. 7, respectively. The position of E-E in power device 300 is similar to the position of D-D line in power device 200 . Compared with the cross-sectional view of D-D in FIG. 6, in FIG. 8, since the first trench 13 of the first device 1 is not directly connected to the second trench 23 of the second device 2, but is communicated through the polysilicon structure , so there is no trench in the body region in the cross-sectional view, but only the P+ diffusion region 6 below the metal spacer region 5 . In addition, as shown in FIG. 8 , in the region above the P+ diffusion region 6 , polysilicon 8 for connecting trenches is also shown.

The positions of F-F in the power device 300 are similar to the positions of A-A in the power device 200 , they both straddle the metal isolation region 5 , one end is within the range of the first device 1 , and the other end is within the range of the second device 2 . The difference is that the two ends of A-A are located on the metal contacts 14 and 24 of the first device 1 and the second device 2 respectively, and the two ends of F-F are respectively located on the trenches 13 and 23 of the first device 1 and the second device 2 superior. As shown in FIG. 9 , the first trench 13 of the first device 1 is communicated with the second trench 23 of the second device 2 through the polysilicon structure 8 .

According to the power device of the embodiment of the present disclosure, by using the polysilicon structure, the working channel of the second device can be completely disconnected from the working channel of the first device, and the trench of the second device can be realized from the trench of the first device. connected.

FIG. 10 is a plan view illustrating a power device 400 according to an exemplary embodiment of the present disclosure. As shown in FIG. 10 , the same as the power device 200 shown in FIG. 2 , the power device 300 includes a first device 1 and a second device 2 . The second device 2 is embedded in the first device 1 , and the second device 2 is electrically isolated from the first device 1 by the metal spacing region 5 . Furthermore, the first device 1 has a plurality of source regions 12 and a plurality of trenches 13 . These first trenches 13 electrically isolate the plurality of source regions 12 of the first device 1 from each other. The second device 2 has a plurality of source regions 22 and a plurality of trenches 23 . These second trenches 23 electrically isolate the source regions 22 of the second device 2 from each other. In addition, similarly, the second source region 22 of the second device 2 corresponds to a corresponding one of the first source regions 12 of the first device 1, and the second trench 23 of the second device 2 corresponds to the first source region 12 of the first device 1. The trenches 13 are directly connected. The plurality of second source regions 22 of the second device 2 are concentratedly arranged.

The power device 400 in FIG. 10 differs from the power device 200 shown in FIG. 2 in that there is an additional P+ diffusion region 6 only in the portion of the metal spacing region 5 corresponding to the source region 22 of the second device 2, instead of A further P+ diffusion region 6 is arranged around the second device 2 and there is also no further P+ diffusion region at the source metal lead-out line portion 7 of the second device 2 . Therefore, aspects and details consistent with the power device 200 shown in FIG. 2 will not be repeated here.

FIG. 11 shows a cross-sectional view along G-G in FIG. 10 . 11 is similar to FIG. 5, except that there is no other P+ diffusion region in the metal spacing region 5, because in this exemplary embodiment only the part corresponding to the source region 22 of the second device 2 in the metal spacing region 5 (i.e. In the part perpendicular to the trench) there is an additional P+ diffusion region 6 . In this example embodiment, in a direction parallel to the trench direction, the first device 2 and the second device 2 can be isolated from each other by the trench itself. Specifically, the first device 1 and the second device 2 obtain their respective currents through their respective source regions 12 and 22 via metal contacts 14 and 24, as indicated by I1 and I2, and the active region in the metal spacing region 5 is due to the above Because of the oxide layer 10 there is no current transport, therefore, the first device 1 and the second device 2 are physically separated.

Fig. 12 shows a cross-sectional view along H-H in Fig. 10 . FIG. 12 is similar to FIG. 4 , except that there is no additional P+ diffusion region under the source metal lead-out line portion 7 of the second device 2 . This design, for example, can be adapted to the case where the width (L) of the source metal lead-out line portion 7 of the second device 2 is small (for example, less than 30 μm), because the breakdown voltage of the first device 1 is not high in this case. will be affected.

It should be understood that, although in this exemplary embodiment, no additional P+ diffusion region is provided under the source metal lead-out line portion 7 of the second device 2, in order not to affect the breakdown voltage of the first device 1, it may also be A further P+ diffusion region is provided below the source metal lead-out portion 7 .

FIG. 13 is a plan view illustrating a power device 500 according to an exemplary embodiment of the present disclosure. As shown in FIG. 13 , the same as the power device 200 shown in FIG. 2 , the power device 500 includes a first device 1 and a second device 2 . The second device 2 is embedded in the first device 1 , and the second device 2 is electrically isolated from the first device 1 by the metal spacing region 5 . Furthermore, the first device 1 has a plurality of source regions 12 and a plurality of trenches 13 . These first trenches 13 electrically isolate the plurality of source regions 12 of the first device 1 from each other. The second device 2 has a plurality of source regions 22 and a plurality of trenches 23 . These second trenches 23 electrically isolate the source regions 22 of the second device 2 from each other. In addition, similarly, the second source region 22 of the second device 2 corresponds to a corresponding one of the first source regions 12 of the first device 1, and the second trench 23 of the second device 2 corresponds to the first source region 12 of the first device 1. The trenches 13 are directly connected. The plurality of second source regions 22 of the second device 2 are concentratedly arranged.

The power device 500 in FIG. 13 differs from the power device 200 shown in FIG. 2 in that there is an additional P+ diffusion region 6 only in the metal spacing region 5 and that the additional P+ diffusion region 6 is arranged around the second device 2, but There is no additional P+ diffusion region in the source metal lead-out portion 7 of the second device 2 . Regarding aspects and details consistent with the power device 200 shown in FIG. 2 , details are not repeated here.

FIG. 14 is a plan view illustrating a power device 600 according to an exemplary embodiment of the present disclosure. As shown in FIG. 14 , the same as the power device 400 shown in FIG. 10 , the power device 600 includes a first device 1 and a second device 2 . The second device 2 is embedded in the first device 1 , and the second device 2 is electrically isolated from the first device 1 by the metal spacing region 5 . Furthermore, the first device 1 has a plurality of source regions 12 and a plurality of trenches 13 . These first trenches 13 electrically isolate the plurality of source regions 12 of the first device 1 from each other. The second device 2 has a plurality of source regions 22 and a plurality of trenches 23 . These second trenches 23 electrically isolate the source regions 22 of the second device 2 from each other. In addition, similarly, the second source region 22 of the second device 2 corresponds to a corresponding one of the first source regions 12 of the first device 1, and the second trench 23 of the second device 2 corresponds to the first source region 12 of the first device 1. The trenches 13 are directly connected. Regarding aspects and details consistent with the power device 200 shown in FIG. 2 , details are not repeated here.

The difference between the power device 600 in FIG. 14 and the power device 400 shown in FIG. 10 is that the plurality of second source regions 22 of the second device 2 are not arranged in a concentrated manner, but the plurality of second source regions 22 At least one pair of adjacent second source regions 22 is arranged in such a way that at least one first source region is spaced apart, and at the position between the first source regions of the adjacent second source regions 22 is diffused by another P+ area fill. As shown by the shaded part in the figure, two adjacent second source regions 22 are separated by two first source regions, and another P+ diffusion region 6 is filled at the positions of the two first source regions. It should be understood that in this case, actually this part of the first source region has been replaced by the P+ diffusion region. It should be noted that the number of the first source regions separated from the second source region is not limited, for example, it can be one, two, three. . . , which can be set according to specific requirements.

Fig. 15 shows a sectional view along I-I in Fig. 14 . I-I spans the two second source regions 22, the two first source regions between the two second source regions and the trench therebetween. As shown in FIG. 15 , the two second source regions respectively collect the corresponding current I2 through their respective source region metal contacts 24. There are three trenches between the two source regions 22, and there are three trenches between each two trenches. first source region, but this first source region is filled with another P+ diffusion region.

FIG. 16 shows a cross-sectional view along J-J in FIG. 14 . J-J crosses the second device 2, and both ends are respectively located in the first device 1, one end is just on the metal contact 14 in the source region, while the other end is in the source region, but not on the metal contact. As shown in FIG. 16 , the metal 21 of the second device 2 in the middle and the metal 11 of the first device 1 on both sides are shown in the figure, and the metal 21 and the metal 11 are separated by a metal spacing region 5 . Since one end of the J-J line is right on the metal contact 14 of the first device, the metal contact 24 collects the corresponding current I1 , and the other end is not on the first contact 14 . Additionally, as shown, an additional P+ diffusion region spans the entire cross-sectional width of the second device.

Through the above exemplary embodiments, the current collected by the second device can reflect state changes within a larger chip area. In addition, since there is no metal contact in the part of the first source region separated from the second source region, the state of this part is different from the state of the conventional first device, and the breakdown voltage of the first device can be prevented from decreasing by filling the P+ diffusion region , although some of the active area of the first device is lost, but since the width of the first device is enormous relative to the width of the second device, this loss is not detrimental. This arrangement can be used when the width of the second device is large (for example, above 30 μm). In some cases, for example, when the width of the second device is small (for example, less than 30 μm), only at least one pair of adjacent two second source regions of the second device may be replaced by at least one first source region. spacing without P+ diffusion filling.

The structure of the power device according to the exemplary embodiment of the present disclosure is described above through the embodiments. It is understood that the number of source regions and trenches may be the same or different than the described embodiments. It should also be noted that the structure of the second device is the same as that of the first device in the left half and the right half of the figure, the description about the left half is also applicable to the corresponding structure of the right half, and the description about the right half Also applies to the corresponding structure in the left half.

FIG. 17 is a partial equivalent circuit diagram illustrating a power device according to an exemplary embodiment of the present disclosure. As shown in Figure 17, the first device has a gate G1, a drain D1 and a source S1; the source S2 of the second device and the source of the first device are equivalent to The resistor R, therefore, the first device and the second device are resistively isolated, so that the two can share the external diode D to realize their respective current discharge, so the structure is relatively simple. In FIG. 17 , reference numeral 9 denotes a control circuit, and the control circuit 9 is used to control the operation of the power device, for example, turning on or off the first device and/or the second device.

According to the power device of the above exemplary embodiment, the first device and the second device are coupled and isolated in a unique manner, and the embedding of the second device is smooth and does not cause structural changes to the first device, so there is no Any adverse effect on the current-voltage performance of the first device. In addition, since the additional P+ diffusion region is included in the metal spacing region, the second device can achieve good resistive isolation from the first device, so that the second device can share the same freewheeling diode as the first device to realize current shedding. put. In the case where an additional P+ diffusion region is provided under the source metal lead-out line portion of the second device, it is also possible to prevent the breakdown voltage of the first device from being affected.

The present disclosure also provides a method for preparing a power device. FIG. 18 illustrates a method 1800 of fabricating a power device according to an example embodiment of the present invention. As shown in FIG. 18 , the method 1800 includes: S1801, providing a substrate. Next, in step S1802, the body region of the first device and the body region of at least one second device are formed on the substrate. In step S0803, a plurality of first trenches are formed in the body region of the first device, and a plurality of second trenches are formed in the body region of the second device, wherein the second trenches of the second device and the first The corresponding first trenches of the devices are connected. Finally in step S1804, a plurality of first source regions for the first device and a plurality of second source regions for the second device are formed, wherein the plurality of first source regions are connected to each other by a plurality of first trenches Electrically isolated, a plurality of second source regions are electrically isolated from each other by a plurality of second trenches, wherein the second source region of the second device and the first source region of the first device have a metal spacing region, and the metal spacing region A further P+ diffusion region is formed as a resistive isolation between the second device and the first device.

In some exemplary embodiments, an additional P+ diffusion region may surround the second device. In some exemplary embodiments, the additional P+ diffusion region is located only in the portion of the metal spacer region corresponding to the second source region. In some exemplary embodiments, an additional P+ diffusion region may also be formed under the source metal lead-out portion of the second device.

In some exemplary embodiments, the plurality of second source regions of the second device may be arranged intensively.

In some exemplary embodiments, the substrate may be a P+N substrate, and the power device is an insulated gate bipolar transistor. In some exemplary embodiments, the substrate may be an N+N substrate, and the power device may be a metal oxide semiconductor field effect transistor.

In some exemplary embodiments, each second source region of the second device corresponds to a corresponding one of the first source regions of the first device, and each second trench of the second device may correspond to a corresponding one of the first device. The first trenches are directly connected. In some exemplary embodiments, each second source region of the second device corresponds to a corresponding one of the first source regions of the first device, and each second trench of the second device corresponds to a first source region of the first device. Corresponding to one of the first trenches, and the method 1800 may further include: forming at least one polysilicon structure, the at least one polysilicon structure connecting the second trench of the second device with the corresponding first trench of the first device Pass.

In some exemplary embodiments, the plurality of second source regions of the second device may be arranged in such a manner that at least one pair of adjacent two second source regions is separated by at least one first source region. In some exemplary embodiments, the position of at least one first source region separating at least one pair of adjacent two second source regions among the plurality of second source regions may be filled with another P+ diffusion region.

As above, the power device and the manufacturing method thereof according to the present disclosure are discussed by means of specific embodiments. According to the technology of the present disclosure, the first device and the second device are simultaneously fabricated on the same substrate through the same process, wherein the first device and the second device are well resistively isolated. It is precisely because of this resistive isolation that the first device and at least one second device can share the same freewheeling diode, which greatly reduces the cost of the device.

While at least one exemplary embodiment and method of preparation have been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments are by way of example only, and are not intended to limit the scope, application, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a road map for conveniently implementing the exemplary embodiment of the invention, and it is to be understood that various changes may be made in the function and arrangement of elements described in the exemplary embodiment. without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.

Claims (22)

1. A power device, comprising: a first device having a plurality of first source regions and having a plurality of first trenches electrically isolating the plurality of first source regions from each other; at least one second device having a plurality of second source regions and having a plurality of second trenches electrically isolating the plurality of second source regions from each other, Wherein, the second device is embedded in the first device, and the second groove of the second device communicates with the corresponding first groove of the first device, and the second device There is a metal spacing region between the second source region of the first device and the first source region of the first device, and there is another P+ diffusion region in the metal spacing region as a gap between the second device and the first device. resistive isolation. 2. The power device of claim 1, wherein the further P+ diffusion region surrounds the second device. 3. The power device of claim 1, wherein the further P+ diffusion region is located only in a portion of the metal spacer region corresponding to the second source region. 4. A power device according to claim 2 or 3, wherein the second device comprises a source metal lead-out portion with a further P+ diffusion region underneath. 5. The power device according to claim 1, wherein the plurality of second source regions of the second device are concentratedly arranged. 6. The power device of claim 1, wherein the first device and the second device are formed on a P+N substrate, and the power device is an insulated gate bipolar transistor. 7. The power device of claim 1, wherein the first device and the second device are formed on an N+N substrate, and the power device is a Metal Oxide Semiconductor Field Effect Transistor. 8. The power device according to claim 1, wherein each second source region of the second device corresponds to a corresponding one of the first source regions of the first device, and each of the second device The two second trenches correspond to and directly communicate with the corresponding one of the first trenches of the first device. 9. The power device according to claim 1, wherein each second source region of the second device corresponds to a corresponding one of the first source regions of the first device, and each of the second device A second trench corresponds to a corresponding first trench of the first device, and the second trench of the second device communicates with the first trench of the first device through at least one polysilicon structure . 10. The power device according to claim 1, wherein the plurality of second source regions are arranged in such a manner that at least one pair of adjacent two second source regions is separated by at least one first source region. 11. The power device according to claim 10, wherein the position of at least one first source region separating at least one pair of adjacent two second source regions among the plurality of second source regions is separated by another P+ diffusion region filling. 12. A method for preparing a power device, comprising: provide the substrate; forming a body region of a first device and a body region of at least one second device on a substrate; A plurality of first trenches for the first device are formed in the body region of the first device, and a plurality of second trenches for the second device are formed in the body region of the second device. trenches, wherein the second trenches of the second device communicate with corresponding first trenches of the first device; forming a plurality of first source regions for the first device and a plurality of second source regions for the second device, wherein the plurality of first source regions pass through the plurality of first trenches are electrically isolated from each other, the plurality of second source regions are electrically isolated from each other by the plurality of second trenches, wherein the second source region of the second device and the first source region of the first device There is a metal spacer region in between, and an additional P+ diffusion region is formed in the metal spacer region as a resistive isolation between the second device and the first device. 13. The method of manufacturing a power device according to claim 12, wherein the further P+ diffusion region surrounds the second device. 14. The method for fabricating a power device according to claim 12, wherein the additional P+ diffusion region is only located in a portion of the metal spacing region corresponding to the second source region. 15. A power device according to claim 13 or 14, wherein a further P+ diffusion region is formed under the source metal lead-out portion of the second device. 16. The method for manufacturing a power device according to claim 12, wherein the plurality of second source regions of the second device are arranged in a concentrated manner. 17. The method for preparing a power device according to claim 12, wherein the first device and the second device are formed on a P+N substrate, and the power device is an insulated gate bipolar transistor . 18. The manufacturing method of a power device according to claim 12, wherein the first device and the second device are formed on an N+N substrate, and the power device is a metal oxide semiconductor field effect transistor. 19. The method for fabricating a power device according to claim 12, wherein each second source region of the second device corresponds to a corresponding first source region of the first device, and the second Each second trench of the device corresponds to and directly communicates with a corresponding first trench of the first device. 20. The method for fabricating a power device according to claim 12, wherein each second source region of the second device corresponds to a corresponding first source region of the first device, and the second Each second trench of the device corresponds to a corresponding one of the first trenches of the first device, and the method further comprises: At least one polysilicon structure is formed that communicates the second trench of the second device with the corresponding first trench of the first device. 21. The method for manufacturing a power device according to claim 12, wherein the plurality of second source regions are arranged in such a manner that at least one pair of adjacent two second source regions is separated by at least one first source region cloth. 22. The method for manufacturing a power device according to claim 21, wherein the position of at least one first source region separating at least one pair of adjacent two second source regions among the plurality of second source regions is determined by P+ diffusion area filling.