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CN106773403A - 像素单元结构及显示装置 - Google Patents

像素单元结构及显示装置 Download PDF

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Publication number
CN106773403A
CN106773403A CN201611244006.9A CN201611244006A CN106773403A CN 106773403 A CN106773403 A CN 106773403A CN 201611244006 A CN201611244006 A CN 201611244006A CN 106773403 A CN106773403 A CN 106773403A
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transparent electrode
electrode layer
layer
unit structure
pixel unit
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应见见
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201611244006.9A priority Critical patent/CN106773403A/zh
Priority to US15/329,365 priority patent/US10224348B2/en
Priority to PCT/CN2017/071240 priority patent/WO2018120319A1/zh
Publication of CN106773403A publication Critical patent/CN106773403A/zh
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Abstract

本发明公开了一种像素单元结构及显示装置，属于显示技术领域，解决了现有的显示装置存在开口率较低的技术问题。该像素单元结构包括形成于衬底基板上的薄膜晶体管，以及从下至上依次形成在所述薄膜晶体管上方的第一绝缘层、第一透明电极层、第二绝缘层、第二透明电极层；其中，所述第一透明电极层与所述第二透明电极层形成存储电容。

Description

像素单元结构及显示装置
技术领域
本发明涉及显示技术领域，具体的说，涉及一种像素单元结构及显示装置。
背景技术
随着显示技术的发展，液晶显示屏已经成为最为常见的显示装置。液晶显示屏具有高空间利用率、低功耗、无辐射以及低电磁干扰等优越特性，因此在电视、手机、平板电脑等信息沟通工具中得到广泛使用。
目前，显示科技发展的一个方向是高分辨率和高PPI(Pixel per Inch，每英寸像素数)。在达到精细和细腻的超高清显示的同时，对应的像素尺寸也随着分辨率和PPI的提高而减小。像素尺寸减小，单位面积的金属面积则会增加，相应开口率也会降低，对应的穿透率也通常会有较大幅的降低，成为高分辨率和高PPI像素设计的瓶颈。
如图1所示，以垂直排列型(Vertical Alignment，简称VA)液晶显示器为例，并且色阻层设置在阵列基板上，即采用COA(Color filter On Array)技术的像素结构。图中左侧部分为薄膜晶体管(Thin Film Transistor，简称TFT)结构，右侧部分为提供像素偏转电压的存储电容(Cst)结构，存储电容由第一金属层1和第二金属层2组成，电容值与两层金属的对组面积成正比，由于第一金属层1和第二金属层2为不透光的金属，因此严重影响开口率。另外，数据线(Data line)上方及遮光设计也为不透光设计，采用无数据线黑矩阵(Dataline BM Less，简称DBS)设计的产品如图2所示，数据线20上方采用透明的公共电极30遮光，考虑到穿透率的提升，通常将公共电极30与像素电极40的间距B调整到最小，因此也增加了制程难度。数据线上方的整个不透光区域就为如图2中的A区域：包括公共电极30和两倍的B区域以及像素电极40与屏蔽金属10的重合区域。因此，现有的显示装置的开口率较低，进而导致穿透率较低的技术问题。
发明内容
本发明的目的在于提供一种像素单元结构及显示装置，以解决现有的显示装置存在开口率较低的技术问题。
本发明提供一种像素单元结构，包括形成于衬底基板上的薄膜晶体管，以及从下至上依次形成在所述薄膜晶体管上方的第一绝缘层、第一透明电极层、第二绝缘层、第二透明电极层；
其中，所述第一透明电极层与所述第二透明电极层形成存储电容。
在一种实施方式中，所述第一透明电极层为公共电极，所述第二透明电极层为像素电极。
进一步的是，所述第二透明电极层通过过孔与所述薄膜晶体管的漏极相连。
优选的是，所述公共电极呈平板状，所述像素电极呈梳齿状。
进一步的是，所述第一透明电极层与所述色阻层之间还包括第三绝缘层。
在另一种实施方式中，所述第一透明电极层为像素电极，所述第二透明电极层为公共电极。
进一步的是，所述第一透明电极层通过过孔与所述薄膜晶体管的漏极相连。
优选的是，所述公共电极呈梳齿状，所述像素电极呈平板状。
优选的是，该像素单元结构还包括设置在第一绝缘层和第一透明电极层之间的色阻层。
本发明还提供一种显示装置，包括多个像素单元，且每个所述像素单元具有上述的像素单元结构。
本发明带来了以下有益效果：本发明提供的像素单元结构中，在薄膜晶体管上方形成有第一绝缘层、第一透明电极层、第二绝缘层、第二透明电极层，并且由第一透明电极层与第二透明电极层形成存储电容。因为本发明提供的像素单元结构中，存储电容是由两层透明电极层形成的，所以能够显著提升开口率，从而提高了显示装置整体的穿透率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分的从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚的说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是现有的像素单元结构的示意图；
图2是现有的像素单元结构中遮光区域的示意图；
图3是本发明实施例一提供的像素单元结构的示意图；
图4是本发明实施例一提供的像素单元结构中遮光区域的示意图；
图5是本发明实施例一提供的像素单元结构中电极形状的示意图；
图6是本发明实施例一提供的另一种像素单元结构的示意图；
图7是本发明实施例二提供的像素单元结构的示意图；
图8是本发明实施例二提供的像素单元结构中遮光区域的示意图；
图9是本发明实施例二提供的像素单元结构中电极形状的示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一：
如图3所示，本发明实施例提供一种像素单元结构，包括形成于衬底基板100上的薄膜晶体管110，以及从下至上依次形成在薄膜晶体管上方的第一绝缘层121、色阻层130、第一透明电极层141、第二绝缘层122、第二透明电极层142。其中，第一透明电极层141与第二透明电极层142形成存储电容。
本实施例中，薄膜晶体管110为底栅型薄膜晶体管。薄膜晶体管110包括位于第一金属层的栅极111，覆盖在栅极111上方的栅极绝缘层112，形成于栅极绝缘层112上的半导体层113，形成于半导体层113上的源极114和漏极115，源极114和漏极115位于第二金属层。
本实施例中，第一透明电极层141为公共电极，第二透明电极层142为像素电极，且第二透明电极层142通过过孔与薄膜晶体管110的漏极115相连。
本发明实施例提供的像素单元结构中，通过在色阻层130与第二绝缘层122之间设置第一透明电极层141，作为公共电极，进而利用两层透明电极层形成存储电容，从而能够显著提升开口率。
如图4所示，采用DBS设计时，由于像素电极1420与公共电极1410位于不同的图层，因此相邻的两个像素电极的间距可在B与A之间变动，而不会影响到开口率，可调控的范围大，因此也降低了制程难度。同时数据线1105上方的不透光区域仅为公共电极1410的宽度区域A，从而在保证数据线1105上方遮光效果的基础上，降低了数据线1105上面的遮光区域的面积，增大了开口率，从而可达到提升穿透率的效果。
另一方面，在现有的像素单元结构中，受限于开口率，存储电容的面积一般都不会做的很大，寄生电容Cgs的电容耦合(Feed through)电压V＝ΔV·Cgs/(Cgs+Cst+Clc)，Clc为液晶电容，其中的Cgs/(Cgs+Cst+Clc)较大。由于面板不同区域ΔV会有差异，因此相应的电容耦合电压差异也会被放大，导致像素单元的电压差异较大，进而影响面板的均一性。
本实施例中，因为存储电容由透明电极材料形成，所以不需要考虑穿透率的影响，所以可根据实际情况增大存储电容，电容耦合电压中的Cgs/(Cgs+Cst+Clc)可以较小，从而能够降低面板不同区域电容耦合电压的差异，提升面板均一性。另外，本实施例中在色阻层上形成第一透明电极层，由于第一透明电极层具有致密结构，对色阻具有保护作用，因此还能够防止色组扩散至液晶中而与液晶反应，导致的显示异常。
如图5所示，作为一个优选方案，公共电极1410呈平板状，像素电极1420呈梳齿状，像素电极1420与公共电极1410之间的电压差提供液晶分子的偏转电压。从图5中可以看出，像素电极1420的缝隙基于四个分区设计，使一个像素单元中的液晶分子具有四种不同的偏转方向。
如图6所示，在另一种实施方式中，还可以在第一透明电极层141与色阻层130之间设置第三绝缘层123，利用第三绝缘层123对色阻层130起到进一步的保护作用。
实施例二：
如图7所示，本发明实施例提供一种像素单元结构，包括形成于衬底基板200上的薄膜晶体管210，以及从下至上依次形成在薄膜晶体管上方的第一绝缘层221、色阻层230、第一透明电极层241、第二绝缘层222、第二透明电极层242。其中，第一透明电极层241与第二透明电极层242形成存储电容。其中，薄膜晶体管210为底栅型薄膜晶体管。
本实施例中，第一透明电极层241为像素电极，第二透明电极层242为公共电极，且第一透明电极层241通过过孔与薄膜晶体管210的漏极215相连。
本发明实施例提供的像素单元结构中，通过在色阻层230与第二绝缘层222之间设置第一透明电极层241，作为像素电极，进而利用两层透明电极层形成存储电容，从而能够显著提升开口率。
如图8所示，采用DBS设计时，由于像素电极2410与公共电极2420位于不同的图层，因此相邻的两个像素电极的间距可在B与A之间变动，而不会影响到开口率，可调控的范围大，因此也降低了制程难度。同时数据线2105上方的不透光区域仅为公共电极2420的宽度区域A，从而在保证数据线2105上方遮光效果的基础上，降低了数据线2105上面的遮光区域的面积，增大了开口率，从而可达到提升穿透率的效果。
本实施例中，因为存储电容由透明电极材料形成，所以不需要考虑穿透率的影响，所以可根据实际情况增大存储电容，电容耦合电压中的Cgs/(Cgs+Cst+Clc)可以较小，从而能够降低面板不同区域电容耦合电压的差异，提升面板均一性。另外，本实施例中在色阻层上形成第一透明电极层，由于第一透明电极层具有致密结构，对色阻具有保护作用，因此还能够防止色组扩散至液晶中而与液晶反应，导致的显示异常。
如图9所示，作为一个优选方案，公共电极2420呈梳齿状，像素电极2410呈平板状，像素电极2410与公共电极2420之间的电压差提供液晶分子的偏转电压。从图9中可以看出，公共电极2420的缝隙基于四个分区设计，使一个像素单元中的液晶分子具有四种不同的偏转方向。
此外，本实施例和实施例一虽然都是基于四个分区设计，但本实施例中的公共电极2420与实施例一(如图5所示)中的像素电极1420的形状是互补的。由于本实施例中公共电极2420与彩膜基板电极的电位相同，因此起到屏蔽像素电极2410与公共电极2420重合部分的电位，所以像素电极2410与彩膜基板电极之间电压的有效部分与实施例一相同，从而可达到与实施例一相同的电场分布，达到同样的显示效果。
实施例三：
本发明提供一种显示装置，其中包括多个像素单元，且每个像素单元具有上述实施例一或实施例二提供的像素单元结构。
作为一个优选方案，本发明实施例提供的显示装置为VA液晶显示器，并且采用COA技术，将色阻层设置在阵列基板上。
本发明实施例提供的显示装置，与上述实施例一、实施例二提供的像素单元结构具有相同的技术特征，所以也能解决相同的技术问题，达到相同的技术效果。
可以理解的是，本发明中的实施例是基于VA液晶模式的COA和DBS结构设计来说明提升穿透率，但不用于限定本发明，非COA和非DBS的像素单元结构也可利用本发明中的这种两层透明电极结构形成存储电容的方式提升穿透率。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

1.一种像素单元结构，其特征在于，包括形成于衬底基板上的薄膜晶体管，以及从下至上依次形成在所述薄膜晶体管上方的第一绝缘层、第一透明电极层、第二绝缘层、第二透明电极层；
其中，所述第一透明电极层与所述第二透明电极层形成存储电容。
2.根据权利要求1所述的像素单元结构，其特征在于，所述第一透明电极层为公共电极，所述第二透明电极层为像素电极。
3.根据权利要求2所述的像素单元结构，其特征在于，所述第二透明电极层通过过孔与所述薄膜晶体管的漏极相连。
4.根据权利要求2所述的像素单元结构，其特征在于，所述公共电极呈平板状，所述像素电极呈梳齿状。
5.根据权利要求2所述的像素单元结构，其特征在于，所述第一透明电极层与所述色阻层之间还包括第三绝缘层。
6.根据权利要求1所述的像素单元结构，其特征在于，所述第一透明电极层为像素电极，所述第二透明电极层为公共电极。
7.根据权利要求6所述的像素单元结构，其特征在于，所述第一透明电极层通过过孔与所述薄膜晶体管的漏极相连。
8.根据权利要求6所述的像素单元结构，其特征在于，所述公共电极呈梳齿状，所述像素电极呈平板状。
9.根据权利要求1所述的像素单元结构，其特征在于，还包括设置在第一绝缘层和第一透明电极层之间的色阻层。
10.一种显示装置，其特征在于，包括多个像素单元，且每个所述像素单元具有如权利要求1至9任一项所述的像素单元结构。
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