CN106685778B - Bus multiplexing transmission system - Google Patents
Bus multiplexing transmission system Download PDFInfo
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- CN106685778B CN106685778B CN201510753743.0A CN201510753743A CN106685778B CN 106685778 B CN106685778 B CN 106685778B CN 201510753743 A CN201510753743 A CN 201510753743A CN 106685778 B CN106685778 B CN 106685778B
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 10
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 33
- 230000000630 rising effect Effects 0.000 claims description 20
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/0001—Arrangements for dividing the transmission path
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- Liquid Crystal Display Device Control (AREA)
Abstract
The invention relates to the field of time division multiplexing, in particular to a bus multiplexing transmission system.A first trigger has an input end connected with the output end of a singlechip and an output end connected with a first logic circuit and then connected with a liquid crystal display module for data output; the input end of the second trigger is connected with the output end of the singlechip for receiving the control signal, and the output end of the second trigger is connected with the liquid crystal display module; the input end of the buffer is connected with the liquid crystal display module and used for receiving input data, and the output end of the buffer is connected with the input end of the singlechip; the input end of the decoder is connected with the output end of the single chip microcomputer, and the output end of the decoder is respectively connected with the first trigger, the second trigger and the buffer after passing through the second logic circuit; the single chip microcomputer is also sequentially connected with a latch and an RAM memory for data read-write control. The invention solves the display problem that the OCMJ15 multiplied by 20D Chinese liquid crystal display module needs to adopt an I/O mode, greatly improves the utilization rate of the bus, and simultaneously can reduce the complexity of the circuit and the number of I/O ports.
Description
Technical Field
The invention relates to the field of time division multiplexing, in particular to a bus multiplexing transmission system.
Background
Bus multiplexing refers to the way data and addresses are transmitted simultaneously on one bus. The multiplexing transmission refers to a mechanism for multiple users to share a common channel, and currently, the most common mechanisms are code division multiplexing, time division multiplexing, frequency division multiplexing, and the like.
Because the liquid crystal display module produced by a certain company is a dot matrix liquid crystal display module with Chinese and English characters and a drawing mode, the ROM font code of 512KByte is built in, the liquid crystal display module can display Chinese characters, numeric symbols, English, Japanese, European and other letters, and the display memory of a double layer (TwoPage) is built in. In the character mode, the Chinese can be directly displayed by receiving the standard Chinese character internal code without entering the drawing mode to draw the Chinese, so that much time of a microprocessor can be saved, and the processing efficiency of displaying the Chinese by the liquid crystal is improved. When the module processes the display program by using a 51 single chip microcomputer, an I/O mode is needed. It is known that the port P0 of the single chip can be used as both address/data bus and general I/O port, but when the port P0 is used as address/data bus, it can not be used as general I/O port. Therefore, when using this liquid crystal display module, there is an urgent need for a method of using the P0 port as an address/data multiplexing line and, at some point, as a normal I/O port.
Disclosure of Invention
In view of the deficiencies of the prior art, the present invention provides a bus multiplexing transmission system.
The technical scheme adopted by the invention for realizing the purpose is as follows: a bus multiplexing transmission system is characterized in that the input end of a first trigger is connected with the output end of a single chip microcomputer to receive a control signal, and the output end of the first trigger is connected with a liquid crystal display module after being connected with a first logic circuit to output data;
the input end of the second trigger is connected with the output end of the singlechip for receiving the control signal, and the output end of the second trigger is connected with the liquid crystal display module for data output;
the input end of the buffer is connected with the liquid crystal display module and used for receiving input data, and the output end of the buffer is connected with the input end of the singlechip;
the input end of the decoder is connected with the output end of the singlechip and receives the trigger control signal, and the output end of the decoder is respectively connected with the first trigger, the second trigger and the buffer after passing through the second logic circuit to perform trigger control;
the single chip microcomputer is also sequentially connected with a latch and an RAM memory for data read-write control.
The first flip-flop is a 6 rising edge D flip-flop.
The second flip-flop is an 8 rising edge D flip-flop.
The buffer is a 3-state 8-bit buffer.
The first logic circuit is a not gate circuit.
The second logic circuit is an NOR gate circuit.
The invention has the following beneficial effects and advantages:
the programming is simple, the code conversion efficiency is improved, the utilization rate of the bus is greatly improved, the complexity of the circuit can be reduced, and the number of I/O ports is reduced.
Drawings
FIG. 1 is a block diagram of the system connections of the present invention;
FIG. 2 is a schematic diagram of the connections of the decoder chip 74LS139 and the NOR chip 74LS32 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Fig. 1 shows a system connection block diagram of the present invention.
The signal flow of the system is divided into five parts: (1) the data/address bus of the single chip is connected with an eight-D latch with tristate buffer output, and the output of the latch is connected with an external RAM to jointly form a read-write part of the external RAM. (2) The data/address bus of the single chip is connected with a decoder, the output of the decoder is connected with a logic NOR gate, the output of the NOR gate is respectively connected with a control chip and a data writing-in and writing-out chip of the liquid crystal display module, and a trigger control part of the system is formed together. (3) The data/address bus of the single chip is connected with the input of the 6 rising edge D trigger chip, and the signal directly controls the liquid crystal display module through the D trigger and the logic NOT gate circuit. (4) The data/address bus of the single chip is connected with the D trigger of 8 rising edges, and the D trigger is connected with the data bus of the liquid crystal display module to form a data input part of the system. (5) The data/address bus of the single chip is connected with a 3-state 8-bit buffer, and the buffer is connected with the data bus of the liquid crystal display module to form a data reading part of the system.
The address/data bus of the single chip microcomputer is connected with the input of the 8 rising edge D trigger chip, the output of the 3-state 8-bit buffer chip and the input signal of the 6 rising edge D trigger chip, and the output of the 8 rising edge D trigger chip, the input of the 3-state 8-bit buffer chip and the data bus of the liquid crystal display module are connected together. The output of the 6 rising edge D trigger is matched with a logic not gate to provide a control signal for the liquid crystal display module, and the decoder is matched with a logic not gate to provide a trigger signal for the 8 rising edge D trigger, the 3-state 8-bit buffer and the 6 rising edge D trigger. The bus multiplexing transmission function is completed, and the writing and reading of the display data of the liquid crystal display module are realized.
The liquid crystal display module is an OCMJ15 × 20D Chinese liquid crystal display module produced by Zhaoqing Jinpeng industry Co., Ltd, which is a dot matrix liquid crystal display module with Chinese and English characters and drawing modes, has a built-in ROM font code of 512Kbyte, can display Chinese characters, numerical symbols, English, Japanese, European characters and other letters, and has a built-in display memory with double graphic layers (TwoPage). In the character mode, the Chinese can be directly displayed by receiving the standard Chinese character internal code without entering the drawing mode to draw the Chinese, so that much time of a microprocessor can be saved, and the processing efficiency of displaying the Chinese by the liquid crystal is improved.
In order to transfer the data latched at the output terminal of U10 to the data line of U14 and display the data correctly, the write timing of U14 must be strictly observed, and the control signals of U14 must be correct. For example, if a character represented by 0x30 is to be displayed, in the first step, 0x30 is written into the 4000H address; second, let the respective control signals of U14: CS1 is low, RD is high, RS is low, WR is low. This requires the U12 to write different data at the corresponding clock edge, i.e. write 0x2C, 0x28, 0x2A, etc. to C000H address; thirdly, delaying for a period of time; the fourth step makes the respective control signals of U14: WR goes high, RS goes high, CS1 goes high, i.e., data of 0x28, 0x2C, 0x04, etc. are written to C000H address. The reason why the CS2 signal and the RST signal are not involved is that the CS2 is connected to the power supply and always kept in a high state, while the RST signal must always be kept in a high state, otherwise, the RST signal is always kept in a reset state and cannot normally operate.
In order to read out the data of the U14, that is, the data at the output end of the U11 is read into the single chip or processed, the read-out timing of the U14 must be strictly observed, and the control signals of the U14 are correct. For example, if the data 0xff in U14 is to be read out, in the first step, the data is read into U11, that is, the data 0xff of U11 is written to the 4000H address; second, let the respective control signals of U14: CS1 is low, WR is high, RS is low, RD is low. I.e., writing 0x2C, 0x08, 0x09, etc. data to the C000H address; thirdly, delaying for a period of time; fourthly, transferring the data 0xff of the 4000H address to an intermediate variable; in the fifth step, RD is high, RS is high, and CS1 is high, i.e. 0x08, 0x0C, 0x04, etc. data are written to C000H address. The CS2 signal and RST signal are not involved, and the reason is the same as that for writing data, and thus are not described again.
After the port P0 of the single chip microcomputer is used as an address/data bus, in order to enable the single chip microcomputer to have the function of a general I/O port at some moment, a pull-up resistor is required to be externally connected, and high level output is achieved.
In order to enable the port P0 to have the function of a general I/O port at some moments, an 8-rising-edge D flip-flop 74LS374 chip is adopted in the scheme and used as a data input bus of a liquid crystal display module; a 3-state 8-bit buffer 74LS244 chip is adopted as a data readout bus of the liquid crystal display module; the 6 rising edge D flip-flop 74LS174 chip is used as the control signal of the LCD module. The input and output terminals of the three chips are respectively connected together by buses. The edge clock signals of the three chips are controlled by the decoding chip 74LS139 and the OR-NOT circuit 74LS 32.
For convenience of explanation, the numbers of the chips used are as follows: the 51 single chip microcomputer is U1, the 74LS373 is U2, the external RAM chip 62256 is U3, the 74LS139 is U4, the 74LS32 is U5, the 74LS374 is U10, the 74LS244 is U11, the 74LS174 is U12, the 74LS04 is U13, and the liquid crystal display module is U14.
FIG. 2 shows a schematic diagram of the connection of the decoder chip 74LS139 and the NOR chip 74LS32 according to the present invention.
The input of U4 terminates P2.6 and P2.7 of U1, i.e., A14 and A15 of the upper address. The control signal of U10 is/WE 1, the control signal of U11 is/RD 4, and the control signal of U12 is/WE 3. To make the clock control signal of U10 low requires that the 5 pin output of U4 be low, i.e., a14 is high and a15 is low, while ensuring that the write signal WR of U1 is low, so that data is only written to the 4000H address. To make the control signal of U11 low, it is necessary to make the output of pin 11 of U4 low, i.e., a14 is high and a15 is low, and to ensure that the read signal RD of U1 is low, so that the control signal RD4 of U11 is low only when data at the address of the monolithic computer 4000H is read.
The U10 chip is used as a data write chip of U14, the input ends D0-D7 of the U10 chip are directly connected with the P0 port of U1, and the output ends Q0-Q7 of the U10 chip are connected with the data buses DB 0-DB 7 of U14. When the tri-state enable control terminal OE is low, Q0-Q7 are in normal logic state and can be used to drive the load or bus. When OE is high, Q0-Q7 are in high impedance state, and are not used for driving the bus or loads of the bus, but the logic operation inside the latch is not affected. When the clock end CLK pulse rises, the outputs Q0-Q7 change with the inputs D0-D7.
The U11 chip is used as a data reading chip of U14, the input end of the U11 chip is connected with a data bus of U14, the output end of the U11 chip is directly connected with a P0 port of U1, and a control pin 1G is connected with a control pin 2G and then connected with a pin 11Y of U5. From the connection relationship of the schematic diagram, the control terminal of the chip is determined by the read pin RD of U1 and the upper two bits of the address a14 and a 15.
The input ends D1-D6 of the U12 chip are directly connected with the P0.0-P0.5 of the U1, and the output ends are connected with all control pins of the U14. Q1 is connected to pin 6 of U14 as a read control signal through an inverter; q2 is connected to pin 5 of U14 as a write control signal through an inverter; q3 is connected directly to pin 5 of U14 as an access register control signal; the Q4 is connected to the 7 pin of the U14 through an inverter to serve as an enabling signal of the module; q5 is connected to pin 11 of U14 as a reset signal through an inverter; q6 is connected to the OE pin of U10 via an inverter as a control signal for U10.
The port P0 of the MCS-51 singlechip is used as an address/data bus. Taking the MCS-51 single chip microcomputer connected with an external RAM memory as an example, the port P0 of the single chip microcomputer is used as a low-order address/data bus, and the port P2 is used as a high-order 8-order address bus. The ALE of the MCS-51 single chip microcomputer is an address latch signal, and two positive pulses are output in each machine period. When accessing off-chip memory, the falling edge is used to control an externally connected address latch to latch the lower 8-bit address output from port P0. The address latch adopts a common address latch chip 74LS 373: when the latch is used, OE is enabled to be low level, and when the latch enable end C is enabled to be high level, the states of the output Q0-Q7 are the same as the states of the input ends D1-D7; when C generates negative jump, the data of the input ends D0-D7 are locked into Q0-Q7. The ALE signal of the 51 single chip microcomputer is directly connected with the C of the 74LS 373. The connection schematic diagram of the single chip microcomputer and the latch is shown in fig. 1. The input ends D1-D7 are connected to the P0 port of the single chip, the output end provides low 8-bit address, and the C end is connected to the address latch enable signal ALE of the single chip. The output enable terminal OE is connected to ground, indicating that the output tri-state gate is always open.
The address/data bus of U1 is connected to the inputs of U10, the output of U11, the input signals of U12, the output of U10, the input of U11, and the data bus of U14. The output of U12 cooperates with U13 to provide control signals to U14 and U4 cooperates with U5 to provide trigger signals to U10, U11, U12. The bus multiplexing transmission function is completed, and the writing and reading of the display data of the U14 are realized.
Claims (1)
1. A bus multiplexing transmission system characterized by: the input end of the 6 rising edge D trigger is connected with the output end of the singlechip and receives a control signal, and the output end of the 6 rising edge D trigger is connected with the NOT gate circuit and then connected with the liquid crystal display module for data output;
the input end of the 8 rising edge D trigger is connected with the output end of the singlechip to receive a control signal, and the output end of the D trigger is connected with the liquid crystal display module to output data;
the input end of the 3-state 8-bit buffer is connected with the liquid crystal display module and used for receiving input data, and the output end of the 3-state 8-bit buffer is connected with the input end of the singlechip;
the input end of the decoder is connected with the output end of the singlechip and receives a trigger control signal, and the output end of the decoder is respectively connected with a 6 rising edge D trigger, an 8 rising edge D trigger and a 3-state 8-bit buffer through an NOR gate circuit to perform trigger control;
the single chip microcomputer is also sequentially connected with an eight-D latch and an RAM memory for data read-write control;
the data/address bus of the single chip is connected with an eight-D latch with tristate buffer output, the output of the eight-D latch is connected with the RAM memory, and the eight-D latch and the RAM memory together form a read-write part of the RAM memory; the data/address bus of the single chip is connected with a decoder, the output of the decoder is connected with a NOR gate, the output of the NOR gate is respectively connected with a control chip and a data writing-in and writing-out chip of the liquid crystal display module, and a trigger control part of the system is formed by the NOR gate and the data writing-in and writing-out chips; the data/address bus of the single chip microcomputer is connected with the input of the 6 rising edge D trigger, and the signal directly controls the liquid crystal display module through the 6 rising edge D trigger and the NOT gate circuit; the data/address bus of the single chip microcomputer is connected with the D trigger with the rising edge of 8, and the D trigger with the rising edge of 8 is connected with the data bus of the liquid crystal display module to form a data input part of the system; the data/address bus of the singlechip is connected with a 3-state 8-bit buffer, and the buffer is connected with the data bus of the liquid crystal display module to form a data reading part of the system;
the decoder is a decoding chip 74LS 139;
the eight D latch is an address latch chip 74LS 373.
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| CN101122783A (en) * | 2007-09-20 | 2008-02-13 | 成都方程式电子有限公司 | SCM memory system |
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|---|---|---|---|---|
| CN1558305A (en) * | 2004-01-19 | 2004-12-29 | 中国科学院计算技术研究所 | A bus type universal serial bus multiplexer |
| US8341300B1 (en) * | 2007-08-30 | 2012-12-25 | Virident Systems, Inc. | Systems for sustained read and write performance with non-volatile memory |
| CN101122783A (en) * | 2007-09-20 | 2008-02-13 | 成都方程式电子有限公司 | SCM memory system |
| CN103139054A (en) * | 2011-11-29 | 2013-06-05 | 合肥爱默尔电子科技有限公司 | Gateway based on konnex (KNX) protocol and digital addressable lighting interface (DALI) protocol |
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