CN106569040B - Single Event Transient Pulse Width Measurement Circuits, Integrated Circuits and Electronic Devices - Google Patents

Abstract

The invention relates to the technical field of electrical pulse width measurement, and relates to a single-particle transient pulse width measurement circuit. The input terminal of a latch circuit is connected to the input terminal of a signal to be measured; Both the first input terminal and the second input terminal of the storage circuit are connected to the input terminal of the signal to be measured; when the single-event transient pulse width measurement circuit includes two or more delay latch circuits, start from the second-level delay latch circuit The first input end of the delay latch circuit of each stage is connected to the first output end of the delay latch circuit of the previous stage, and the second input end of the delay latch circuit of each stage is connected to the input end of the signal to be measured; After the terminal is connected to the single-event transient pulse signal to be tested, the latch circuit flips and drives the at least one stage delay latch circuit to flip over, and the output terminal of the latch circuit and the first stage of each delay latch circuit in the at least one stage delay latch circuit are flipped. The two output terminals are used as the signal output terminal of the single-particle transient pulse width measurement circuit.

Description

Single Event Transient Pulse Width Measurement Circuits, Integrated Circuits and Electronic Devices

technical field

The invention relates to the technical field of electrical pulse width measurement, in particular to a single-particle transient pulse width measurement circuit, an integrated circuit and an electronic device.

Background technique

With the development of technology in aerospace, military and other fields, more and more integrated circuits need to work in a radiation environment. The effects of radiation on integrated circuits are mainly divided into two categories: single-event effects and total dose effects. The effect produced by the immediate effect of the radiation effect after the circuit. The single event effects can be subdivided into the following three categories: single event soft error effects, potentially dangerous effects and single event hard error effects.

Among them, the single-event soft error effects include single-event inversion effects, single-event transient effects, single-event multi-flipping effects, etc., which can interfere with circuit nodes in a short time. Potentially dangerous effects include single-event latch-up, which, if not controlled, can lead to single-event burnout of the chip. Single event hard error effects include displacement damage, etc., which can completely disable the transistors in the chip. However, the single-event transient effect is a common main factor affecting the performance of the chip. When the chip is placed in a radiation environment, the surrounding energy particles will be injected into the chip, and a certain number of electrons will be generated on the trajectory of the ionizing radiation energy particles. , hole pairs, they are absorbed by the circuit node under the action of the electric field, changing the node level, if there is no feedback loop, then when the single-particle action time ends, the node level will return to the original value, so that in the A pulse signal is generated in the circuit.

For the research and reinforcement of the single event effect, an effective test environment must be built to accurately measure the characteristics such as the width of the transient pulse signal. Among them, the test environment often chooses the ground irradiation experiment, which simulates the real cosmic space radiation environment by bombarding the chip to be tested by simulating the generation of cosmic ray particles. When measuring the pulse signal width, depending on the type and energy of the incident particles, the generated single-particle pulse signal level maintenance time is also different, and the pulse width can range from tens of ps to more than a thousand ps.

If a traditional oscilloscope or logic analyzer and other testing equipment is used to measure the single-event transient pulse width, the frequency requirements of the equipment are very high, the testing cost is high, and the implementation is very difficult. If the on-chip circuit is used for testing, the existing pulse width measurement methods often measure the pulse signal by sampling the pulse signal by externally inputting a high-frequency signal, and the capture accuracy will be limited by the frequency and performance of the sampling signal. , The waveform characteristics are very good sampling signal, therefore, the measurable range is small.

SUMMARY OF THE INVENTION

The invention solves the technical problem of the small measurable range of the single-particle transient pulse width measuring circuit in the prior art by providing a single-particle transient pulse width measuring circuit, an integrated circuit and an electronic device.

The embodiment of the present invention provides a single-event transient pulse width measurement circuit, including a signal input end to be measured, a latch circuit and at least one stage of delay latch circuit;

The input end of the latch circuit is connected to the input end of the signal to be measured;

Both the first input terminal and the second input terminal of the first-stage delay latch circuit in the at least one-stage delay latch circuit are connected to the input terminal of the signal to be tested;

When the single-event transient pulse width measurement circuit includes more than two stages of delay latch circuits, starting from the second stage of delay latch circuits, the first input end of each stage of delay latch circuits is connected to the previous stage of delay latch circuits. The first output end of the circuit is connected, and the second input end of each stage of the delay latch circuit is connected to the input end of the signal to be measured;

Wherein, after the single-event transient pulse signal to be tested is connected to the input end of the signal to be tested, the single-event transient pulse signal to be tested drives at least one stage of the delay latch circuit to flip in sequence, and the latch The output end of the circuit and the second output end of each delay latch circuit in the at least one-stage delay latch circuit are used as the signal output end of the single-event transient pulse width measurement circuit.

Preferably, the latch circuit is a two-input RS latch, and the set input terminal of the two-input RS latch is connected to the input terminal of the signal to be measured.

Preferably, the delay latch circuit includes a delay sub-circuit and a latch sub-circuit, an output end of the delay sub-circuit is connected to a first set input end of the latch sub-circuit, and an output end of the latch sub-circuit is connected to the first set input end of the latch sub-circuit. The second set input terminal is connected with the said input terminal of the signal to be tested.

Preferably, the delay subcircuit is composed of even-numbered inverters in cascade.

Preferably, the latch subcircuit is a three-input RS latch.

Preferably, the reset terminal of the latch circuit and the reset terminals of all delay latch circuits are connected to the same reset signal.

Based on the same inventive concept, an embodiment of the present invention also provides an integrated circuit, including the single-event transient pulse width measurement circuit as described above.

Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, including the above-mentioned integrated circuit.

One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

In the present invention, after the single-event transient pulse signal to be tested is connected to the input end of the signal to be tested, the single-event transient pulse signal to be tested drives the at least one stage of the delay latch circuit to be reversed in sequence, and the output of the latch circuit is reversed. The terminal and the output terminals of each delay latch circuit in the at least one-stage delay latch circuit are used as the signal output terminal of the single-event transient pulse width measurement circuit. The pulse width of the state pulse signal can be expanded by increasing the number of stages of the delay latch circuit. It can meet the different test requirements of different stages of delay latch circuits. In addition, the present invention does not need an external input clock signal, so there is no requirement for an external input clock signal.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

1 is a schematic diagram of the circuit structure of a single-particle transient pulse width measurement circuit in a first embodiment of the present invention;

2 is a schematic diagram of the circuit structure of a single-particle transient pulse width measurement circuit in a second embodiment of the present invention;

3 is a schematic diagram of a waveform when a single-particle transient pulse width measurement circuit works in an embodiment of the present invention;

4 is a schematic diagram of a circuit structure of a two-input RS latch in an embodiment of the present invention;

5 is a schematic diagram of a circuit structure of a three-input RS latch in an embodiment of the present invention;

FIG. 6 is a schematic diagram of a circuit structure of a delay subcircuit in an embodiment of the present invention.

Among them, 100 is a latch circuit, 101 is a delay latch circuit, 1011 is a latch sub-circuit, 1012 is a delay sub-circuit, 11 is the first PMOS tube, 12 is the second PMOS tube, 13 is the third PMOS tube, 14 is the fourth PMOS tube, 15 is the fifth PMOS tube, 16 is the sixth PMOS tube, 17 is the seventh PMOS tube, 18 is the eighth PMOS tube, 19 is the ninth PMOS tube, 21 is the first NMOS tube, 22 is the The second NMOS tube, 23 is the third NMOS tube, 24 is the fourth NMOS tube, 25 is the fifth NMOS tube, 26 is the sixth NMOS tube, 27 is the seventh NMOS tube, 28 is the eighth NMOS tube, and 29 is the first NMOS tube Nine NMOS transistors, 31 is the tenth PMOS transistor, 32 is the eleventh PMOS transistor, 41 is the tenth NMOS transistor, and 42 is the eleventh NMOS transistor.

Detailed ways

In order to solve the technical problem of the small measurable range of the single-event transient pulse width measuring circuit in the prior art, the present invention provides a single-event transient pulse width measuring circuit, an integrated circuit and an electronic device.

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a single-event transient pulse width measurement circuit. As shown in FIG. 1 , the single-event transient pulse width measurement circuit includes a signal input terminal to be measured, a latch circuit 100 and at least one stage of delay latch circuit 101. The input end of the latch circuit 100 is connected to the input end of the signal to be tested, and the first input end and the second input end of the first stage of the delay latch circuit in at least one stage of the delay latch circuit 101 are both connected to the input end of the signal to be tested , when the single-event transient pulse width measurement circuit includes more than two stages of delay latch circuits 101, starting from the second stage of the delay latch circuit, the first input end of each stage of the delay latch circuit is connected to the previous stage of the delay latch circuit The first output end of the circuit 101 is connected, and the second input end of each stage of the delay latch circuit is connected to the input end of the signal to be tested.

In the present invention, after the single-event transient pulse signal to be tested is connected to the input terminal of the signal to be tested, the single-event transient pulse signal to be tested drives at least one stage of the delay latch circuit 101 to flip in sequence, and the latch circuit 100 The output terminal of , and the second output terminal of each delay latch circuit 101 in at least one stage of delay latch circuit 101 are used as the signal output terminal of the single-event transient pulse width measurement circuit. According to the level of each signal output terminal, the pulse width of the single-event transient pulse signal to be measured can be inversely deduced. Those skilled in the art can set the number of stages of the delay latch circuit 101 according to the actual measurement requirements, and the delay latch circuit The larger the number of stages of 101, the larger the range of the measurement signal, and by changing the delay time of the delay latch circuit 101, the test accuracy of the corresponding stage can be adjusted to meet the different test requirements of the delay latch circuit 101 of different stages , In addition, the present invention does not require an external input clock signal, so there is no requirement for an external input clock signal.

In a specific embodiment of the present invention, as shown in FIG. 2 , the latch circuit 100 may be a two-input RS latch, and the two-input RS latch includes a set input terminal (S terminal), a reset input terminal ( R terminal), Q output terminal and The output end, the set input end of the two-input RS latch is connected to the input end of the signal to be measured, and the Q output end of the latch circuit 100 is the signal output end of the single-event transient pulse width measurement circuit.

The delay latch circuit 101 in the present invention includes a delay sub-circuit 1012 and a latch sub-circuit 1011 . The input end of the delay sub-circuit 1012 of the first-stage delay latch circuit is connected to the input end of the signal to be tested, and the output end of the delay sub-circuit 1012 of the first-stage delay latch circuit is connected to the latch sub-circuit of the first-stage delay latch circuit. The first input end of the circuit 1011 is connected, and the second input end of the latch sub-circuit 1011 of the first stage delay latch circuit is connected to the input end of the signal to be tested. Starting from the second stage delay latch circuit, the input end of the delay subcircuit 1012 of the delay latch circuit 101 is connected to the output end of the delay subcircuit 1012 of the previous stage delay latch circuit 101, and the delay of each stage delay latch circuit is The output end of the sub-circuit 1012 is connected to the first input end of the latch sub-circuit 1011 of the delay latch circuit 101 of this stage, and the second input end of the latch sub-circuit 1011 of the delay latch circuit of each stage is connected to the Signal input connection.

Further, the latch sub-circuit 1011 may be a three-input RS latch, and the three-input RS latch includes a first set input terminal (S1 terminal), a second set input terminal (S2 terminal), and a reset input terminal (R terminal), Q output and output. Specifically, the three-input RS latch is a three-input NOR gate basic RS latch. The three-input RS latch has two stable states. Under the condition that the input signal is maintained for a long enough time, the three-input RS latch can flip from one stable state to another stable state, and the output signal level changes. For example, when the input signals of the three input terminals of the three-input RS latch change and maintain for a long enough time, the output level of the three-input RS latch will change. Specifically, when the three-input RS latch changes When the first set input and the second set input are not all high, the Q output of the three-input RS latch is low, The output terminal is high level, when the reset input terminal of the three-input RS latch is low level, and the first set input terminal and the second set input terminal are both high level, the Q output terminal is high level, The output terminal is low level. When the reset input terminal of the three-input RS latch is low level, and the first set input terminal and the second set input terminal are not all high level, the Q output terminal and the second set input terminal are not high level. The output level remains unchanged.

Further, the input end of the delay sub-circuit 1012 of the first-stage delay latch circuit is connected to the input end of the signal to be tested, and the output end of the delay sub-circuit 1012 of the first-stage delay latch circuit is connected to the lock of the first-stage delay latch circuit The first set input terminal of the storage sub-circuit 1011 is connected, and the second set input terminal of the latch sub-circuit 1011 of the first stage delay latch circuit is connected to the input terminal of the signal to be tested. Starting from the second stage delay latch circuit, the input end of the delay subcircuit 1012 of each stage delay latch circuit is connected to the output end of the delay subcircuit 1012 of the previous stage delay latch circuit 101. The output terminal of the delay sub-circuit 1012 is connected to the first set input terminal of the latch sub-circuit 1011 of the delay latch circuit 101 of the stage, and the second set input terminal of the latch sub-circuit 1011 of the delay latch circuit of each stage is connected Connect to the input terminal of the signal to be tested. The Q output terminal of the latch circuit 100 and the Q output terminal of each latch sub-circuit 1011 in the at least one stage delay latch circuit 101 are used as the signal output terminal of the single event transient pulse measurement circuit. In the present invention, the delay sub-circuit 1012 may be composed of even-numbered inverters in cascade.

In the present invention, in order to ensure that the latch circuit 100 and the delay latch circuit 101 can maintain a stable state before the single event transient pulse signal to be tested changes, the reset terminal of the latch circuit 100 and the reset terminal of all the delay latch circuits 101 are reset. The same reset signal, ie, RESET, is connected to the terminal, and all the latch circuits 100 are reset under the unified RESET.

In the following, the present invention will describe in detail the working principle of the single-event transient pulse width measurement circuit of the present invention in combination with a specific input signal, wherein the single-event transient pulse width measurement circuit includes a three-stage delay latch circuit 101, and the input is to be To measure the single-event transient pulse signal, out1 is the signal output by the output terminal of the latch circuit 100, out2 is the signal output by the output terminal of the first stage delay latch circuit, and out3 is the output terminal output of the second stage delay latch circuit , and out4 is the signal output by the output end of the third-stage delay latch circuit 101 , and the working waveform of each signal in the single-event transient pulse width measurement circuit is shown in FIG. 3 .

Specifically, in the working process, in the initial state, all the latch circuits 100 are reset under the unified RESET. At this time, the input input of the input terminal of the signal to be tested is low level, and the reset terminal input of all the latch circuits 100 is at a low level. When the signal is at a high level, the signals output by all the output terminals of the latch circuits 100 are 0, that is, out1, out2, out3, out4 and out5 are all 0. At t=20.5ns, the input keeps the low level unchanged, and the RESET changes to the low level. At this time, the signals output by all the latch circuits 100 remain unchanged, that is, out1, out2, out3, out4 and out5 are all 0 . At t=50ns, the input generates a high-level pulse with a pulse width of 200ps. It can be seen from the simulation that the high-level pulse is sufficient to drive the latch circuit 100 to turn over, so that out1 becomes a high level.

Among them, input drives the delay subcircuit 1012 in the first stage delay latch circuit at the same time, and the signal in2 output from the output end of the delay subcircuit 1012 is delayed by Δt2 than that of input. The time period when input is high level is short Δt2, but Δt2 can still meet the minimum time requirement for driving the latch sub-circuit 1011 in the first-stage delay latch circuit to flip over, so the lock in the first-stage delay latch circuit The sub-circuit 1011 is flipped so that out2 becomes a high level. The signal in3 output from the output end of the delay sub-circuit 1012 in the second-stage delay latch circuit is delayed by a delay time Δt3 of the delay sub-circuit 1012 in the second delay latch circuit 101 compared to in2, therefore, in3 and input are both high The time of the level will be Δt2+Δt3 shorter than the time when the input is high. The simulation shows that this period of time is not enough to drive the latch sub-circuit 1011 in the third-stage delay latch circuit 101 to flip, so out4 is at a low level. Therefore, the time period when out3 and the input signal are at a high level at the same time is 0. Therefore, the latch sub-circuit 1011 in the fourth-stage delay latch circuit 101 cannot be reversed.

The above analysis shows that, starting from the first stage of the delay latch circuit, the time when the first set input terminal and the second set input terminal of the latch sub-circuit 1011 in each stage of the delay latch circuit 101 are at a high level at the same time will be Decrease step by step until it becomes 0. And the wider the pulse width of the input input signal, that is, the longer the input signal remains at a high level, the more latches can be driven to flip, so that the number of flipped signals in out2,...,outn is more.

In the present invention, by changing the input pulse width and using circuit simulation to observe the output of the latch circuits 100 at all levels, the corresponding table between the input pulse width and the logic level of the output signal can be obtained, see Table 1 below. , the pulse width of the single-event transient pulse signal to be measured can be inversely deduced according to the inversion of the latch circuit 100 detected in the actual measurement and in accordance with Table 1 below.

Table 1

The circuit structure of the latch circuit 100 in the present invention and the circuit structure of the delay sub-circuit 1012 in the delay latch circuit 101 will be described in detail below:

In the present invention, the two-input RS latch is a NOR gate RS latch. As shown in FIG. 4 , the two-input RS latch includes a first PMOS transistor 11 , a second PMOS transistor 12 , and a third PMOS transistor 13 , a fourth PMOS transistor 14 , a first NMOS transistor 21 , a second NMOS transistor 22 , a third NMOS transistor 23 and a fourth NMOS transistor 24 . The source terminal of the first PMOS transistor 11 and the source terminal of the third PMOS transistor 13 are respectively connected to the power supply, and the gate terminal of the first PMOS transistor 11 and the gate terminal of the first NMOS transistor 21 are respectively connected to the reset terminal of the two-input RS latch. The drain terminal of the first PMOS transistor 11 is connected to the source terminal of the second PMOS transistor 12, and the gate terminal of the second PMOS transistor 12 and the gate terminal of the second NMOS transistor 22 are respectively connected to the two-input RS latch. The output terminal is connected, the first connection node between the drain terminal of the first NMOS transistor 21 and the drain terminal of the second NMOS transistor 22 is connected to the drain terminal of the second PMOS transistor 12, and the first connection node is also latched with the two input RS The Q output terminal of the third PMOS transistor 13 and the gate terminal of the third NMOS transistor 23 are respectively connected to the set terminal of the two-input RS latch, and the drain terminal of the third PMOS transistor 13 is connected to the fourth PMOS transistor The source terminal of the transistor 14 is connected, the gate terminal of the fourth PMOS transistor 14 and the gate terminal of the fourth NMOS transistor 24 are respectively connected to the Q output terminal of the two-input RS latch, and the drain terminal of the third CMOS transistor is connected to the fourth CMOS transistor. The second connection node between the drain terminals is connected to the drain terminal of the fourth PMOS transistor 14, and the second connection node is also connected to the two-input RS latch. The output terminals are connected, and the source terminal of the first NMOS transistor 21 , the source terminal of the second NMOS transistor 22 , the source terminal of the third NMOS transistor 23 and the source terminal of the fourth NMOS transistor 24 are grounded respectively.

Wherein, in the above-mentioned two-input RS latches, all PMOS transistors have a width of 1.92 micrometers and a length of 0.13 micrometers, and all NMOS transistors have a width of 0.64 micrometers and a length of 0.13 micrometers.

Of course, the two-input RS latch may also adopt other two-input RS latch circuit structures having a signal inversion function other than FIG. 4 , which is not limited in this application.

In the present invention, the three-input RS latch may have a circuit structure as shown in FIG. 5, and the three-input RS latch includes a fifth PMOS transistor 15, a sixth PMOS transistor 16, a seventh PMOS transistor 17, and an eighth PMOS transistor tube 18, ninth PMOS tube 19, fifth NMOS tube 25, sixth NMOS tube 26, seventh NMOS tube 27, eighth NMOS tube 28 and ninth NMOS tube 29, the source terminal of the fifth PMOS tube 15, the sixth The source terminal of the PMOS transistor 16 and the source terminal of the seventh PMOS transistor 17 are respectively connected to the power supply, the gate terminal of the fifth PMOS transistor 15 and the gate terminal of the fifth NMOS transistor 25 are respectively connected to the reset terminal of the three-input RS latch, The drain terminal of the fifth PMOS transistor 15 is connected to the source terminal of the eighth PMOS transistor 18, and the gate terminal of the sixth PMOS transistor 16 and the gate terminal of the seventh NMOS transistor 27 are respectively connected with the first set terminal of the three-input RS latch. connection, the gate terminal of the seventh PMOS transistor 17 and the gate terminal of the ninth NMOS transistor 29 are respectively connected to the second set terminal of the three-input RS latch, and the drain terminal of the seventh PMOS transistor 17 is connected to the ninth PMOS transistor 19. The third connection node between the source terminals is connected to the drain terminal of the sixth PMOS transistor 16, and the gate terminal of the eighth PMOS transistor 18 and the gate terminal of the sixth NMOS transistor 26 are respectively connected to the three-input RS latch. The output terminal is connected, and the fourth connection node between the drain terminal of the eighth PMOS transistor 18, the drain terminal of the fifth NMOS transistor 25 and the drain terminal of the sixth NMOS transistor 26 is connected to the Q output terminal of the three-input RS latch, The fifth connection node between the drain terminal of the ninth PMOS transistor 19 , the drain terminal of the seventh NMOS transistor 27 , and the drain terminal of the eighth NMOS transistor 28 and the three-input RS latch The output terminal is connected, the gate terminal of the ninth PMOS transistor 19 and the gate terminal of the eighth NMOS switch are respectively connected to the Q output terminal of the three-input RS latch, and the source terminal of the seventh NMOS transistor 27 is connected to the drain terminal of the ninth NMOS transistor 29. The terminals are connected, the source terminal of the fifth NMOS transistor 25 , the source terminal of the sixth NMOS transistor 26 , the source terminal of the eighth NMOS transistor 28 and the source terminal of the ninth NMOS transistor 29 are grounded respectively.

Wherein, in the above-mentioned three-input RS latch, all PMOS transistors have a width of 1.92 micrometers and a length of 0.13 micrometers, and all NMOS transistors have a width of 0.64 micrometers and a length of 0.13 micrometers.

Of course, the three-input RS latch may also adopt other three-input RS latch circuit structures having a signal inversion function other than FIG. 5 , which is not limited in this application.

In the present invention, the delay subcircuit 1012 may have a circuit structure as shown in FIG. 6 , and the delay subcircuit 1012 includes a tenth PMOS transistor 31 , an eleventh PMOS transistor 32 , a tenth NMOS transistor 41 and an eleventh NMOS transistor 41 , the source terminal of the tenth PMOS transistor 31 and the source terminal of the eleventh PMOS transistor 32 are connected to the power supply, and the source terminal of the tenth NMOS transistor 41 and the source terminal of the eleventh NMOS transistor 42 are grounded respectively. The connection node between the gate terminal and the gate terminal of the eleventh NMOS transistor 41 is the input terminal of the delay sub-circuit 1012, and the connection node between the drain terminal of the eleventh PMOS transistor 32 and the drain terminal of the eleventh NMOS transistor 42 is The output terminal of the delay sub-circuit 1012 is the connection node between the drain terminal of the tenth PMOS transistor 31 and the drain terminal of the tenth NMOS transistor 41 and the gate terminal of the eleventh PMOS transistor 32 and the gate terminal of the eleventh NMOS transistor 42 connection between nodes.

Of course, the delay sub-circuit 1012 may also adopt the circuit structure of the delay sub-circuit 1012 with a signal inversion function other than that shown in FIG. 6 , which is not limited in this application.

Based on the same inventive concept, an embodiment of the present invention also provides an integrated circuit, including the single-event transient pulse width measurement circuit as described above. For the structure of the single-event transient pulse width measurement circuit, refer to the previous embodiment, which is not described here. Repeat.

Based on the same inventive concept, an embodiment of the present invention further provides an electronic device including the above-mentioned integrated circuit.

The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages:

In the present invention, after the single-event transient pulse signal to be tested is connected to the input end of the signal to be tested, the single-event transient pulse signal to be tested drives the at least one stage of the delay latch circuit to be reversed in sequence, and the output of the latch circuit is reversed. The terminal and the output terminals of each delay latch circuit in the at least one-stage delay latch circuit are used as the signal output terminal of the single-event transient pulse width measurement circuit. The pulse width of the state pulse signal can be expanded by increasing the number of stages of the delay latch circuit. It can meet the different test requirements of different stages of delay latch circuits. In addition, the present invention does not need an external input clock signal, so there is no requirement for an external input clock signal.

Although preferred embodiments of the present invention have been described, additional changes and modifications to these embodiments may occur to those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the preferred embodiment and all changes and modifications that fall within the scope of the present invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (6)

1. a single-particle transient pulse width measurement circuit, is characterized in that, comprises the signal input terminal to be measured, latch circuit and multistage delay latch circuit, and each stage delay latch circuit comprises delay subcircuit and latch subcircuit ; The input end of the latch circuit is connected to the input end of the signal to be measured, the latch circuit is a two-input RS latch, and the set input end of the two-input RS latch is connected to the signal to be measured. input connection; The input end of the delay sub-circuit of the first-stage delay latch circuit in the multi-stage delay latch circuit is connected to the input end of the signal to be tested, and the output end of the delay sub-circuit of the first-stage delay latch circuit is connected to the first set input end of the latch sub-circuit of the first-stage delay latch circuit, and the second set input end of the latch sub-circuit of the first-stage delay latch circuit is connected to the Signal input terminal connection; In the multi-stage delay latch circuit, starting from the second stage of the delay latch circuit, the input end of the delay subcircuit in each stage of the delay latch circuit is connected to the output of the delay subcircuit in the previous stage of the delay latch circuit The output end of the delay subcircuit in each stage of the delay latch circuit is connected with the first set input end of the latch subcircuit in the delay latch circuit of this stage, and the latch subcircuit in the delay latch circuit of each stage is connected The second set input end of the circuit is connected to the input end of the signal to be measured; Wherein, after the single-event transient pulse signal to be tested is connected to the input terminal of the signal to be tested, the single-event transient pulse signal to be tested drives the multi-stage delay latch circuit to turn over in sequence, and the lock The Q output terminal of the storage circuit and the Q output terminal of the latch sub-circuits of each delay latch circuit in the multi-stage delay latch circuit are used as the signal output terminal of the single-event transient pulse width measurement circuit. 2 . The single-event transient pulse width measurement circuit according to claim 1 , wherein the delay subcircuit is composed of even-numbered inverters in cascade. 3 . 3 . The single-event transient pulse width measurement circuit according to claim 1 , wherein the latch sub-circuit is a three-input RS latch. 4 . 4 . The single-event transient pulse width measurement circuit according to claim 1 , wherein the reset terminal of the latch circuit and the reset terminals of all delay latch circuits are connected to the same reset signal. 5 . 5. An integrated circuit, characterized by comprising the single-event transient pulse width measurement circuit according to any one of claims 1-4. 6. An electronic device, comprising the integrated circuit of claim 5.