CN103983834B - Single-particle transient pulse signal amplitude measuring circuit - Google Patents

Abstract

A transient pulse amplitude measuring circuit, comprising: a preprocessing circuit, having a single event pulse receiving end, a reset input end, a preprocessing signal output end, a detection signal output end, and a correct or false signal output end, and generating a preprocessing signal according to the input pulse, And the first-level detection signal, and give a positive and false signal to judge whether the input pulse width meets the test requirements; at least one level of detection circuit, each level of detection circuit is composed of a buffer and a basic RS latch of an NOR gate, with a buffer input terminal , the buffer output end, the reset signal input end and the detection signal output end, the buffer input signal is attenuated through the buffer. The input end of the buffer in the detection circuit of the first stage is connected with the preprocessing signal, and the input end of the buffer in the detection circuits of the other stages is connected with the output end of the upper stage buffer. The invention can measure the amplitude of the single particle transient pulse signal, and detect whether the input pulse width is within the test range, the input load is small, and the measurement range and precision are adjustable.

Description

A Single Event Transient Pulse Signal Amplitude Measurement Circuit

technical field

The invention relates to the field of space radiation effect detection and the field of high-frequency electric pulse measurement, in particular, the invention relates to a single-event transient pulse signal pulse amplitude measurement circuit.

Background technique

Aerospace technology is an important symbol to measure a country's modernization level and comprehensive national strength. Integrated circuits are the core of spacecraft, and their performance and functions have become one of the main indicators for measuring the performance of various spacecraft.

The single event effect refers to the radiation damage effect caused by ionizing radiation in sensitive areas inside the chip caused by high-energy particles existing in radiation environments such as aerospace and ground. Ionizing radiation produces dense electron/hole pairs on the particle trajectory. When these electron/hole pairs are collected by circuit nodes, they may change the normal working state of the circuit, resulting in data errors, malfunctions, chip burnout and other serious consequences.

With the continuous reduction of the feature size of integrated circuits, the continuous acceleration of operating speed, and the continuous decline of operating voltage, circuits are becoming more and more sensitive to single event effects. Single event effects have become one of the hot issues that seriously threaten the safety and reliability of spacecraft.

In a radiation environment, the bombardment of particles on the circuit will generate electron/hole pairs on its trajectory, and the electron/hole pairs will be absorbed by the circuit nodes, which will generate an instantaneous narrow pulse signal, that is, a single-particle transient pulse signal. If this signal travels down the combinatorial path to a latch or other type of sequential element, it will cause a single-event upset, which creates a circuit error. Sufficient pulse width and pulse amplitude are the necessary conditions for the single event transient pulse signal to propagate in the combined channel. Therefore, the measurement of the single event transient pulse signal width and amplitude will help in-depth study of the mechanism of single event effects It is of great significance to ensure the safety and reliability of spacecraft by measuring the radiation sensitive parameters of various spaceborne electronic components and integrated circuits and evaluating their resistance to single event effects.

Since the pulse width of the single event transient pulse signal is very narrow, it is directly measured by equipment such as an oscilloscope or a logic analyzer, which requires very high equipment bandwidth and accuracy. Single particle research is a key confidential field abroad, and such equipment is prohibited from exporting. Domestic products are often difficult to meet the measurement requirements, and the measurement is difficult.

Contents of the invention

Aiming at this current situation, the present invention provides a kind of transient pulse amplitude measuring circuit, comprising:

The preprocessing circuit has a single event pulse receiving terminal, a reset input terminal, a preprocessing signal output terminal, a detection signal output terminal, and an error signal output terminal. According to the input pulse, a preprocessing signal and a first-level detection signal are generated, and the error signal is given. The signal judges whether the input pulse width meets the test requirements; at least one level of detection circuit, each level of detection circuit is composed of a buffer and a NOR gate basic RS latch, with a buffer input terminal, a buffer output terminal, a reset signal input terminal and The detection signal output terminal attenuates the buffer input signal through the buffer. When the attenuated signal is enough to drive the latch, the detection signal outputs a high level. When the input signal is not enough to drive the latch, the detection signal outputs a low level. flat.

Wherein, the input end of the buffer in the detection circuit of the first stage is connected with the preprocessing signal, and the input end of the buffer in the detection circuits of the other stages is connected with the output end of the upper stage buffer.

Wherein, the measurement circuit is characterized in that, when the pulse width of the signal to be detected is sufficient, the preprocessing signal generated by the preprocessing circuit has nothing to do with the pulse width of the input signal, but is only related to the pulse amplitude, and the higher the pulse amplitude of the signal to be detected, The higher the pulse amplitude of the preprocessing signal, the wider the pulse width and the stronger the driving ability.

Wherein, the positive and false signal is used to detect whether the pulse width of the input signal meets the minimum pulse width required for the measurement, the detection signal being high level indicates that the input signal pulse width is sufficient, and the measurement result is correct, and the detection signal being low level indicates the input signal pulse width Insufficient, the measurement result is wrong.

Wherein, the buffer in the circuit is formed by cascading an even number of inverters, and the pulse width of the output signal of the buffer is smaller than the pulse width of the input signal of the buffer.

Wherein, the S terminal of the basic RS latch of the NOR gate in each stage of the detection circuit is connected to the output terminal of the buffer of this stage, the R terminal is connected to the reset input terminal, and the Q terminal is connected to the detection signal output terminal.

The detection circuits at all levels adopt the same structure size. According to the true and false signals and the signal levels output by the detection circuits at all levels, the amplitude of the measured pulse signal is inversely deduced. By adjusting the power supply voltage, the structure and size of the buffer in the detection circuit, the measurement range and measurement accuracy can be adjusted.

The single event transient pulse signal amplitude measurement circuit provided by the present invention can measure the single event transient pulse signal amplitude, can automatically detect whether the input pulse width is within the test range, and the circuit input load is small. By adjusting the power supply voltage or detecting The structure and size of the buffer used in the circuit can adjust the measurement range and measurement accuracy.

Description of drawings

Fig. 1 is a schematic structural diagram of a pulse signal amplitude measuring circuit in one embodiment of the present invention;

Fig. 2 is a schematic structural diagram of a preprocessing circuit in an embodiment of the present invention;

Fig. 3 (a) is the output voltage adjustable inverter adopted in the preprocessing circuit in one embodiment of the present invention, and Fig. 3 (b) is the three-input RS lock adopted in the preprocessing circuit in one embodiment of the present invention Schematic diagram of the memory structure;

Fig. 4 is a schematic diagram of the working waveform of the preprocessing circuit in one embodiment of the present invention;

Fig. 5 is a schematic diagram of the buffer structure in the detection circuit in one embodiment of the present invention;

Fig. 6 is a schematic diagram of the working waveform of the detection circuit in one embodiment of the present invention;

FIG. 7 is a schematic diagram of the overall working waveform of a single event transient pulse measured by the single event transient pulse signal amplitude measurement circuit in an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a single event transient pulse signal amplitude measurement circuit provided by an embodiment of the present invention. According to an embodiment of the present invention, the circuit includes a preprocessing circuit 101 and a 16-stage detection circuit; the preprocessing circuit 101 is used to generate a preprocessing signal in, a detection signal out1, and a right and wrong signal right; the pulse input terminal of the preprocessing circuit is connected to be tested Single event transient pulse signal input, reset input terminal connected to reset signal reset, output preprocessing signal in, detection signal out1 and right and wrong signal right; 16-level detection circuit, each detection circuit is latched by buffer and NOR gate basic RS The output terminal of the buffer is connected to the input terminal of the latch S, the reset signal reset is connected to the input terminal of the latch R, and the output terminals of the latches of each level are the output terminals of the detection signals out2 to outn. Except that the input end of the buffer in the detection circuit of the first stage is connected with the preprocessing signal in, the input end of the buffer in the detection circuits of the other stages is connected with the output end of the buffer of the upper stage.

Fig. 2 is the schematic structural diagram of the preprocessing circuit that an embodiment of the present invention provides, and this circuit comprises NOR gate basic RS latch 201, delay circuit 202 and 206, NAND gate 203, inverter 205, output high power Level adjustable inverter 204 and three-input RS latch 207 . Among them, the R input terminal of 201 is connected to the reset signal reset, the S input terminal of 201 is connected to the single event transient pulse signal input, and the Q output terminal of 201 is the detection signal out1. output Connect the output signal of the delay circuit 202, 202 With out1 as two input ends (interchangeable) of NAND gate circuit 203, the output signal in1 of 203 is as the input signal of inverter 204 and 205, wherein output high level adjustable inverter 204, its voltage The input terminal is connected to the input signal input, and the output signal of 204 is the preprocessed signal in. The output signal o1 of 205 is connected to the inverter 206, and the output signal o1_d of 206 is connected with the input terminals S1 and S2 of the three-input RS latch 207 (interchangeable), and o1 is connected to the R input terminal of 207, and the Q terminal of 207 The output signal at the terminal is the right and wrong signal right.

FIG. 3( a ) is a circuit diagram of an inverter 204 with an adjustable output high level, and FIG. 3( b ) is a circuit diagram of a three-input RS latch 207 . The input terminal of 204 is in, the output terminal is out, and the voltage input terminal is in_vdd. Then when in is low level, the output amplitude of out is the same as in_vdd, when in is high level, out is low level. When the input signal S1 and S2 of the latch 207 are both 1, and the input signal R is 0, the output Q is 1, is 0. When S1 and S2 are not all 1, if R is 1, the output Q is 0, is 1, if R is 0, the output remains unchanged.

In the preprocessing circuit, the delay circuit 202 is composed of 8 inverters cascaded, and the delay circuit 206 is composed of 4 inverters cascaded, except for the pmos tube whose gate is connected to the Q and S signals in 201. The ratio is 0.89 microns/0.35 microns, the width-to-length ratio of the pmos tubes in the NAND gate 203 is 0.89 microns/0.35 microns, the width-to-length ratios of the other pmos tubes are 2.3 microns/0.35 microns, and the width-to-length ratios of all nmos tubes are 0.89 microns/0.35 Micron.

Fig. 4 is a schematic diagram of the working waveform diagram of the preprocessing circuit 101 provided by an embodiment of the present invention, the power supply voltage is 3.3V, and the figures are output signal right, intermediate signal o1_d, intermediate signal o1, output signal in, intermediate signal from top to bottom in the figure in1, output signal out1, intermediate signal q1_d, intermediate signal q1_, input signal input, input signal reset.

From 370 nanoseconds to 372 nanoseconds in the simulation time, the reset signal is at high level, the latch 201 is reset, out1 is at low level, q1_ is at high level, q1_d is at high level, in1 is at high level, in is a low level, o1 is a low level, o1_d is a low level, and the right signal remains unchanged.

At the simulation time of 375 nanoseconds, the input signal outputs a high-level signal with a pulse width of 1.5 nanoseconds and an amplitude of 3.3V. This signal drives 201 to set, making the out1 signal high and the q1_ signal low level, and output q1_d through 202 to generate an in signal and an intermediate signal o1 with a pulse width of about 470 picoseconds. The o1 signal is delayed by 206 to output o1_d, and the two function as input to generate the right signal. Since the falling edges of input and o1_d are later than the falling edges of o1, when the o1 signal changes from high level to low level, there is a period of time It is satisfied that o1 is low level, o1_d and input are high level, so that the output result right becomes high level. After that, o1_d and input become low level, and right remains high level.

Obviously, when the input pulse width is insufficient, the falling edge of input is earlier than the falling edge of o1. At this time, after the end of input, there is a period of time to meet, input is 0, o1_d and o1 are 1, so that right outputs low level, and then o1_d and o1 becomes 0, right remains low. That is to say, if the input pulse width is wide enough, the output right is high level, and if the input pulse width is insufficient, the output right is low level. Through the right signal, it can be detected whether the pulse width of the input signal is too narrow and whether the measurement result is correct.

Changing the input width and amplitude simulation shows that when the input signal width is sufficient, the generated preprocessing signal in has nothing to do with the input pulse width, but only with the input pulse amplitude. And the higher the input pulse amplitude, the higher the in pulse amplitude, and the wider the pulse width; for example, the input amplitude is 3.3V, the width is 1.5 nanoseconds, the output in signal amplitude is 3.3V, and the width is 475 picoseconds; the input amplitude is 3.3 V, the width is 2.5 nanoseconds, the output in signal amplitude is 3.3V, and the width is 475 picoseconds; when the input amplitude is 2V, and the width is 1.5 nanoseconds, the output in signal amplitude is 2V, and the width is 327 picoseconds.

In this embodiment, the detection circuits at all levels adopt the same structure size. The buffer used in the detection circuit is composed of two inverters with different sizes. The structure is shown in Figure 5, wherein the width-to-length ratio of the pmos tube 401 connected to the buffer input signal delay_in is 2.1 microns/0.35 microns, and the nmos tube The width to length ratio of 402 is 2 microns/0.35 microns. The width-to-length ratio of the pmos tube 403 connected to the buffer output signal delay_out is 2 microns/0.35 microns, and the width-to-length ratio of the nmos tube 404 is 2.1 microns/0.35 microns. The width-to-length ratios of the pmos tubes in the RS latch 302 used in the detection circuit are both 2.3 microns/0.35 microns, and the width-to-length ratios of the nmos tubes are both 0.89 microns/0.35 microns.

6 is a schematic diagram of working waveforms of the detection circuit provided by an embodiment of the present invention. From top to bottom, reset signal reset, buffer input signal delay_in, buffer output signal delay_out, and result output signal out. The power supply voltage is 3.3V, when the delay_in pulse width is 500 picoseconds, the output signal delay_out pulse width is about 480 picoseconds, and the output signal pulse width is smaller than the input signal pulse width. delay_out drives the RS latch to flip, and the output signal out of the Q terminal becomes 1.

The propagation of the pulse signal in the combined circuit is affected by both the pulse width and the pulse amplitude. The wider the pulse width, the higher the pulse amplitude, and the stronger the driving ability. Since the driving capability of in is determined by the input pulse amplitude, the input pulse amplitude can be inversely deduced according to the driving conditions of the out1 to outn signals.

FIG. 7 shows a schematic diagram of the overall working waveform of a transient pulse measured by the transient pulse signal amplitude measurement circuit in an embodiment of the present invention. From top to bottom are: detection output signal out17, out16, ..., out1, right and wrong signal right, single event transient pulse input signal input, voltage waveform of reset signal reset. The power supply voltage is 3.3V, reset starts from 10 nanoseconds, and outputs a pulse with a width of 2 nanoseconds every 20 nanoseconds. The pulse amplitude is 3.3V. The input starts from 15 nanoseconds, and outputs a pulse with a width of 1.5 nanoseconds every 20 nanoseconds. The second pulse, the pulse amplitude starts from 1.9V, the step size is 0.1V, and increases to 3.3V. The simulation results are shown in Table 1.

When right is 1, according to the output levels of out1 to out17, the measured pulse amplitude can be inversely deduced. For example, when the output right is 1, while out1 to out12 are 1, and out13 to out17 are 0, the input voltage is 2.7V. By adjusting the power supply voltage, the structure and size of the buffer in the detection circuit, etc., the measurement range and measurement accuracy can be adjusted.

Table 1

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the above-mentioned embodiment, and any other changes, modifications, substitutions, combinations, Simplifications should be equivalent replacement methods, and all are included in the protection scope of the present invention.

Claims (6)

1. a transient pulse amplitude measurement circuitry, including:

Pretreatment circuit (101), has single-particle reception of impulse end, the RESET input, preprocessed signal defeated Go out end, detect signal output part and signal output part of correcting errors, produce preprocessed signal according to input pulse, And first order detection signal, and provide positive error signal and judge whether input pulse width meets test request；

At least level detection circuitry (102), every grade of testing circuit is by buffer and nor gate basic RS latch Constitute, there is buffer input, buffer output end, reset signal input and detection signal output End, is decayed to buffer input signals by buffer, when attenuated signal be enough to drive latch Time, detection signal output high level, when input signal is not enough to drive latch, detection signal output Low level；

Wherein in first order testing circuit, buffer input connects preprocessed signal, remaining detection electricity at different levels In road, buffer input connects upper level buffer output end；

Wherein, when input signal pulse width is enough, the preprocessed signal that pretreatment circuit (101) produces Unrelated with input signal pulse width, and only relevant with pulse amplitude, and input signal pulse amplitude is the highest, Preprocessed signal pulse amplitude is the highest, and pulse width is the widest, and driving force is the strongest；

Wherein, described positive error signal is used for detecting whether pwm input signal meets the required minimum pulse width of measurement, Detection signal is that high level explanation pwm input signal is enough, and measurement result is correct, and detection signal is low electricity Put down and show that pwm input signal is not enough, measurement result mistake.

Measuring circuit the most according to claim 1, it is characterised in that the buffer in testing circuit by Even number of inverters cascade is constituted, and wherein buffer output signal pulse width is less than buffer input signals Pulse width.

Measuring circuit the most according to claim 1, it is characterised in that nor gate in every grade of testing circuit Basic RS latch S end connects this grade of buffer output end, and R end connects the RESET input, and Q end connects Detection signal output part.

Measuring circuit the most according to claim 1, it is characterised in that described testing circuits at different levels use Identical physical dimension.

Measuring circuit the most according to claim 1, it is characterised in that according to described positive error signal with each The signal level of level testing circuit output, the surveyed pulse amplitude of anti-release.

Measuring circuit the most according to claim 1, it is characterised in that by regulating power source voltage, inspection The structure of buffer, size in slowdown monitoring circuit, regulation measurement scope and certainty of measurement.