CN106548745A - A kind of array base palte, display floater and display device - Google Patents
A kind of array base palte, display floater and display device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/13454—Drivers integrated on the active matrix substrate
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Abstract
The invention discloses a kind of array base palte, display floater and display device, by arranging display control unit between every adjacent two grid lines in every grid line group, in first resolution, all display control units are used for two grid lines for disconnecting.In second resolution, at least part of display control unit in same grid line group is used for two grid lines for turning on connection, and first resolution is more than second resolution.Due in second resolution, two grid lines of at least part of display control unit conducting connection in same grid line group, make that there is on the grid line of conducting identical scanning signal, so that the corresponding pixel of grid line with same scan signal is opened to be input into identical data signal simultaneously, to show identical grey scale pattern, therefore display driver chip can export scanning signal to specific part grid line with precise control without carrying out substantial amounts of data processing again, you can realize the function that low resolution shows.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
A display generally includes a display panel having a plurality of rows of gate lines and pixels corresponding to each row of gate lines, a gate driving circuit for driving the pixels to be turned on, a source driving circuit for inputting data signals to the turned-on pixels, and a display driving chip for controlling the gate driving circuit to output scan signals. The display driving chip outputs various control signals to the grid driving circuit, so that the grid driving circuit inputs scanning signals to each row of grid lines in sequence to control the pixels corresponding to each row of grid lines to be turned on, and data signals are input into the corresponding pixels, so that the display realizes the image display function. At present, a display generally comprises a high-resolution display and a low-resolution display, the image display effect of the high-resolution display is better than that of the low-resolution display, but the high-resolution display means that the power consumption is also larger. However, in actual display, high resolution display may not improve the display effect of some pictures, but power consumption is increased significantly, and low resolution display may reduce power consumption. In order to perform low-resolution display, the display driving chip needs to precisely control the gate driving circuit to output a scanning signal to a specific portion of gate lines so as to control specific portions of pixels to be turned on to input a data signal, so that the display realizes a low-resolution display function. This results in a large amount of data processing required by the display driver chip, which in turn results in problems of special customization, long data processing time and high power consumption required by the display driver chip.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a display device, which are used for solving the problems that a display driving chip needs to be specially customized, the data processing time is long and the power consumption is high due to the fact that a display driving chip needs to perform a large amount of data processing when low-resolution display is performed in the prior art.
Therefore, an embodiment of the present invention provides an array substrate, including: a plurality of gate lines; dividing all the grid lines into a plurality of grid line groups, wherein each grid line group comprises at least two adjacent grid lines; the array substrate further includes: the display control unit is connected between every two adjacent grid lines in each grid line group;
when the first resolution is reached, each display control unit is used for disconnecting the two connected grid lines;
at the second resolution, at least part of the display control units in the same grid line group are used for conducting the two connected grid lines; wherein the first resolution is greater than the second resolution.
Preferably, in the array substrate provided in the embodiment of the present invention, the array substrate further includes: a drive control unit;
the driving control unit is used for controlling the two grid lines which are disconnected by each display control unit at the first resolution, and controlling at least part of the two grid lines which are connected by the display control units in the same grid line group at the second resolution.
Preferably, in the array substrate provided in the embodiment of the present invention, each of the display control units is connected to the driving control unit through a first control signal line corresponding to each of the display control units; or,
all the display control units are connected with the drive control unit through the same second control signal line; or,
and the part of the display control units in the same grid line group are connected with the drive control unit through the same third control signal line, and the rest of the display control units are connected with the drive control unit through the fourth control signal lines or the same fifth control signal lines which are in one-to-one correspondence.
Preferably, in the array substrate provided in the embodiment of the present invention, one display control unit is connected between every two adjacent gate lines in each gate line group, and the display control units are located at the same end of the connected gate lines; or,
and two display control units are connected between every two adjacent grid lines in each grid line group and are respectively positioned at two ends of the connected grid lines.
Preferably, in the array substrate provided in an embodiment of the present invention, the display control unit includes: a switching transistor; wherein,
the grid electrode of the switch transistor is used for receiving a driving control signal output by the driving control unit, and the source electrode and the drain electrode of the switch transistor are respectively connected with two corresponding adjacent grid lines.
Preferably, in the array substrate provided in the embodiment of the present invention, at the second resolution, all the display control units in the same gate line group are configured to conduct two connected gate lines.
Preferably, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a gate driving circuit at least at one end of each gate line;
the grid driving circuit comprises cascaded multi-stage shift register units, and the shift register units at each stage are Mth-stage shift register units respectively; m is an integer greater than or equal to 1, and the output ends of the shift register units of each stage are correspondingly connected with one grid line one by one; or,
the array substrate further includes: the grid driving circuits are respectively positioned at two ends of each grid line; wherein,
the gate driving circuit at one end of each of the gate lines includes: the shift register units at each stage are 2N-1 stage shift register units respectively; the gate driving circuit at the other end of each gate line includes: the shift register unit comprises cascaded multiple stages of shift register units, wherein each stage of shift register unit is a 2N-stage shift register unit; and N is an integer greater than or equal to 1, and the output ends of the shift register units of each stage are connected with one grid line in a one-to-one correspondence mode.
Preferably, in the array substrate provided in the embodiment of the present invention, the array substrate further includes: a display driving chip;
when the first resolution ratio is reached, the display driving chip is used for controlling all the shift register units to sequentially output scanning signals;
when the second resolution is higher than the first resolution, the display driving chip is used for controlling the kN- (k-n) th-stage shift register unit to sequentially output scanning signals; wherein k is the total number of the gate lines in each gate line group, and n is an integer less than or equal to k.
Correspondingly, the embodiment of the invention also provides a display panel which comprises any one of the array substrates provided by the embodiment of the invention.
Correspondingly, the embodiment of the invention also provides a display device which comprises the display panel provided by the embodiment of the invention.
The invention has the following beneficial effects:
according to the array substrate, the display panel and the display device provided by the embodiment of the invention, the display control unit is arranged between every two adjacent grid lines in each grid line group, and at the first resolution, the two connected grid lines are disconnected by the display control unit, so that each grid line can be mutually independent, each grid line can have respective scanning signals, and the pixels corresponding to each grid line input required data signals, so that each pixel can display respective gray scale patterns. At the second resolution, the two gate lines connected with each other are conducted by at least part of the display control units, so that the mutually conducted gate lines have the same scanning signals, pixels corresponding to the gate lines with the same scanning signals are simultaneously turned on to input the same data signals, and the pixels corresponding to the gate lines with the same scanning signals display the same gray scale pattern. Therefore, high-resolution display with high resolution can be realized by adopting the first resolution for display, and low-resolution display can be realized by adopting the second resolution for display, so that the conversion function of high-resolution display and low-resolution display can be realized. Compared with the prior art for realizing low-resolution display, the array substrate provided by the embodiment of the invention has the advantages that after the display driving chip and the grid driving circuit are assembled, as the conducted grid lines have the same scanning signals, the display driving chip can accurately control the scanning signals to be output to the specific part of the grid lines without carrying out a large amount of data processing, and the function of low-resolution display can be realized. And the structural design of the array substrate is slightly changed, so that the process can be reduced, and the manufacturing cost can be saved.
Drawings
Fig. 1a is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 1b is a second schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 1c is a third schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 1d is a fourth schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 1e is a fifth schematic structural view of an array substrate according to an embodiment of the invention;
fig. 2a is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2b is a second schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 2c is a third schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;
FIG. 4a is a timing diagram of the input/output of the shift register unit of FIG. 3 at a first resolution;
FIG. 4b is a timing diagram of the input/output of the shift register unit shown in FIG. 3 at the second resolution.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of an array substrate, a display panel and a display device according to embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The size, shape and the like of each graph in the drawings do not reflect the real proportion of the array substrate, and the purpose is only to schematically illustrate the content of the invention.
An embodiment of the present invention provides an array substrate, as shown in fig. 1a to 1e, including: a plurality of gate lines 100; dividing all the gate lines 100 into a plurality of gate line groups 200, wherein each gate line group 200 comprises at least two adjacent gate lines; the array substrate further includes: a display control unit 300 connected between every two adjacent gate lines 100 in each gate line group 200;
at the first resolution, each display control unit 300 is configured to disconnect two gate lines 100;
at the second resolution, at least a part of the display control units 300 in the same gate line group 200 are used to turn on the two connected gate lines 100; wherein the first resolution is greater than the second resolution.
In the array substrate provided by the embodiment of the invention, the display control unit is arranged between every two adjacent gate lines in each gate line group, and at the first resolution, the two connected gate lines are disconnected by the display control unit, so that each gate line can be mutually independent, each gate line can have a respective scanning signal, and the pixels corresponding to each gate line input the required data signals, so that each pixel can display a respective gray scale pattern. At the second resolution, the two gate lines connected with each other are conducted by at least part of the display control units, so that the mutually conducted gate lines have the same scanning signals, pixels corresponding to the gate lines with the same scanning signals are simultaneously turned on to input the same data signals, and the pixels corresponding to the gate lines with the same scanning signals display the same gray scale pattern. Therefore, high-resolution display with high resolution can be realized by adopting the first resolution for display, and low-resolution display can be realized by adopting the second resolution for display, so that the conversion function of high-resolution display and low-resolution display can be realized. Compared with the prior art for realizing low-resolution display, the array substrate provided by the embodiment of the invention has the advantages that after the display driving chip and the grid driving circuit are assembled, as the conducted grid lines have the same scanning signals, the display driving chip can accurately control the scanning signals to be output to the specific part of the grid lines without carrying out a large amount of data processing, and the function of low-resolution display can be realized. And the structural design of the array substrate is slightly changed, so that the process can be reduced, and the manufacturing cost can be saved.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, all the gate lines may be equally divided into a plurality of gate line groups. For example, as shown in fig. 1a and 1e, each gate line group 200 may include two gate lines 100. Or as shown in fig. 1b, each gate line group 200 may include three gate lines 100. Or as shown in fig. 1c, each gate line group 200 may include four gate lines 100. Or as shown in fig. 1d, each gate line group 200 may include five gate lines 100.
Alternatively, in a specific implementation, all the gate lines may be arbitrarily divided into a plurality of gate line groups by using a non-average division method. That is, two gate lines may be included in one gate line group, and three gate lines may be included in the other gate line group. Or, the first partial gate line group may include two gate lines, the second partial gate line group may include three gate lines, and the third partial gate line group may include four gate lines. Of course, in practical applications, the division of the gate line group needs to be determined according to practical application conditions, and is not limited herein. The following describes an array substrate provided in an embodiment of the present invention, taking an average division of gate line groups as an example.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, at the second resolution, a part of the display control units in the same gate line group is used to connect two connected gate lines. Specifically, as shown in fig. 1b, when each gate line group 200 includes three gate lines 100, at the second resolution, one of the two display control units 300 in the same gate line group 200 is used to turn on two connected gate lines, so two of the three gate lines 100 in each gate line group 200 can be turned on to have the same scan signal, and the pixels corresponding to the two turned on gate lines 100 can be turned on at the same time to input the same data signal, so that two rows corresponding to the two turned on gate lines 100 and two pixels in the same column are equivalent to displaying a gray scale pattern of one pixel, and the second resolution can be smaller than the first resolution. Alternatively, as shown in fig. 1c, when each gate line group 200 includes four gate lines 100, at the second resolution, two adjacent gate lines 100 in three display control units 300 in the same gate line group 200 are used to turn on two connected gate lines 100, so that three adjacent gate lines 100 in the four gate lines 100 in each gate line group 200 can be turned on to have the same scan signal, and the pixels corresponding to the three turned on gate lines 100 can be turned on at the same time to input the same data signal, so that three rows corresponding to the three turned on gate lines 100 and three pixels in the same column are equivalent to a pattern for displaying one pixel, and the second resolution can be smaller than the first resolution. Of course, when each gate line group 200 includes four gate lines 100, at the second resolution, the second display control unit 300 in the same gate line group 200 is configured to turn on two connected gate lines 100, so that the second gate line 100 and the third gate line 100 in each gate line group 200 can be turned on to have the same scan signal, and the pixels corresponding to the two turned-on gate lines 100 can be turned on at the same time to input the same data signal, so that the two turned-on gate lines 100 correspond to two rows and two pixels in the same column are equivalent to displaying a pattern of one pixel, and the second resolution can be smaller than the first resolution. Alternatively, as shown in fig. 1d, when each gate line group 200 includes five gate lines 100, at the second resolution, one, two, or three display control units 300 in the same gate line group 200 are used to turn on two connected gate lines 100, so that the pixels corresponding to the turned-on gate lines 100 in each gate line group 200 can be turned on at the same time to input the same data signal, so that several pixels in several rows and in the same column corresponding to the turned-on gate lines 100 are equivalent to a pattern for displaying one pixel, and the second resolution can be lower than the first resolution. Similarly, the description is omitted here, so that the conversion function of displaying with multiple resolutions can be realized.
Alternatively, in practical implementation, in the array substrate provided in the embodiment of the present invention, at the second resolution, the same substrate is usedAll the display control units in the grid line group are used for conducting the connected two grid lines. Specifically, as shown in fig. 1a and fig. 1e, when each gate line group 200 includes two gate lines 100, at the second resolution, the display control unit 300 in the same gate line group 200 is configured to turn on the two connected gate lines 100, that is, the pixels corresponding to the two gate lines 100 in each gate line group 200 are simultaneously turned on to input the same data signal, so that two rows and two pixels in the same column corresponding to the two turned on gate lines 100 correspond to a pattern for displaying one pixel, and the second resolution can be the first resolutionAlternatively, as shown in fig. 1b, when each gate line group 200 includes three gate lines 100, at the second resolution, the display control unit 300 in the same gate line group 200 is used to turn on two connected gate lines 100, so that the pixels corresponding to the three gate lines 100 in each gate line group 200 can be turned on at the same time to input the same data signal, so that three rows and three pixels in the same column corresponding to the three turned on gate lines 100 correspond to a pattern for displaying one pixel, and the second resolution can be the first resolutionAlternatively, as shown in fig. 1c, when each gate line group 200 includes four gate lines 100, at the second resolution, the display control unit 300 in the same gate line group 200 is used to turn on two connected gate lines 100, so that the pixels corresponding to the four gate lines 100 in each gate line group 200 can be turned on at the same time to input the same data signal, so that the four rows and four pixels in the same column corresponding to the four turned on gate lines 100 correspond to a pattern for displaying one pixel, and the second resolution can be the first resolutionAlternatively, as shown in fig. 1d, when each gate line group 200 includes five gate lines 100, at the second resolution, the display control units 300 in the same gate line group 200 are used to turn on two connected gate lines 100, so five gate lines in each gate line group 200The pixels corresponding to the gate lines 100 may be simultaneously turned on to input the same data signal, so that five pixels in five rows and the same column corresponding to the five turned-on gate lines 100 correspond to a pattern for displaying one pixel, and the second resolution may be the first resolutionSimilarly, the description is omitted here, so that the conversion function of two resolution displays can be realized.
In a specific implementation, the array substrate provided in the embodiment of the present invention may further include a substrate on which the gate lines and the display control units are disposed.
In specific implementation, as shown in fig. 1a to 1e, the array substrate provided in the embodiment of the present invention further includes: a drive control unit 400;
the driving control unit 400 is configured to control each display control unit to disconnect two gate lines at a first resolution, and control at least some display control units in the same gate line group to connect two gate lines at a second resolution. The driving control unit may output a driving control signal to the display control unit to control each display control unit to turn off the two connected gate lines at a first resolution, and to control at least some display control units in the same gate line group to turn on the two connected gate lines at a second resolution.
In specific implementation, in the array substrate provided in the embodiment of the present invention, as shown in fig. 1b and fig. 1e, each display control unit 300 may be connected to the driving control unit 400 through a one-to-one corresponding first control signal line 510.
Alternatively, as shown in fig. 1a, all the display control units 300 may be connected to the driving control unit 400 through the same second control signal line 520.
Alternatively, as shown in fig. 1c and 1d, some display control units 300 in the same gate line group 200 may be connected to the driving control unit 400 through the same third control signal line 530, and the rest of the display control units 300 may be connected to the driving control unit 400 through the one-to-one fourth control signal lines 540.
Or, some display control units in the same gate line group may be connected to the driving control unit through the same third control signal line, and the remaining display control units may be connected to the driving control unit through the same fifth control signal line.
In specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 1a to fig. 1d, one display control unit 300 is connected between every two adjacent gate lines 100 in each gate line group 200, and is located at the same end of the connected gate lines 100.
Alternatively, for further stable control, as shown in fig. 1e, two display control units 300 are connected between every two adjacent gate lines 100 in each gate line group 200 and are respectively located at two ends of the connected gate lines 100. Thus, when one display control unit 300 between every two adjacent gate lines 100 is damaged and does not work, the function of conducting the two gate lines can be realized due to the function of the other display control unit 300.
The array substrate provided by the embodiment of the invention is described below by taking an example that each gate line group includes two gate lines and a display control unit connected between two adjacent gate lines.
In a specific implementation, as shown in fig. 2a to 2c, in the array substrate provided in the embodiment of the present invention, the display control unit 300 may specifically include: a switching transistor M0; wherein,
the gate of the switching transistor M0 is used for receiving the driving control signal output by the driving control unit 400, and the source and the drain of the switching transistor M0 are respectively connected to two corresponding adjacent gate lines 100. Two adjacent gate lines 100 corresponding to the switching transistor M0 are respectively two gate lines 100 connected to the display control unit 300 where the switching transistor M0 is located.
In practical implementation, in the array substrate provided by the embodiment of the invention, as shown in fig. 2a to 2c, the switch transistor M0 may be an N-type transistor, and the driving control signal is a voltage signal with a low potential at the first resolution and a voltage signal with a high potential at the second resolution. Alternatively, the switching transistor may be a P-type transistor, and the driving control signal may be a voltage signal having a high potential at the time of the first resolution and a voltage signal having a low potential at the time of the second resolution. In practical applications, the specific structure of the switching transistor needs to be determined according to practical application conditions, and is not limited herein.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, when the switching transistor is in a conducting state under the control of the driving control signal, the two gate lines connected to the source and the drain of the switching transistor may be conducted.
In a specific implementation, as shown in fig. 2a, in the array substrate provided in the embodiment of the present invention, the array substrate may further include: a gate driving circuit 600 at one end of each gate line 100;
the gate driving circuit 600 includes cascaded shift register units sr (M), and the shift register units sr (M) at each stage are the mth stage shift register units, respectively; wherein M is an integer greater than or equal to 1, and Output ends Output of the shift register units sr (M) at each stage are connected to one gate line 100 in a one-to-one correspondence.
Alternatively, as shown in fig. 2b, the array substrate may further include: a gate driving circuit 600 positioned at both ends of each gate line;
the gate driving circuit 600 includes cascaded shift register units sr (M), and the shift register units sr (M) at each stage are the mth stage shift register units, respectively; wherein M is an integer greater than or equal to 1, and Output ends Output of the shift register units sr (M) at each stage are connected to one gate line 100 in a one-to-one correspondence.
Alternatively, as shown in fig. 2c, the array substrate may further include: a gate driving circuit 600 respectively located at both ends of each gate line 100; wherein,
the gate driving circuit 600 at one end of each gate line 100 includes: the cascaded multi-stage shift register units SR (2N-1), and the shift register units SR (2N-1) at each stage are the 2N-1 stage shift register units respectively; the gate driving circuit 600 at the other end of each gate line 100 includes: cascaded multi-stage shift register units SR (2N), wherein each stage of shift register unit SR (2N) is a 2N-stage shift register unit; wherein N is an integer greater than or equal to 1, Output ends Output of the shift register units SR (2N-1) of each stage are connected to one gate line in a one-to-one correspondence, and Output ends Output of the shift register units SR (2N) of each stage are connected to one gate line in a one-to-one correspondence.
In a specific implementation, the array substrate provided in the embodiment of the present invention further includes: a display driving chip;
when the display driver chip is at the first resolution, the display driver chip is used for controlling all the shift register units to sequentially output scanning signals;
when the resolution is the second resolution, the display driving chip is used for controlling the kN- (k-n) th-stage shift register unit to sequentially output scanning signals; wherein k is the total number of the grid lines in each grid line group, and n is an integer less than or equal to k. For example, when each gate line group includes two gate lines, the display driving chip controls each shift register unit in the odd-numbered rows to sequentially output the scan signal, or controls each shift register unit in the even-numbered rows to sequentially output the scan signal. When each grid line group comprises three grid lines, the display driving chip controls each level of shift register units of 3N lines to sequentially output scanning signals, or controls each level of shift register units of 3N-1 lines to sequentially output scanning signals, or controls each level of shift register units of 3N-2 lines to sequentially output scanning signals.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, the driving control unit may also be a driving control chip. And the driving control chip and the display driving chip can be a chip or can be independent chips respectively. The specific structures of the driving control chip and the display driving chip are the same as those of the prior art, and should be understood by those skilled in the art, and are not described in detail herein, nor should they be construed as limiting the present invention.
In a specific implementation, as shown in fig. 3, in the array substrate provided in the embodiment of the present invention, the shift register unit may specifically include: a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, an eighth switching transistor M8, a first capacitor C1, and a second capacitor C2; wherein,
a gate of the first switching transistor M1 is connected to the Input signal terminal Input, a source thereof is connected to the first dc signal terminal CN, and a drain thereof is connected to the first node a;
the gate of the second switching transistor M2 is connected to the Reset signal terminal Reset, the source is connected to the second dc signal terminal CNB, and the drain is connected to the first node a;
the gate of the third switching transistor M3 is connected to the first node a, the source is connected to the first clock signal terminal CK, and the drain is connected to the Output terminal Output of the shift register unit;
the gate of the fourth switching transistor M4 is connected to the second node B, the source is connected to the reference signal terminal VGL, and the drain is connected to the Output terminal Output;
a gate of the fifth switching transistor M5 is connected to the second node B, a source thereof is connected to the reference signal terminal VGL, and a drain thereof is connected to the first node a;
a gate of the sixth switching transistor M6 is connected to the first node a, a source thereof is connected to the reference signal terminal VGL, and a drain thereof is connected to the second node B;
a gate of the seventh switching transistor M7 is connected to the Output terminal Output, a source is connected to the reference signal terminal VGL, and a drain is connected to the second node B;
the gate and the source of the eighth switching transistor M8 are both connected to the second clock signal terminal, and the drain is connected to the second node B;
the first capacitor C1 is connected between the first node a and the Output terminal Output;
the second capacitor C2 is connected between the second node B and the reference signal terminal VGL.
In a specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 3, all the switch transistors may be N-type transistors, the active pulse signal of the Input signal terminal is at a high potential, the potential of the first dc signal terminal CN is at a high potential, and the potentials of the second dc signal terminal CNB and the reference signal terminal VGL are both at a low potential. Alternatively, all the switch transistors may be P-type transistors, the effective pulse signal at the input signal end is at a low potential, the potential at the first dc signal end is at a low potential, and the potential at the second dc signal end and the potential at the reference signal end are both at a high potential and a low potential, which is not limited herein.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, the N-type transistor is turned on by a high-level voltage signal and turned off by a low-level voltage signal. The P-type transistor is turned on by a low-level voltage signal and turned off by a high-level voltage signal.
The above is merely an example of specific structures of the display control unit and the shift register unit provided in the embodiment of the present invention, and in a specific implementation, the specific structures of the display control unit and the shift register unit are not limited to the above structures provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and are not limited herein.
The structure of the shift register unit shown in fig. 3 is taken as an example, and the operation state of the shift register unit provided by the implementation of the present invention is described with reference to the input/output timing diagrams of the first resolution and the second resolution. The potential of the first dc signal terminal CN is high potential, the potential of the second dc signal terminal CNB is low potential, and the potential of the reference signal terminal VGL is low potential.
In the first resolution, the Input/Output timing diagrams corresponding to the shift register units are shown in fig. 4a, when each stage of the shift register units in the odd-numbered rows is in operation, the signals of the Input signal terminal Input, the first clock signal terminal CK, the second clock signal terminal CKB and the Output terminal Output are Input1, CK1, CKB1 and Output1, respectively; when the shift register units in each stage in even rows are in operation, the signals of the Input signal terminal Input, the first clock signal terminal CK, the second clock signal terminal CKB and the Output terminal Output are Input2, CK2, CKB2 and Output2, respectively. And the specific working process of the shift register unit is the same as that of the prior art, which is understood by those skilled in the art and will not be described in detail herein.
At the second resolution, when the shift register units in each odd-numbered row work, the potentials of all the signal ends of the shift register units in each even-numbered row are low potentials. As shown in fig. 4b, when each shift register unit in the odd-numbered row operates, signals of the Input signal terminal Input, the first clock signal terminal CK, the second clock signal terminal CKB, and the Output terminal Output are Input, CK, CKB, and Output, respectively. And the specific working process of the shift register unit is the same as that of the prior art, which is understood by those skilled in the art and will not be described in detail herein.
Based on the same inventive concept, the embodiment of the invention further provides a display panel, which comprises any one of the array substrates provided by the embodiment of the invention. The principle of the display panel to solve the problem is similar to the aforementioned array substrate, so the implementation of the display panel can be referred to the implementation of the aforementioned array substrate, and repeated details are not repeated herein.
In specific implementation, the display panel provided in the embodiment of the present invention may adopt a Smart View technology to perform timing output control on the gate driving circuit, and then the display control unit controls the connection and disconnection of the two connected gate lines, so as to save the calculation amount of the display driving chip for processing and calculating the big data, thereby avoiding the display driving chip from performing a large amount of data processing and reducing power consumption.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention. The implementation of the display device can refer to the above embodiments of the array substrate, and repeated descriptions are omitted.
According to the array substrate, the display panel and the display device provided by the embodiment of the invention, the display control unit is arranged between every two adjacent grid lines in each grid line group, and at the first resolution, the two connected grid lines are disconnected by the display control unit, so that each grid line can be mutually independent, each grid line can have respective scanning signals, and the pixels corresponding to each grid line input required data signals, so that each pixel can display respective gray scale patterns. At the second resolution, the two gate lines connected with each other are conducted by at least part of the display control units, so that the mutually conducted gate lines have the same scanning signals, pixels corresponding to the gate lines with the same scanning signals are simultaneously turned on to input the same data signals, and the pixels corresponding to the gate lines with the same scanning signals display the same gray scale pattern. Therefore, high-resolution display with high resolution can be realized by adopting the first resolution for display, and low-resolution display can be realized by adopting the second resolution for display, so that the conversion function of high-resolution display and low-resolution display can be realized. Compared with the prior art for realizing low-resolution display, the array substrate provided by the embodiment of the invention has the advantages that after the display driving chip and the grid driving circuit are assembled, as the conducted grid lines have the same scanning signals, the display driving chip can accurately control the scanning signals to be output to the specific part of the grid lines without carrying out a large amount of data processing, and the function of low-resolution display can be realized. And the structural design of the array substrate is slightly changed, so that the process can be reduced, and the manufacturing cost can be saved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An array substrate, comprising: a plurality of gate lines; the method is characterized in that all the grid lines are divided into a plurality of grid line groups, and each grid line group comprises at least two adjacent grid lines; the array substrate further includes: the display control unit is connected between every two adjacent grid lines in each grid line group;
when the first resolution is reached, each display control unit is used for disconnecting the two connected grid lines;
at the second resolution, at least part of the display control units in the same grid line group are used for conducting the two connected grid lines; wherein the first resolution is greater than the second resolution.
2. The array substrate of claim 1, further comprising: a drive control unit;
the driving control unit is used for controlling the two grid lines which are disconnected by each display control unit at the first resolution, and controlling at least part of the two grid lines which are connected by the display control units in the same grid line group at the second resolution.
3. The array substrate of claim 2, wherein each of the display control units is connected to the driving control unit through a one-to-one corresponding first control signal line; or,
all the display control units are connected with the drive control unit through the same second control signal line; or,
and the part of the display control units in the same grid line group are connected with the drive control unit through the same third control signal line, and the rest of the display control units are connected with the drive control unit through the fourth control signal lines or the same fifth control signal lines which are in one-to-one correspondence.
4. The array substrate of claim 1, wherein one display control unit is connected between every two adjacent gate lines in each gate line group and is located at the same end of the connected gate line; or,
and two display control units are connected between every two adjacent grid lines in each grid line group and are respectively positioned at two ends of the connected grid lines.
5. The array substrate of any one of claims 1-4, wherein the display control unit comprises: a switching transistor; wherein,
the grid electrode of the switch transistor is used for receiving a driving control signal output by the driving control unit, and the source electrode and the drain electrode of the switch transistor are respectively connected with two corresponding adjacent grid lines.
6. The array substrate of any one of claims 1-4, wherein at the second resolution, all of the display control units in the same gate line group are configured to conduct two connected gate lines.
7. The array substrate of claim 6, wherein the array substrate further comprises: a gate driving circuit at least at one end of each gate line;
the grid driving circuit comprises cascaded multi-stage shift register units, and the shift register units at each stage are Mth-stage shift register units respectively; m is an integer greater than or equal to 1, and the output ends of the shift register units of each stage are correspondingly connected with one grid line one by one; or,
the array substrate further includes: the grid driving circuits are respectively positioned at two ends of each grid line; wherein,
the gate driving circuit at one end of each of the gate lines includes: the shift register units at each stage are 2N-1 stage shift register units respectively; the gate driving circuit at the other end of each gate line includes: the shift register unit comprises cascaded multiple stages of shift register units, wherein each stage of shift register unit is a 2N-stage shift register unit; and N is an integer greater than or equal to 1, and the output ends of the shift register units of each stage are connected with one grid line in a one-to-one correspondence mode.
8. The array substrate of claim 7, further comprising: a display driving chip;
when the first resolution ratio is reached, the display driving chip is used for controlling all the shift register units to sequentially output scanning signals;
when the second resolution is higher than the first resolution, the display driving chip is used for controlling the kN- (k-n) th-stage shift register unit to sequentially output scanning signals; wherein k is the total number of the gate lines in each gate line group, and n is an integer less than or equal to k.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
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