CN105575318A - Display panel and display apparatus - Google Patents

Abstract

The invention discloses a display panel and a display device. The display panel comprises: a plurality of cascaded shift register units for inputting gate scanning signals to corresponding gate lines; every two adjacent columns of pixels form a group, and each group A data line is arranged between two columns of pixels in the pixel; each shift register unit includes multiple modules, and each module is located at a gap between two adjacent groups of pixels. Wherein, two columns of pixels share one data line, therefore, the number of data lines can be halved, and the vacated space can be used to set shift register units for driving the display panel to realize gate drive scanning, that is, to set the gate drive circuit on The display area of the display panel makes the shape and frame of the display panel provided by the embodiment of the present invention no longer limited by peripheral circuits, not only can realize narrow frame, but also can realize special-shaped display, so that the application range of the display panel is from mobile phones, Pad, etc. are extended to special-shaped displays such as automotive circular instrument panels.

Description

Display panel and display device

technical field

The present invention relates to the field of display technology, in particular to a display panel and a display device.

Background technique

Currently, display technologies are widely used in displaying televisions, mobile phones, and public information, and display panels for displaying images are also various, and can display rich and colorful images. Generally, the source driver chip in the display panel is responsible for receiving image data, buffering the image data and converting the digital signal to an analog signal, and finally sending the converted signal to each data line of the display panel through the output buffer. The gate drive circuit is responsible for realizing progressive scanning, and generates gate line scanning signals that are opened line by line for timing control. After loading the gate line scanning signals of each row to the corresponding gate lines, the pixel switches are controlled to open, so that the image data enters this row of pixels. The storage capacitor, and finally realize the normal display of the image.

At present, the gate driving circuit constructed by thin film transistors is generally placed in the peripheral areas on the left and right sides of the display panel. Since the gate driving circuit occupies a certain frame area, the display panel cannot realize a narrow frame design. Especially for medium and large size display panels, the size of each component of the gate drive circuit is large, and the gate drive circuit is placed in the peripheral area of the display panel, occupying a large frame area, which makes it impossible for medium and large size display panels to achieve narrow frame.

Therefore, how to realize the narrow frame design of the display panel is a technical problem to be solved urgently by those skilled in the art.

Contents of the invention

Embodiments of the present invention provide a display panel and a display device, which are used to realize the narrow frame design of the display panel.

An embodiment of the present invention provides a display panel, including: a plurality of cascaded shift register units for inputting gate scanning signals to corresponding gate lines;

Every two adjacent columns of pixels is a group, and a data line is arranged between the two columns of pixels in each group of pixels;

Each of the shift register units includes a plurality of modules, and each of the modules is located at a gap between two adjacent groups of pixels.

In a possible implementation manner, in the above-mentioned display panel provided by the embodiment of the present invention, the multiple modules included in each shift register unit are located in gaps between multiple adjacent adjacent pixel groups.

In a possible implementation manner, in the above display panel provided by the embodiment of the present invention, the shift register unit includes: an input module, a reset module and an output module; wherein,

The input terminal and the control terminal of the input module are respectively connected to the signal input terminal, and the output terminal is connected to the pull-up node; the input module is used to pull the signal input through the signal input terminal under the control of the signal input terminal. increasing the potential of the pull-up node;

The input terminal of the reset module is connected to the reference signal terminal, the control terminal is connected to the reset signal terminal, and the output terminal is connected to the pull-up node; the reset module is used to pass the reference signal terminal under the control of the reset signal terminal. The signal at the signal terminal pulls down the potential of the pull-up node;

The first input terminal of the output module is connected to the clock signal terminal, the second input terminal is connected to the reference signal terminal, the first control terminal is connected to the pull-up node, and the second control terminal is connected to the reset signal terminal , the output terminal is connected to the scanning signal output terminal; the output module is used to output the signal of the clock signal terminal to the scanning signal output terminal under the control of the pull-up node, and pass the The signal at the reference signal terminal pulls down the potential at the scanning signal output terminal.

In a possible implementation manner, in the above display panel provided by the embodiment of the present invention, the output module includes: a first output module and a second output module; wherein,

The input terminal of the first output module is connected to the clock signal terminal, the control terminal is connected to the pull-up node, and the output terminal is connected to the scan signal output terminal; Under the control of the pull node, output the signal of the clock signal terminal to the scanning signal output terminal;

The input terminal of the second output module is connected to the reference signal terminal, the control terminal is connected to the reset signal terminal, and the output terminal is connected to the scanning signal output terminal; Under the control of the signal terminal, the signal of the reference signal terminal pulls down the potential of the scanning signal output terminal.

In a possible implementation manner, in the above display panel provided by the embodiment of the present invention, the first output module includes: a first switching transistor and a capacitor; wherein,

The gate of the first switch transistor is connected to the pull-up node, the source is connected to the clock signal terminal, and the drain is connected to the scanning signal output terminal;

The capacitor is connected between the pull-up node and the scan signal output end.

In a possible implementation manner, in the above-mentioned display panel provided by the embodiment of the present invention, the second output module includes: a second switch transistor;

The gate of the second switching transistor is connected to the reset signal terminal, the source is connected to the reference signal terminal, and the drain is connected to the scanning signal output terminal.

In a possible implementation manner, in the above-mentioned display panel provided by the embodiment of the present invention, the input module includes: a third switch transistor;

The gate and source of the third switch transistor are respectively connected to the signal input terminal, and the drain is connected to the pull-up node.

In a possible implementation manner, in the above display panel provided by the embodiment of the present invention, the reset module includes: a fourth switch transistor;

The gate of the fourth switching transistor is connected to the reset signal terminal, the source is connected to the reference signal terminal, and the drain is connected to the pull-up node.

In a possible implementation manner, in the above-mentioned display panel provided by the embodiment of the present invention, each of the shift register units is located in an area defined by two rows and six columns of pixels; wherein, the third switch transistor and the fourth switch transistor are located on the side of the pixels in the first column that are not provided with data lines, the first switch transistor and the capacitor are located on the side of the pixels in the third column that are not provided with data lines, and the second switch transistors are located on the side of the pixels in the third column that are not provided with data lines. The fifth column of pixels is not provided on the side of the data line.

In a possible implementation manner, in the above-mentioned display panel provided by the embodiment of the present invention, two gate lines are arranged between two adjacent rows of pixels; The output end of the shift register unit and the input end of the shift register unit of the next stage are connected to the same gate line.

An embodiment of the present invention provides a display device, including the above-mentioned display panel provided by the embodiment of the present invention.

The beneficial effects of the embodiments of the present invention include:

Embodiments of the present invention provide a display panel and a display device, the display panel comprising: a plurality of cascaded shift register units for inputting gate scan signals to corresponding gate lines; every two adjacent columns of pixels form a group, A data line is arranged between two columns of pixels in each group of pixels; each shift register unit includes a plurality of modules, and each module is located at a gap between two adjacent groups of pixels. In the above-mentioned display panel provided by the embodiment of the present invention, two columns of pixels share one data line, therefore, the number of data lines can be halved, and the vacated space can be used to set shift registers for driving the display panel to realize gate-driven scanning In this way, the gate driving circuit is arranged in the display area of the display panel. Compared with the prior art where the gate driving circuit is arranged in the peripheral area of the display panel, the shape and frame of the display panel provided by the embodiment of the present invention can be different. Restricted by peripheral circuits, not only narrow borders can be realized, but also special-shaped displays can be realized, so that the application range of display panels is extended from mobile phones, Pads, etc. to special-shaped displays such as automobile circular instrument panels, which improves the actual application range of display panels.

Description of drawings

FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention;

FIG. 3 is an input and output timing diagram of a shift register unit provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present invention.

detailed description

The specific implementation manners of the display panel and the display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

An embodiment of the present invention provides a display panel, including: a plurality of cascaded shift register units for inputting gate scan signals to corresponding gate lines; every two adjacent columns of pixels form a group, and two pixels in each group A data line is arranged between the pixels of a column; each shift register unit includes a plurality of modules, and each module is located at a gap between two adjacent groups of pixels.

In the above-mentioned display panel provided by the embodiment of the present invention, two columns of pixels share one data line, therefore, the number of data lines can be halved, and the vacated space can be used to set shift registers for driving the display panel to realize gate-driven scanning In this way, the gate driving circuit is arranged in the display area of the display panel. Compared with the prior art where the gate driving circuit is arranged in the peripheral area of the display panel, the shape and frame of the display panel provided by the embodiment of the present invention can be different. Restricted by peripheral circuits, not only narrow borders can be realized, but also special-shaped displays can be realized, so that the application range of display panels is extended from mobile phones, Pads, etc. to special-shaped displays such as automobile circular instrument panels, which improves the actual application range of display panels.

In specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, multiple modules included in each shift register unit can be arranged at the gaps between multiple adjacent adjacent pixel groups, so that each The shift register unit is set in the smallest area, realizing the compact setting between cascaded multiple shift register units. Specifically, the above-mentioned display panel provided by the embodiment of the present invention can adopt a double gate line structure, that is, two gate lines are arranged between two adjacent rows of pixels in the display area, so that two adjacent columns of pixels in the display area can be divided into One group, a data line is set between two columns of pixels in each group of pixels, that is, the number of data lines can be reduced by half, and the space vacated due to the reduction of the number of data lines can just be used to set the shift register. Each module and the required signal routing.

In specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, among the multiple cascaded shift register units; except the first-stage shift register unit and the last-stage shift register unit, each of the other shift The signal output terminals of the bit register unit all input the trigger signal to the signal input terminal of the next-stage shift register unit adjacent to it, and input the reset signal to the reset signal terminal of the upper-stage shift register unit adjacent to it; The signal output terminal of the first-stage shift register unit inputs a trigger signal to the signal input terminal of the second-stage shift register unit; the signal lines of each shift register unit can be parallel to the gate lines and/or data lines.

During specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, as shown in FIG. 1 , the shift register unit may include: an input module 01, a reset module 02 and an output module 03; The control terminals are respectively connected to the signal input terminal Input, and the output terminal is connected to the pull-up node P; the input module 01 is used to pull up the potential of the pull-up node P through the signal input by the signal input terminal Input under the control of the signal input terminal Input; The input terminal of the reset module 02 is connected to the reference signal terminal Vref, the control terminal is connected to the reset signal terminal Reset, and the output terminal is connected to the pull-up node P; the reset module 02 is used to pass the reference signal terminal Vref under the control of the reset signal terminal Reset. The signal pulls down the potential of the pull-up node P; the first input terminal of the output module 03 is connected to the clock signal terminal CLK, the second input terminal is connected to the reference signal terminal Vref, the first control terminal is connected to the pull-up node P, and the second The control terminal is connected to the reset signal terminal Reset, and the output terminal is connected to the scan signal output terminal Out; the output module 03 is used to output the signal of the clock signal terminal CLK to the scan signal output terminal Out under the control of the pull-up node P. Under the control of the terminal Reset, the potential of the scanning signal output terminal Out is pulled down by the signal of the reference signal terminal Vref.

Specifically, in the above-mentioned display panel provided by the embodiment of the present invention, the gate drive circuit provided in the display area includes a plurality of cascaded shift register units, each shift register unit corresponds to a gate line, and the shift register unit can It includes an input module, a reset module and an output module, so that the potential of the pull-up node is pulled up through the input module, and then the output module outputs the signal of the clock signal terminal to the scan signal output terminal under the control of the pull-up node to realize the output of the scan signal; After the scanning of the row of gate lines is completed, the potential of the pull-up node can be pulled down by the reset module to close the row of gate lines, and the output module can pull down the potential of the scan signal output terminal under the control of the reset signal terminal to eliminate noise.

In specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, as shown in FIG. 2 , the output module may include: a first output module 031 and a second output module 032; The clock signal terminal CLK is connected, the control terminal is connected to the pull-up node P, and the output terminal is connected to the scan signal output terminal Out; the first output module 031 is used to output the signal of the clock signal terminal CLK to The scanning signal output terminal Out; the input terminal of the second output module 032 is connected with the reference signal terminal Vref, the control terminal is connected with the reset signal terminal Reset, and the output terminal is connected with the scanning signal output terminal Out; the second output module 032 is used for reset signal Under the control of the terminal Reset, the potential of the scanning signal output terminal Out is pulled down by the signal of the reference signal terminal Vref.

Specifically, in the above display panel provided by the embodiment of the present invention, the output module may include a first output module and a second output module, the first output module may output scan signals under the control of the pull-up node, and the second output module may The control of the reset signal terminal pulls down the potential of the scan signal output terminal to eliminate noise.

In specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, as shown in FIG. 2 , the first output module 031 may include: a first switching transistor T1 and a capacitor C; The pull-up node P is connected, the source is connected to the clock signal terminal CLK, and the drain is connected to the scan signal output terminal Out; the capacitor C is connected between the pull-up node P and the scan signal output terminal Out. Specifically, the first switch transistor can be turned on under the control of the pull-up node, and the turned-on first switch transistor can turn on the clock signal terminal and the scan signal output terminal, and then can output the scan signal.

During specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, as shown in FIG. 2 , the second output module 032 may include: a second switching transistor T2; the gate of the second switching transistor T2 is connected to the reset signal terminal Reset , the source is connected to the reference signal terminal Vref, and the drain is connected to the scanning signal output terminal Out. Specifically, the second switching transistor can be turned on under the control of the reset signal terminal, and the turned-on second switching transistor connects the reference signal terminal and the scanning signal output terminal, thereby pulling down the potential of the scanning signal output terminal to eliminate noise.

During specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, as shown in FIG. 2 , the input module 01 may include: a third switching transistor T3; the gate and source of the third switching transistor T3 are respectively connected to the signal input terminal The Input is connected, and the drain is connected to the pull-up node P. Specifically, the third switch transistor may be turned on under the control of the input signal terminal, and the turned-on third switch transistor conducts the signal input terminal and the pull-up node, thereby pulling up the potential of the pull-up node.

During specific implementation, in the above-mentioned display panel provided by the embodiment of the present invention, as shown in FIG. 2 , the reset module 02 may include: a fourth switching transistor T4; the gate of the fourth switching transistor T4 is connected to the reset signal terminal Reset, and the source The pole is connected to the reference signal terminal Vref, and the drain is connected to the pull-up node P. Specifically, the fourth switch transistor may be turned on under the control of the reset signal terminal, and the turned-on fourth switch transistor conducts the reference signal terminal and the pull-up node, thereby pulling down the potential of the pull-up node.

It should be noted that the switching transistor mentioned in the above embodiments of the present invention may be a thin film transistor (TFT, ThinFilmTransistor) or a metal oxide semiconductor field effect transistor (MOS, MetalOxideSemiconductor), which is not limited here. In specific implementation, the sources and drains of these transistors can be interchanged, and no specific distinction is made. When describing specific embodiments, a thin film transistor is taken as an example for illustration.

The working process of the shift register unit provided by the embodiment of the present invention will be described in detail below in conjunction with the structure and timing of the shift register unit provided by the embodiment of the present invention. The shift register unit and the input and output timing diagram of FIG. 2 shown in FIG. 3 describe the working process of the shift register unit provided by the embodiment of the present invention. Among them, three stages t1 to t3 in the input and output timing diagram shown in FIG. 3 are selected. In the following description, 1 represents a high-level signal, and 0 represents a low-level signal.

In the t1 stage, Input=1, CLK=0, Reset=0, Vref=0. Since Input=1, the third switch transistor T3 is in a conduction state, and the conduction third switch transistor T3 outputs the signal of the signal input terminal Input to the pull-up node P, thereby pulling up the potential of the pull-up node P; at the same time , the potential of the pull-up node P rises, and the capacitor C can be charged. The t1 stage is the charging stage.

In the t2 stage, Input=0, CLK=1, Reset=0, Vref=0. Since Input=0, the third switching transistor T3 is in a cut-off state. The charging of the capacitor C ends and enters the discharge stage. The discharge of the capacitor C makes the potential of the gate of the first switching transistor T1 rise, so that the first switching transistor T1 is turned on, and the turned-on first switching transistor T1 connects the clock signal terminal CLK to the scan The signal output terminal Out is turned on, so as to output the signal of the clock signal terminal CLK. The t2 stage is the scan signal output stage.

In the t3 stage, Input=0, CLK=0, Reset=1, Vref=0. Since Reset=1, the second switch transistor T2 and the fourth switch transistor T4 are in a conduction state; the conduction of the fourth switch transistor T4 conducts the reference signal terminal Vref with the pull-up node P, thereby pulling down the pull-up node P The potential of the first switching transistor T1 is turned off, and the scanning signal output is turned off; the second switching transistor T2 is turned on to conduct the reference signal terminal Vref and the scanning signal output terminal Out, and then pull down the potential of the scanning signal output terminal Out to eliminate noise. . The t3 stage is the scan signal output cut-off stage.

In specific implementation, the above-mentioned display panel provided by the embodiment of the present invention is provided with a gate drive circuit in the display area, wherein the gate drive circuit includes a plurality of cascaded shift register units, and each shift register unit is composed of Multiple switching transistors and capacitors are built through signal lines. Specifically, as shown in FIG. 4, the display panel can adopt a double gate line structure, and the number of data lines can be halved. Therefore, a plurality of switching transistors and capacitors can be arranged in the gap between two adjacent groups of pixels, and each element Signal lines connected between devices may be parallel to gate lines and data lines.

As shown in Figure 4, taking the first-stage shift register unit to the fourth-stage shift register unit as an example, in the area occupied by two rows and six columns of pixels, four switches of one shift register unit can be The transistor and 1 capacitor are placed. Specifically, taking the first-stage shift register unit as an example, the third switching transistor T3 is placed on the left side of the first red pixel in the first row, and the fourth switching transistor T4 is placed on the left side of the first red pixel in the second row , the first switching transistor T1 and capacitor C are placed on the left of the first blue pixel in the first row, and the second switching transistor T2 is on the left of the second green pixel in the first row. There are no data lines set in these positions, and the shift The signal lines required by the register unit are arranged along the direction of the data lines, and the connection lines of the components in the shift register unit can be arranged along the direction parallel to the gate lines and the data lines.

As shown in FIG. 4, the drain of the first switching transistor T1 of the first-stage shift register unit is connected to the first gate line Gate1, while the source of the third switching transistor T3 of the second-stage shift register unit is connected to the first gate line Gate1. A gate line Gate1 is connected, that is, among two adjacent shift register units, the output terminal of the upper-stage shift register unit and the input end of the next-stage shift register unit are connected to the same gate line, and the upper-stage shift register unit The output signal of the bit register unit is used as the trigger signal of the shift register unit of the next stage; in addition, the gates of the second switching transistor T2 and the fourth switching transistor T4 in each shift register unit are the same as the corresponding gates of the shift register unit of this stage. The gate lines of the next row adjacent to the line are connected, wherein, the drain of the second switching transistor T2 is connected to the gate line corresponding to the shift register unit of the current stage, and is used to pull down the gate line of the row when the gate line of the next row enters the scanning phase. signal to reduce noise; at the same time, the fourth switching transistor T4 pulls down the potential of the first node, and then turns off the shift register unit of this stage, so that it stops outputting the scan signal to the corresponding gate line.

As shown in Figure 4, the four-stage shift register units can be arranged in a pixel area of 2 rows and 24 columns, and arranged downwards in a cycle of four rows, and all the shift register units can be placed in the display area.

In actual application, the number of occupied pixels can be adjusted according to the number and size of components in the gate driving circuit, which is not limited here.

Based on the same inventive concept, an embodiment of the present invention provides a display device, including the above-mentioned display panel provided by the embodiment of the present invention. The display device can be applied to any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. Since the problem-solving principle of the display device is similar to that of the display panel, the implementation of the display device can refer to the implementation of the display panel above, and repeated descriptions will not be repeated.

Embodiments of the present invention provide a display panel and a display device, the display panel comprising: a plurality of cascaded shift register units for inputting gate scan signals to corresponding gate lines; every two adjacent columns of pixels form a group, A data line is arranged between two columns of pixels in each group of pixels; each shift register unit includes a plurality of modules, and each module is located at a gap between two adjacent groups of pixels. In the above-mentioned display panel provided by the embodiment of the present invention, two columns of pixels share one data line, therefore, the number of data lines can be halved, and the vacated space can be used to set shift registers for driving the display panel to realize gate-driven scanning In this way, the gate driving circuit is arranged in the display area of the display panel. Compared with the prior art where the gate driving circuit is arranged in the peripheral area of the display panel, the shape and frame of the display panel provided by the embodiment of the present invention can be different. Restricted by peripheral circuits, not only narrow borders can be realized, but also special-shaped displays can be realized, so that the application range of display panels is extended from mobile phones, Pads, etc. to special-shaped displays such as automobile circular instrument panels, which improves the actual application range of display panels.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (11)

1. A display panel, comprising: a plurality of cascaded shift register units for inputting grid scan signals to corresponding gate lines; characterized in that: Every two adjacent columns of pixels is a group, and a data line is arranged between the two columns of pixels in each group of pixels; Each of the shift register units includes a plurality of modules, and each of the modules is located at a gap between two adjacent groups of pixels. 2 . The display panel according to claim 1 , wherein each of the shift register units comprises a plurality of modules located in gaps between adjacent adjacent pixel groups. 3. The display panel according to claim 1 or 2, wherein the shift register unit comprises: an input module, a reset module and an output module; wherein, The input terminal and the control terminal of the input module are respectively connected to the signal input terminal, and the output terminal is connected to the pull-up node; the input module is used to pull the signal input through the signal input terminal under the control of the signal input terminal. increasing the potential of the pull-up node; The input terminal of the reset module is connected to the reference signal terminal, the control terminal is connected to the reset signal terminal, and the output terminal is connected to the pull-up node; the reset module is used to pass the reference signal terminal under the control of the reset signal terminal. The signal at the signal terminal pulls down the potential of the pull-up node; The first input terminal of the output module is connected to the clock signal terminal, the second input terminal is connected to the reference signal terminal, the first control terminal is connected to the pull-up node, and the second control terminal is connected to the reset signal terminal , the output terminal is connected to the scanning signal output terminal; the output module is used to output the signal of the clock signal terminal to the scanning signal output terminal under the control of the pull-up node, and pass the The signal at the reference signal terminal pulls down the potential at the scanning signal output terminal. 4. The display panel according to claim 3, wherein the output module comprises: a first output module and a second output module; wherein, The input end of the first output module is connected to the clock signal end, the control end is connected to the pull-up node, and the output end is connected to the scan signal output end; Under the control of the pull node, output the signal of the clock signal terminal to the scanning signal output terminal; The input terminal of the second output module is connected to the reference signal terminal, the control terminal is connected to the reset signal terminal, and the output terminal is connected to the scanning signal output terminal; Under the control of the signal terminal, the signal of the reference signal terminal pulls down the potential of the scanning signal output terminal. 5. The display panel according to claim 4, wherein the first output module comprises: a first switching transistor and a capacitor; wherein, The gate of the first switch transistor is connected to the pull-up node, the source is connected to the clock signal terminal, and the drain is connected to the scanning signal output terminal; The capacitor is connected between the pull-up node and the scan signal output terminal. 6. The display panel according to claim 5, wherein the second output module comprises: a second switching transistor; The gate of the second switching transistor is connected to the reset signal terminal, the source is connected to the reference signal terminal, and the drain is connected to the scanning signal output terminal. 7. The display panel according to claim 6, wherein the input module comprises: a third switching transistor; The gate and source of the third switch transistor are respectively connected to the signal input terminal, and the drain is connected to the pull-up node. 8. The display panel according to claim 7, wherein the reset module comprises: a fourth switching transistor; The gate of the fourth switching transistor is connected to the reset signal terminal, the source is connected to the reference signal terminal, and the drain is connected to the pull-up node. 9. The display panel according to claim 8, wherein each of the shift register units is located in an area defined by two rows and six columns of pixels; wherein, the third switching transistor and the first The four switching transistors are located on the side of the pixels in the first column that are not provided with data lines, the first switching transistor and the capacitor are located on the side of the pixels in the third column that are not provided with data lines, and the second switching transistors are located on the side of the pixels in the fifth column The side of the data line that is not set. 10. The display panel according to claim 1, wherein two gate lines are arranged between two adjacent rows of pixels; among two adjacent shift register units, the upper stage shift register The output terminal of the unit and the input terminal of the shift register unit of the next stage are connected to the same gate line. 11. A display device, comprising the display panel according to any one of claims 1-10.