CN106531053A - Shift register, gate driving circuit and display panel - Google Patents
Shift register, gate driving circuit and display panel Download PDFInfo
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- CN106531053A CN106531053A CN201710011077.2A CN201710011077A CN106531053A CN 106531053 A CN106531053 A CN 106531053A CN 201710011077 A CN201710011077 A CN 201710011077A CN 106531053 A CN106531053 A CN 106531053A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
The invention discloses a shift register, a gate driving circuit and a display panel. The shift register comprises a pull-up module, a pull-down module, a reset module, a first control module, a second control module and an output module. By adopting the pull-up module, the pull-down module, the reset module, the first control module, the second control module and the output module, normal output of scanning signals can be realized. The output module of the shift register comprises two output ends which are connected with two adjacent gate lines, thus, one shift register disclosed by the invention can correspond to two gate lines, and the effect of inputting the scanning signals to the two adjacent gate lines by means of one shift register can be further realized. Compared with the situation that one shift register corresponds to one gate line in the prior art, the number of the shift registers can be reduced by half in the invention, thereby reducing the area occupied by the gate driving circuit on the display panel, saving the manufacturing cost and facilitating the implementation of the narrow-bezel design of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a grid driving circuit and a display panel.
Background
At present, display technologies are widely applied to televisions, mobile phones, and public information displays, and display panels for displaying pictures are also various and can display rich and colorful pictures. Generally, a source driver chip in a display panel is responsible for receiving image data, buffering the image data, converting a digital signal into an analog signal, and finally transmitting the converted signal to each data line of the display panel through an output buffer, a gate driver unit is responsible for realizing line-by-line scanning, generating a gate line scanning signal which is opened line by line aiming at timing control, loading the gate line scanning signal of each line to a corresponding gate line and then controlling a pixel switch to be opened, so that the image data enters a storage capacitor of the pixel of the line, and finally realizing normal display of the image.
The existing gate driving unit is generally realized by a gate circuit integration technology, i.e. the gate driving circuit is integrated on the display panel to replace a gate driving chip of the traditional display panel, so that the product development cost is reduced, and the process of a module end is simplified. However, with the development of the display industry, the requirements for the appearance and the technology of the display panel are higher and higher, and the display products with narrow frames gradually meet the demands of the market and the public. However, in order to ensure the driving capability of the gate line, especially for large-size high-resolution display products, the size of the transistor building the shift register circuit in the gate driving circuit is often designed to be large, so that the space occupied by the shift register circuit structure is large, and the realization of a narrow frame of the display panel is not facilitated.
Therefore, a technical problem to be solved by those skilled in the art is how to reduce the space of the display panel occupied by the gate driving circuit, so as to implement a narrow frame design of the display panel.
Disclosure of Invention
The embodiment of the invention provides a shift register, a gate driving circuit and a display panel, which are used for solving the problems that the gate driving circuit in the prior art occupies a larger space of the display panel and is not beneficial to realizing the narrow frame design of the display panel.
An embodiment of the present invention provides a shift register, including: the device comprises a pull-up module, a pull-down module, a reset module, a first control module, a second control module and an output module; wherein,
the control end and the input end of the pull-up module are both connected with the signal input end, and the output end of the pull-up module is connected with the first node; the pull-up module is used for pulling up the potential of the first node through a signal input by the signal input end under the control of the signal input end;
the first control end of the pull-down module is connected with the second node, the second control end is connected with the third node, the input end is connected with the low-level signal end, and the output end is connected with the first node; the pull-down module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the second node or the third node;
the control end of the reset module is connected with a reset signal end, the input end of the reset module is connected with the low-level signal end, and the output end of the reset module is connected with the first node; the reset module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the reset signal end;
a first control end of the first control module is connected with the first node, a second control end and a first input end are connected with a first reference signal end, a second input end is connected with the low-level signal end, and an output end is connected with the third node; the first control module is used for pulling down the potential of the third node through a signal of the low-level signal end under the control of the first node; under the control of the first reference signal terminal, the potential of the third node is pulled up through a signal of the first reference signal terminal;
a first control end of the second control module is connected with the first node, a second control end and a first input end of the second control module are connected with a second reference signal end, a second input end of the second control module is connected with the low-level signal end, and an output end of the second control module is connected with the second node; the second control module is used for pulling down the potential of the second node through a signal of the low-level signal end under the control of the first node; under the control of the second reference signal terminal, the potential of the second node is pulled up through the signals of the two reference signal terminals;
a first control end of the output module is connected with the first node, a second control end of the output module is connected with the second node, a third control end of the output module is connected with the third node, a first input end of the output module is connected with a first clock signal end, a second input end of the output module is connected with a second clock signal end, a third input end of the output module is connected with the low level signal end, and a first output end and a second output end of the output module are respectively connected with two adjacent grid lines; the output module is configured to output a signal of the first clock signal terminal and a signal of the second clock signal terminal to two adjacent gate lines through the first output terminal and the second output terminal, respectively, under the control of the first node; and under the control of the second node or the third node, pulling down the potential of the first output end through the signal of the low-level signal end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the output module includes: a first output unit and a second output unit; wherein,
the control end of the first output unit is connected with the first node, the first input end of the first output unit is connected with the first clock signal end, the second input end of the first output unit is connected with the second clock signal end, and the first output end and the second output end of the first output unit are respectively connected with two adjacent grid lines; the first output unit is configured to output a signal of the first clock signal terminal and a signal of the second clock signal terminal to two adjacent gate lines through the first output terminal and the second output terminal, respectively, under the control of the first node;
the first control end of the second output unit is connected with the second node, the second control end is connected with the third node, the input end is connected with the low-level signal end, and the output end is connected with the first output end of the first output unit; the second output unit is used for pulling down the potential of the first output end of the first output unit through the signal of the low-level signal end under the control of the second node or the third node.
In a possible implementation manner, in the shift register provided by an embodiment of the present invention, the first output unit includes: a first subunit and a second subunit; wherein,
the control end of the first subunit is connected with the first node, the input end of the first subunit is connected with the first clock signal end, the output end of the first subunit is connected with the corresponding grid line, and the first subunit is used for outputting a signal of the first clock signal end to the grid line connected with the output end under the control of the first node;
the control end of the second subunit is connected with the first node, the input end of the second subunit is connected with the second clock signal end, and the output end of the second subunit is connected with the next adjacent grid line of the grid lines connected with the output end of the first subunit; the second subunit is configured to output a signal at the second clock signal end to the gate line connected to the output end of the second subunit under the control of the first node.
In a possible implementation manner, in the shift register provided by an embodiment of the present invention, the first subunit includes: a first switching transistor and a first capacitor; wherein,
a grid electrode of the first switch transistor is connected with the first node, a source electrode of the first switch transistor is connected with the first clock signal end, and a drain electrode of the first switch transistor is connected with the corresponding grid line;
the first capacitor is connected between the first node and the drain of the first switching transistor.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second subunit includes: a second switching transistor and a second capacitor; wherein,
a grid electrode of the second switching transistor is connected with the first node, a source electrode of the second switching transistor is connected with the second clock signal end, and a drain electrode of the second switching transistor is connected with the next adjacent grid line of the grid lines connected with the output end of the first subunit;
the second capacitor is connected between the first node and the drain of the second switching transistor.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second output unit includes: a third switching transistor and a fourth switching transistor; wherein,
the grid electrode of the third switching transistor is connected with the second node, the source electrode of the third switching transistor is connected with the low-level signal end, and the drain electrode of the third switching transistor is connected with the first output end of the first output unit;
and the grid electrode of the fourth switching transistor is connected with the third node, the source electrode of the fourth switching transistor is connected with the low-level signal end, and the drain electrode of the fourth switching transistor is connected with the first output end of the first output unit.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the pull-up module includes: a fifth switching transistor;
and the grid electrode and the source electrode of the fifth switching transistor are both connected with the signal input end, and the drain electrode of the fifth switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the pull-down module includes: a sixth switching transistor and a seventh switching transistor; wherein,
a grid electrode of the sixth switching transistor is connected with the second node, a source electrode of the sixth switching transistor is connected with the low-level signal end, and a drain electrode of the sixth switching transistor is connected with the first node;
and the grid electrode of the seventh switching transistor is connected with the third node, the source electrode of the seventh switching transistor is connected with the low-level signal end, and the drain electrode of the seventh switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset module includes: an eighth switching transistor;
and the grid electrode of the eighth switching transistor is connected with the reset signal end, the source electrode of the eighth switching transistor is connected with the low-level signal end, and the drain electrode of the eighth switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first control module includes: a ninth switching transistor, a tenth switching transistor, an eleventh switching transistor, and a twelfth switching transistor; wherein,
a gate and a source of the ninth switching transistor are connected to the first reference signal terminal, and a drain of the ninth switching transistor is connected to a gate of the tenth switching transistor;
a source electrode of the tenth switching transistor is connected with the first reference signal end, and a drain electrode of the tenth switching transistor is connected with the third node;
a gate of the eleventh switching transistor is connected to the first node, a source thereof is connected to the low-level signal terminal, and a drain thereof is connected to a gate of the tenth switching transistor;
and the grid electrode of the twelfth switching transistor is connected with the first node, the source electrode of the twelfth switching transistor is connected with the low-level signal end, and the drain electrode of the twelfth switching transistor is connected with the third node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second control module includes: a thirteenth switching transistor, a fourteenth switching transistor, a fifteenth switching transistor, and a sixteenth switching transistor; wherein,
a gate and a source of the thirteenth switching transistor are connected to the second reference signal terminal, and a drain of the thirteenth switching transistor is connected to a gate of the fourteenth switching transistor;
a source of the fourteenth switching transistor is connected to the second reference signal terminal, and a drain thereof is connected to the second node;
a gate of the fifteenth switching transistor is connected to the first node, a source thereof is connected to the low-level signal terminal, and a drain thereof is connected to a gate of the fourteenth switching transistor;
and the grid electrode of the sixteenth switching transistor is connected with the first node, the source electrode of the sixteenth switching transistor is connected with the low-level signal end, and the drain electrode of the sixteenth switching transistor is connected with the second node.
In a possible implementation manner, the shift register provided in an embodiment of the present invention further includes: initializing a module;
the control end of the initialization module is connected with an initialization signal end, the input end of the initialization module is connected with the low level signal end, and the output end of the initialization module is connected with the first node; the initialization module is used for initializing the first node through the signal of the low level signal end under the control of the initialization signal end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the initialization module includes: a seventeenth switching transistor;
and the gate of the seventeenth switching transistor is connected with the initialization signal end, the source is connected with the low level signal end, and the drain is connected with the first node.
The embodiment of the invention provides a gate driving circuit, which comprises a plurality of cascaded shift registers, except the last stage of shift register, the first output end of each stage of shift register inputs a trigger signal to the signal input end of the next stage of shift register adjacent to the first output end, and the first output end and the second output end respectively input a gate scanning signal to the gate line connected with the first output end; and in the adjacent three shift registers, the second output end of the third shift register inputs a reset signal to the reset signal end of the first shift register.
The embodiment of the invention provides a display panel, which comprises the gate driving circuit provided by the embodiment of the invention.
The embodiment of the invention has the beneficial effects that:
the embodiment of the invention provides a shift register, a grid drive circuit and a display panel, wherein the shift register comprises: the device comprises a pull-up module, a pull-down module, a reset module, a first control module, a second control module and an output module; wherein,
the control end and the input end of the pull-up module are both connected with the signal input end, and the output end of the pull-up module is connected with the first node; the pull-up module is used for pulling up the potential of the first node through a signal input by the signal input end under the control of the signal input end;
the first control end of the pull-down module is connected with the second node, the second control end is connected with the third node, the input end is connected with the low-level signal end, and the output end is connected with the first node; the pull-down module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the second node or the third node;
the control end of the reset module is connected with the reset signal end, the input end of the reset module is connected with the low-level signal end, and the output end of the reset module is connected with the first node; the reset module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the reset signal end;
a first control end of the first control module is connected with the first node, a second control end and a first input end are connected with the first reference signal end, a second input end is connected with the low-level signal end, and an output end is connected with the third node; the first control module is used for pulling down the potential of the third node through a signal of the low-level signal end under the control of the first node; under the control of the first reference signal end, the potential of the third node is pulled up through the signal of the first reference signal end;
a first control end of the second control module is connected with the first node, a second control end and a first input end are connected with a second reference signal end, a second input end is connected with a low-level signal end, and an output end is connected with the second node; the second control module is used for pulling down the potential of the second node through a signal of the low-level signal end under the control of the first node; under the control of a second reference signal end, the potential of a second node is pulled up through signals of the two reference signal ends;
a first control end of the output module is connected with a first node, a second control end of the output module is connected with a second node, a third control end of the output module is connected with a third node, a first input end of the output module is connected with a first clock signal end, a second input end of the output module is connected with a second clock signal end, a third input end of the output module is connected with a low level signal end, and a first output end and a second output end of the output module are respectively connected with two adjacent grid lines; the output module is used for respectively outputting a signal of the first clock signal end and a signal of the second clock signal end to two adjacent grid lines through the first output end and the second output end under the control of the first node; and under the control of the second node or the third node, the potential of the first output end is pulled down through the signal of the low-level signal end.
Specifically, the shift register provided in the embodiment of the present invention can realize normal output of the scan signal through the pull-up module, the pull-down module, the reset module, the first control module, the second control module, and the output module; the output module of the shift register is provided with two output ends which are respectively connected with two adjacent grid lines, so that one shift register can correspond to the two grid lines, and further, scanning signals can be input to the two adjacent grid lines through one shift register; compared with the prior art that one shift register corresponds to one grid line, the invention can reduce the number of the shift registers by half, thereby reducing the occupied area of the grid driving circuit on the display panel, saving the manufacturing cost and being beneficial to realizing the narrow frame design of the display panel.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating an operation of a shift register according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
The following describes in detail specific embodiments of a shift register, a gate driver circuit, and a display panel according to embodiments of the present invention with reference to the accompanying drawings.
An embodiment of the present invention provides a shift register, as shown in fig. 1, which may include: the device comprises an upward pulling module 01, a downward pulling module 02, a resetting module 03, a first control module 04, a second control module 05 and an output module 06; wherein,
the control end and the Input end of the pull-up module 01 are both connected with the signal Input end, and the output end is connected with a first node P1; the pull-up module 01 is configured to pull up a potential of the first node P1 through a signal Input by the signal Input terminal under the control of the signal Input terminal Input;
a first control terminal of the pull-down module 02 is connected to the second node P2, a second control terminal is connected to the third node P3, an input terminal is connected to the low level signal terminal VSS, and an output terminal is connected to the first node P1; the pull-down module 02 is used for pulling down the potential of the first node P1 by the signal of the low level signal terminal VSS under the control of the second node P2 or the third node P3;
the control end of the Reset module 03 is connected with a Reset signal end Reset, the input end is connected with a low-level signal end VSS, and the output end is connected with a first node P1; the Reset module 03 is configured to pull down the potential of the first node P1 through a signal of the low-level signal terminal VSS under the control of the Reset signal terminal Reset;
a first control terminal of the first control module 04 is connected to the first node P1, a second control terminal and a first input terminal are connected to the first reference signal terminal Vref1, a second input terminal is connected to the low level signal terminal VSS, and an output terminal is connected to the third node P3; the first control module 04 is used for pulling down the potential of the third node P3 by the signal of the low level signal terminal VSS under the control of the first node P1; the potential of the third node P3 is pulled up by the signal of the first reference signal terminal Vref1 under the control of the first reference signal terminal Vref 1;
a first control terminal of the second control module 05 is connected to the first node P1, a second control terminal and a first input terminal are connected to a second reference signal terminal Vref2, a second input terminal is connected to the low-level signal terminal VSS, and an output terminal is connected to the second node P2; the second control module 05 is used for pulling down the potential of the second node P2 by the signal of the low level signal terminal VSS under the control of the first node P1; under the control of the second reference signal terminal Vref2, the potential of the second node P2 is pulled up by the signal of the second reference signal terminal Vref 2;
a first control terminal of the output module 06 is connected to a first node P1, a second control terminal is connected to a second node P2, a third control terminal is connected to a third node P3, a first input terminal is connected to a first clock signal terminal CLK1, a second input terminal is connected to a second clock signal terminal CLK2, a third input terminal is connected to a low level signal terminal VSS, and a first output terminal Out1 and a second output terminal Out2 are respectively connected to two adjacent gate lines; the output module 06 is configured to output a signal of the first clock signal terminal CLK1 and a signal of the second clock signal terminal CLK2 to two adjacent gate lines through the first output terminal Out1 and the second output terminal Out2, respectively, under the control of the first node P1; the potential of the first output terminal Out1 is pulled down by the signal of the low level signal terminal VSS under the control of the second node P2 or the third node P3.
Specifically, the shift register provided in the embodiment of the present invention can realize normal output of the scan signal through the pull-up module, the pull-down module, the reset module, the first control module, the second control module, and the output module; the output module of the shift register is provided with two output ends which are respectively connected with two adjacent grid lines, so that one shift register can correspond to the two grid lines, and further, scanning signals can be input to the two adjacent grid lines through one shift register; compared with the prior art that one shift register corresponds to one grid line, the invention can reduce the number of the shift registers by half, thereby reducing the occupied area of the grid driving circuit on the display panel, saving the manufacturing cost and being beneficial to realizing the narrow frame design of the display panel.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the output module 06 may include: a first output unit 061 and a second output unit 062; wherein,
a control terminal of the first output unit 061 is connected to the first node P1, a first input terminal is connected to the first clock signal terminal CLK1, a second input terminal is connected to the second clock signal terminal CLK2, and a first output terminal Out1 and a second output terminal Out2 are respectively connected to two adjacent gate lines; the first output unit 061 is configured to output a signal of the first clock signal terminal CLK1 and a signal of the second clock signal terminal CLK2 to two adjacent gate lines through the first output terminal Out1 and the second output terminal Out2, respectively, under the control of the first node P1;
the first control terminal of the second output unit 062 is connected to the second node P2, the second control terminal is connected to the third node P3, the input terminal is connected to the low level signal terminal VSS, and the output terminal is connected to the first output terminal Out1 of the first output unit 061; the second output unit 062 is configured to pull down the potential of the first output terminal Out1 of the first output unit 061 by a signal of the low-level signal terminal VSS under the control of the second node P2 or the third node P3.
Specifically, in the shift register provided in the embodiment of the present invention, the output module may include a first output unit and a second output unit, where the first output unit is configured to output a scan signal to two adjacent gate lines, so that one shift register can input the scan signal to two gate lines; the second output unit is used for pulling down the electric potential of the first output end, thereby closing the output of the shift register.
In specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the first output unit 061 may include: a first subunit 0611 and a second subunit 0612; wherein,
the control terminal of the first subunit 0611 is connected to the first node P1, the input terminal is connected to the first clock signal terminal CLK1, the output terminal Out1 is connected to the corresponding gate line, and the first subunit 0611 is configured to output a signal of the first clock signal terminal CLK1 to the gate line connected to the output terminal Out1 under the control of the first node P1;
the control terminal of the second subunit 0612 is connected to the first node P1, the input terminal is connected to the second clock signal terminal CLK2, and the output terminal is connected to the next gate line adjacent to the gate line connected to the output terminal Out1 of the first subunit 0611; the second subunit 0612 is configured to output the signal of the second clock signal terminal CLK2 to the gate line connected to the output terminal of the second subunit 0612 under the control of the first node P2.
Specifically, in the shift register provided in the embodiment of the present invention, the first output unit may include two sub-units, and the two sub-units correspond to one gate line respectively, so that one shift register can input a scan signal to the two gate lines.
In specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the first subunit 0611 may include: a first switching transistor T1 and a first capacitor C1; a gate electrode of the first switching transistor T1 is connected to a first node P1, a source electrode thereof is connected to a first clock signal terminal CLK1, and a drain electrode thereof is connected to a corresponding gate line; the first capacitor C1 is connected between the first node P1 and the drain of the first switching transistor T1. Specifically, the first switching transistor may be turned on under the control of the first node, and the turned-on first switching transistor may output a signal of the first clock signal terminal to a corresponding gate line.
In specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the second subunit 0612 may include: a second switching transistor T2 and a second capacitor C2; the gate of the second switching transistor T2 is connected to the first node P1, the source is connected to the second clock signal terminal CLK2, and the drain is connected to the next gate line adjacent to the gate line connected to the output terminal of the first subunit 0611; the second capacitor C2 is connected between the first node P1 and the drain of the second switching transistor T2. Specifically, the second switching transistor may be turned on under the control of the first node, and the turned-on second switching transistor may output a signal of the second clock signal terminal to a corresponding gate line.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the second output unit 062 may include: a third switching transistor T3 and a fourth switching transistor T4; the gate of the third switching transistor T3 is connected to the second node P2, the source is connected to the low level signal terminal VSS, and the drain is connected to the first output terminal Out1 of the first output unit 0611; the fourth switching transistor T4 has a gate connected to the third node P3, a source connected to the low level signal terminal VSS, and a drain connected to the first output terminal Out1 of the first output unit 0611. Specifically, the third switching transistor may be turned on under the control of the second node, and the turned-on third switching transistor may output a signal of the low level signal terminal to the first output terminal of the first output unit; the fourth switching transistor may be turned on under the control of the third node, and the turned-on fourth switching transistor may output a signal of the low level signal terminal to the first output terminal of the first output unit.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the pull-up module 01 may include: a fifth switching transistor T5; the gate and source of the fifth switching transistor T5 are both connected to the signal Input terminal Input, and the drain is connected to the first node P1. Specifically, the fifth switching transistor may be turned on under the control of the signal input terminal, and the turned-on fifth switching transistor may output the signal of the signal input terminal to the first node.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the pull-down module 02 may include: a sixth switching transistor T6 and a seventh switching transistor T7; the sixth switching transistor T6 has a gate connected to the second node P2, a source connected to the low level signal terminal VSS, and a drain connected to the first node P1; the seventh switching transistor T7 has a gate connected to the third node P3, a source connected to the low-level signal terminal VSS, and a drain connected to the first node P1. Specifically, the sixth switching transistor may be turned on under the control of the second node, and the turned-on sixth switching transistor may output a signal of the low-level signal terminal to the first node; the seventh switching transistor may be turned on under the control of the third node, and the turned-on seventh switching transistor may output a signal of the low-level signal terminal to the first node.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the reset module 03 may include: an eighth switching transistor T8; the eighth switching transistor T8 has a gate connected to a Reset signal terminal Reset, a source connected to a low level signal terminal VSS, and a drain connected to the first node P1. Specifically, the eighth switching transistor may be turned on under the control of the reset signal terminal, and the turned-on eighth switching transistor may output a signal of the low level signal terminal to the first node.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the first control module 04 includes: a ninth switching transistor T9, a tenth switching transistor T10, an eleventh switching transistor T11, and a twelfth switching transistor T12; wherein a gate and a source of the ninth switching transistor T9 are connected to the first reference signal terminal Vref1, and a drain is connected to a gate of the tenth switching transistor T10; a source of the tenth switching transistor T10 is connected to the first reference signal terminal Vref1, and a drain thereof is connected to the third node P3; the eleventh switching transistor T11 has a gate connected to the first node P1, a source connected to the low-level signal terminal VSS, and a drain connected to the gate of the tenth switching transistor T10; the twelfth switching transistor T12 has a gate connected to the first node P1, a source connected to the low-level signal terminal VSS, and a drain connected to the third node P3. Specifically, the ninth switching transistor may be turned on under the control of the first reference signal terminal, and the turned-on ninth switching transistor may output a signal of the first reference signal terminal to a gate of the tenth switching transistor; the tenth switching transistor may be turned on under control of a signal of the first reference signal terminal output from the drain of the ninth switching transistor, and the turned-on tenth switching transistor may output the signal of the first reference signal terminal to the third node; the eleventh switching transistor may be turned on under the control of the first node, and the turned-on eleventh switching transistor may output a signal of the low-level signal terminal to a gate of the tenth switching transistor; the twelfth switching transistor may be turned on under the control of the first node, and the turned-on twelfth switching transistor may output a signal of the low-level signal terminal to the third node.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the second control module 05 may include: a thirteenth switching transistor T13, a fourteenth switching transistor T14, a fifteenth switching transistor T15, and a sixteenth switching transistor T16; wherein a gate and a source of the thirteenth switching transistor T13 are connected to the second reference signal terminal Vref2, and a drain is connected to a gate of the fourteenth switching transistor T14; the fourteenth switching transistor T14 has a source connected to the second reference signal terminal Vref2 and a drain connected to the second node P2; a fifteenth switching transistor T15 having a gate connected to the first node P1, a source connected to the low-level signal terminal VSS, and a drain connected to the gate of the fourteenth switching transistor T14; the sixteenth switching transistor T16 has a gate connected to the first node P1, a source connected to the low-level signal terminal VSS, and a drain connected to the second node P2. Specifically, the thirteenth switching transistor may be turned on under the control of the second reference signal terminal, and the turned-on thirteenth switching transistor may output a signal of the second reference signal terminal to a gate of the fourteenth switching transistor; the fourteenth switching transistor may be turned on under control of a signal of the second reference signal terminal output from the drain of the thirteenth switching transistor, and the turned-on fourteenth switching transistor may output the signal of the second reference signal terminal to the second node; the fifteenth switching transistor may be turned on under the control of the first node, and the turned-on fifteenth switching transistor may output a signal of the low-level signal terminal to a gate of the fourteenth switching transistor; the sixteenth switching transistor may be turned on under the control of the first node, and the turned-on sixteenth switching transistor may output a signal of the low-level signal terminal to the second node.
In specific implementation, as shown in fig. 2, the shift register provided in the embodiment of the present invention may further include: an initialization module 07; the control end of the initialization module 07 is connected with an initialization signal end STV, the input end is connected with a low level signal end VSS, and the output end is connected with a first node P1; the initialization block 07 is configured to initialize the first node P1 by a signal of the low level signal terminal VSS under the control of the initialization signal terminal STV. Specifically, in the shift register provided in the embodiment of the present invention, the initialization module may further initialize the first node, so as to clear the residual charge of the previous frame.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the initialization module 07 may include: a seventeenth switching transistor T17; the seventeenth switching transistor T17 has a gate connected to the initialization signal terminal STV, a source connected to the low level signal terminal VSS, and a drain connected to the first node P1. Specifically, the seventeenth switching transistor may be turned on under the control of the initialization signal terminal, and the turned-on seventeenth switching transistor may output a signal of a low level signal terminal to the first node.
It should be noted that the switching Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), and is not limited herein. In specific implementations, the sources and drains of these transistors may be interchanged without specific distinction. A thin film transistor will be described as an example in describing specific embodiments.
The operation of the shift register according to the embodiment of the present invention will be described with reference to the shift register shown in fig. 2 and the input/output timing diagram shown in fig. 3 and shown in fig. 2. Specifically, three stages t1 to t3 in the input/output timing diagram shown in fig. 3 are selected. In the following description, a high level signal is denoted by 1, and a low level signal is denoted by 0.
In stage t1, Input is 1, CLK1 is 0-1, CLK2 is 0, Reset is 0, Vref1 is 1, and Vref2 is 0. Since Input is equal to 1, the fifth switching transistor T5 is turned on, and the turned-on fifth switching transistor T5 turns on the signal Input terminal Input and the first node P1, and at this time, since Input is equal to 1, the potential of the first node P1 is pulled high, so that the first switching transistor T1 and the second switching transistor T2 are turned on; the turned-on first switching transistor T1 turns on the first clock signal terminal CLK1 and the output terminal Out1, at this time, CLK1 is 0-1, as shown in fig. 3, the signal of the first clock signal terminal CLK1 is at a low level in the first two-thirds stage of the T1 stage, and at a high level in the last one-third stage, so that the output terminal Out1 starts to output a high level in the last one-third stage of the T1 stage; the turned-on second switching transistor T2 turns on the second clock signal terminal CLK2 and the output terminal Out2 at the stage CLK2 equals 0, so the output terminal Out2 outputs a low level. In addition, since the potential of the first node P1 is pulled high, the eleventh, twelfth, fifteenth and sixteenth switching transistors are all turned on; the tenth switching transistor T11 being turned on pulls down the potential of the gate of the tenth switching transistor T10; the turned-on twelfth switching transistor T12 pulls down the potential of the third node P3; the turned-on fifteenth switching transistor T15 pulls down the potential of the gate of the fourteenth switching transistor T14; the turned-on sixteenth switching transistor T16 pulls the potential of the second node P2 low.
In stage t2, Input is 0, CLK1 is 1-0, CLK2 is 1, Reset is 0, Vref1 is 1, and Vref2 is 0. At this stage, since Input is equal to 0, the fifth switching transistor T5 is turned off, the first node P1 maintains the high potential of the previous stage, and meanwhile, due to the bootstrap action of the first capacitor C1 and the second capacitor C2, the potential of the first node P1 further rises, and the first switching transistor T1 and the second switching transistor T2 continue to be turned on; the turned-on first switching transistor T1 turns on the first clock signal terminal CLK1 and the output terminal Out1, at this time, CLK1 is 1-0, as shown in fig. 3, the signal of the first clock signal terminal CLK1 is at a high level in the first two thirds of the period T2, and at a low level in the last one third of the period T2, so that the output terminal Out1 outputs a high level in the first two thirds of the period T2, and at a low level in the last one third of the period T2; the turned-on second switching transistor T2 turns on the second clock signal terminal CLK2 and the output terminal Out2 at the stage CLK2 equals 1, so the output terminal Out2 outputs a high level. In addition, the eleventh, twelfth, fifteenth, and sixteenth switching transistors maintain the on state of the previous stage.
In stage t3, Input is 0, CLK1 is 0-1, CLK2 is 0, Reset is 1, Vref1 is 1, and Vref2 is 0. Since Reset is equal to 1, the eighth switching transistor T8 is turned on, and the turned-on eighth switching transistor T8 turns on the low-level signal terminal VSS and the first node P1, and further pulls down the potential of the first node P1, so that the first switching transistor T1 and the second switching transistor T2 are turned off. At this stage, the ninth switch transistor T9 is turned on under the control of the first reference signal terminal Vref1, and the gate potential of the tenth switch transistor T10 is pulled high by the signal of the first reference signal terminal Vref1, so that the tenth switch transistor T10 is turned on; the turned-on tenth switching transistor T10 pulls high the potential of the third node P3, thereby turning on the seventh switching transistor T7 and the fourth switching transistor T4; the turned-on fourth switching transistor T4 turns on the low-level signal terminal VSS and the output terminal Out1, and performs noise reduction on the output terminal Out 1; the turned-on seventh switching transistor T7 turns on the low level signal terminal VSS and the first node P1, and thus reduces noise at the first node P1.
The shift register keeps the output state at stage t3 until the next frame arrives, the signal Input inputs a high-level turn-on signal, and the shift register repeats the above 3 operation stages.
It should be noted that the initialization signal terminal STV may input the initialization signal before each frame starts, so that the seventeenth switching transistor T17 is turned on, and the turned-on seventeenth switching transistor T17 turns on the low level signal terminal VSS and the first node P1, so as to initialize the first node P1 and remove the residual charges of the previous frame; the high and low levels of the signals of the first reference signal terminal Vref1 and the second reference signal terminal Vref2 are opposite, and can be interchanged every 2s, so as to control the corresponding switch transistor to be turned on.
Based on the same inventive concept, an embodiment of the present invention provides a gate driving circuit, including a plurality of cascaded shift registers provided in the embodiments of the present invention, except for a last stage of shift register, a first output terminal of each of the other shift registers inputs a trigger signal to a signal input terminal of a next stage of shift register adjacent thereto, and a first output terminal and a second output terminal respectively input a gate scanning signal to a gate line connected thereto; and in the adjacent three shift registers, the second output end of the third shift register inputs a reset signal to the reset signal end of the first shift register.
Specifically, for convenience of illustration, only four shift registers, namely, the nth stage shift register GOAN, the N +1 th stage shift register GOAN +1, the N +2 th stage shift register GOAN +2, and the N +3 th stage shift register GOAN +3, are shown in fig. 4. The scanning signal output end Out1 of each stage of shift register except the last stage of shift register not only outputs a grid opening signal to the grid line connected with the scanning signal output end, but also inputs a trigger signal to the signal Input end Input of the next stage of shift register adjacent to the scanning signal output end; the second output terminal Out2 of the third shift register among the adjacent three shift registers inputs the Reset signal to the Reset signal terminal Reset of the first shift register.
Based on the same inventive concept, embodiments of the present invention provide a display panel, including the gate driving circuit provided in embodiments of the present invention. The display panel can be applied to any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Since the principle of the display panel to solve the problem is similar to that of the gate driving circuit, the implementation of the display panel can refer to the implementation of the gate driving circuit, and repeated descriptions are omitted.
The embodiment of the invention provides a shift register, a grid drive circuit and a display panel, wherein the shift register comprises: the device comprises a pull-up module, a pull-down module, a reset module, a first control module, a second control module and an output module; wherein,
the control end and the input end of the pull-up module are both connected with the signal input end, and the output end of the pull-up module is connected with the first node; the pull-up module is used for pulling up the potential of the first node through a signal input by the signal input end under the control of the signal input end;
the first control end of the pull-down module is connected with the second node, the second control end is connected with the third node, the input end is connected with the low-level signal end, and the output end is connected with the first node; the pull-down module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the second node or the third node;
the control end of the reset module is connected with the reset signal end, the input end of the reset module is connected with the low-level signal end, and the output end of the reset module is connected with the first node; the reset module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the reset signal end;
a first control end of the first control module is connected with the first node, a second control end and a first input end are connected with the first reference signal end, a second input end is connected with the low-level signal end, and an output end is connected with the third node; the first control module is used for pulling down the potential of the third node through a signal of the low-level signal end under the control of the first node; under the control of the first reference signal end, the potential of the third node is pulled up through the signal of the first reference signal end;
a first control end of the second control module is connected with the first node, a second control end and a first input end are connected with a second reference signal end, a second input end is connected with a low-level signal end, and an output end is connected with the second node; the second control module is used for pulling down the potential of the second node through a signal of the low-level signal end under the control of the first node; under the control of a second reference signal end, the potential of a second node is pulled up through signals of the two reference signal ends;
a first control end of the output module is connected with a first node, a second control end of the output module is connected with a second node, a third control end of the output module is connected with a third node, a first input end of the output module is connected with a first clock signal end, a second input end of the output module is connected with a second clock signal end, a third input end of the output module is connected with a low level signal end, and a first output end and a second output end of the output module are respectively connected with two adjacent grid lines; the output module is used for respectively outputting a signal of the first clock signal end and a signal of the second clock signal end to two adjacent grid lines through the first output end and the second output end under the control of the first node; and under the control of the second node or the third node, the potential of the first output end is pulled down through the signal of the low-level signal end.
Specifically, the shift register provided in the embodiment of the present invention can realize normal output of the scan signal through the pull-up module, the pull-down module, the reset module, the first control module, the second control module, and the output module; the output module of the shift register is provided with two output ends which are respectively connected with two adjacent grid lines, so that one shift register can correspond to the two grid lines, and further, scanning signals can be input to the two adjacent grid lines through one shift register; compared with the prior art that one shift register corresponds to one grid line, the invention can reduce the number of the shift registers by half, thereby reducing the occupied area of the grid driving circuit on the display panel, saving the manufacturing cost and being beneficial to realizing the narrow frame design of the display panel.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. A shift register, comprising: the device comprises a pull-up module, a pull-down module, a reset module, a first control module, a second control module and an output module; wherein,
the control end and the input end of the pull-up module are both connected with the signal input end, and the output end of the pull-up module is connected with the first node; the pull-up module is used for pulling up the potential of the first node through a signal input by the signal input end under the control of the signal input end;
the first control end of the pull-down module is connected with the second node, the second control end is connected with the third node, the input end is connected with the low-level signal end, and the output end is connected with the first node; the pull-down module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the second node or the third node;
the control end of the reset module is connected with a reset signal end, the input end of the reset module is connected with the low-level signal end, and the output end of the reset module is connected with the first node; the reset module is used for pulling down the potential of the first node through a signal of the low-level signal end under the control of the reset signal end;
a first control end of the first control module is connected with the first node, a second control end and a first input end are connected with a first reference signal end, a second input end is connected with the low-level signal end, and an output end is connected with the third node; the first control module is used for pulling down the potential of the third node through a signal of the low-level signal end under the control of the first node; under the control of the first reference signal terminal, the potential of the third node is pulled up through a signal of the first reference signal terminal;
a first control end of the second control module is connected with the first node, a second control end and a first input end of the second control module are connected with a second reference signal end, a second input end of the second control module is connected with the low-level signal end, and an output end of the second control module is connected with the second node; the second control module is used for pulling down the potential of the second node through a signal of the low-level signal end under the control of the first node; under the control of the second reference signal terminal, the potential of the second node is pulled up through the signals of the two reference signal terminals;
a first control end of the output module is connected with the first node, a second control end of the output module is connected with the second node, a third control end of the output module is connected with the third node, a first input end of the output module is connected with a first clock signal end, a second input end of the output module is connected with a second clock signal end, a third input end of the output module is connected with the low level signal end, and a first output end and a second output end of the output module are respectively connected with two adjacent grid lines; the output module is configured to output a signal of the first clock signal terminal and a signal of the second clock signal terminal to two adjacent gate lines through the first output terminal and the second output terminal, respectively, under the control of the first node; and under the control of the second node or the third node, pulling down the potential of the first output end through the signal of the low-level signal end.
2. The shift register of claim 1, wherein the output module comprises: a first output unit and a second output unit; wherein,
the control end of the first output unit is connected with the first node, the first input end of the first output unit is connected with the first clock signal end, the second input end of the first output unit is connected with the second clock signal end, and the first output end and the second output end of the first output unit are respectively connected with two adjacent grid lines; the first output unit is configured to output a signal of the first clock signal terminal and a signal of the second clock signal terminal to two adjacent gate lines through the first output terminal and the second output terminal, respectively, under the control of the first node;
the first control end of the second output unit is connected with the second node, the second control end is connected with the third node, the input end is connected with the low-level signal end, and the output end is connected with the first output end of the first output unit; the second output unit is used for pulling down the potential of the first output end of the first output unit through the signal of the low-level signal end under the control of the second node or the third node.
3. The shift register of claim 2, wherein the first output unit comprises: a first subunit and a second subunit; wherein,
the control end of the first subunit is connected with the first node, the input end of the first subunit is connected with the first clock signal end, the output end of the first subunit is connected with the corresponding grid line, and the first subunit is used for outputting a signal of the first clock signal end to the grid line connected with the output end under the control of the first node;
the control end of the second subunit is connected with the first node, the input end of the second subunit is connected with the second clock signal end, and the output end of the second subunit is connected with the next adjacent grid line of the grid lines connected with the output end of the first subunit; the second subunit is configured to output a signal at the second clock signal end to the gate line connected to the output end of the second subunit under the control of the first node.
4. The shift register of claim 3, wherein the first subunit comprises: a first switching transistor and a first capacitor; wherein,
a grid electrode of the first switch transistor is connected with the first node, a source electrode of the first switch transistor is connected with the first clock signal end, and a drain electrode of the first switch transistor is connected with the corresponding grid line;
the first capacitor is connected between the first node and the drain of the first switching transistor.
5. The shift register of claim 3, wherein the second subunit comprises: a second switching transistor and a second capacitor; wherein,
a grid electrode of the second switching transistor is connected with the first node, a source electrode of the second switching transistor is connected with the second clock signal end, and a drain electrode of the second switching transistor is connected with the next adjacent grid line of the grid lines connected with the output end of the first subunit;
the second capacitor is connected between the first node and the drain of the second switching transistor.
6. The shift register of claim 2, wherein the second output unit comprises: a third switching transistor and a fourth switching transistor; wherein,
the grid electrode of the third switching transistor is connected with the second node, the source electrode of the third switching transistor is connected with the low-level signal end, and the drain electrode of the third switching transistor is connected with the first output end of the first output unit;
and the grid electrode of the fourth switching transistor is connected with the third node, the source electrode of the fourth switching transistor is connected with the low-level signal end, and the drain electrode of the fourth switching transistor is connected with the first output end of the first output unit.
7. The shift register of any of claims 1-6, wherein the pull-up module comprises: a fifth switching transistor;
and the grid electrode and the source electrode of the fifth switching transistor are both connected with the signal input end, and the drain electrode of the fifth switching transistor is connected with the first node.
8. The shift register of any of claims 1-6, wherein the pull-down module comprises: a sixth switching transistor and a seventh switching transistor; wherein,
a grid electrode of the sixth switching transistor is connected with the second node, a source electrode of the sixth switching transistor is connected with the low-level signal end, and a drain electrode of the sixth switching transistor is connected with the first node;
and the grid electrode of the seventh switching transistor is connected with the third node, the source electrode of the seventh switching transistor is connected with the low-level signal end, and the drain electrode of the seventh switching transistor is connected with the first node.
9. The shift register of any of claims 1-6, wherein the reset module comprises: an eighth switching transistor;
and the grid electrode of the eighth switching transistor is connected with the reset signal end, the source electrode of the eighth switching transistor is connected with the low-level signal end, and the drain electrode of the eighth switching transistor is connected with the first node.
10. The shift register of any one of claims 1-6, wherein the first control module comprises: a ninth switching transistor, a tenth switching transistor, an eleventh switching transistor, and a twelfth switching transistor; wherein,
a gate and a source of the ninth switching transistor are connected to the first reference signal terminal, and a drain of the ninth switching transistor is connected to a gate of the tenth switching transistor;
a source electrode of the tenth switching transistor is connected with the first reference signal end, and a drain electrode of the tenth switching transistor is connected with the third node;
a gate of the eleventh switching transistor is connected to the first node, a source thereof is connected to the low-level signal terminal, and a drain thereof is connected to a gate of the tenth switching transistor;
and the grid electrode of the twelfth switching transistor is connected with the first node, the source electrode of the twelfth switching transistor is connected with the low-level signal end, and the drain electrode of the twelfth switching transistor is connected with the third node.
11. The shift register of any one of claims 1-6, wherein the second control module comprises: a thirteenth switching transistor, a fourteenth switching transistor, a fifteenth switching transistor, and a sixteenth switching transistor; wherein,
a gate and a source of the thirteenth switching transistor are connected to the second reference signal terminal, and a drain of the thirteenth switching transistor is connected to a gate of the fourteenth switching transistor;
a source of the fourteenth switching transistor is connected to the second reference signal terminal, and a drain thereof is connected to the second node;
a gate of the fifteenth switching transistor is connected to the first node, a source thereof is connected to the low-level signal terminal, and a drain thereof is connected to a gate of the fourteenth switching transistor;
and the grid electrode of the sixteenth switching transistor is connected with the first node, the source electrode of the sixteenth switching transistor is connected with the low-level signal end, and the drain electrode of the sixteenth switching transistor is connected with the second node.
12. The shift register of claim 1, further comprising: initializing a module;
the control end of the initialization module is connected with an initialization signal end, the input end of the initialization module is connected with the low level signal end, and the output end of the initialization module is connected with the first node; the initialization module is used for initializing the first node through the signal of the low level signal end under the control of the initialization signal end.
13. The shift register of claim 12, wherein the initialization module comprises: a seventeenth switching transistor;
and the gate of the seventeenth switching transistor is connected with the initialization signal end, the source is connected with the low level signal end, and the drain is connected with the first node.
14. A gate driving circuit comprising a plurality of shift registers according to any one of claims 1 to 13, cascaded, wherein the first output terminal of each of the shift registers except the last shift register inputs a trigger signal to the signal input terminal of the next shift register adjacent thereto, and the first output terminal and the second output terminal input a gate scanning signal to the gate line connected thereto, respectively; and in the adjacent three shift registers, the second output end of the third shift register inputs a reset signal to the reset signal end of the first shift register.
15. A display panel comprising the gate driver circuit according to claim 14.
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| CN108511025A (en) * | 2018-04-12 | 2018-09-07 | 京东方科技集团股份有限公司 | A kind of shift register cell, gate driving circuit and display device |
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| US11101013B2 (en) | 2018-05-30 | 2021-08-24 | Beijing Boe Display Technology Co., Ltd. | Shift register, method for fabricating inverter, gate driving circuit, and display device |
| CN108766336A (en) * | 2018-05-30 | 2018-11-06 | 京东方科技集团股份有限公司 | Shift register, phase inverter production method, gate driving circuit and display device |
| CN109166542A (en) * | 2018-09-26 | 2019-01-08 | 合肥鑫晟光电科技有限公司 | Shift register cell and driving method, gate driving circuit, display device |
| CN109166542B (en) * | 2018-09-26 | 2024-05-07 | 合肥鑫晟光电科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN109461401A (en) * | 2018-12-20 | 2019-03-12 | 昆山龙腾光电有限公司 | Gate driving circuit and its display device |
| WO2020133823A1 (en) * | 2018-12-27 | 2020-07-02 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
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