CN106531654A - Chip input pin test method and device - Google Patents
Chip input pin test method and device Download PDFInfo
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- CN106531654A CN106531654A CN201610999240.6A CN201610999240A CN106531654A CN 106531654 A CN106531654 A CN 106531654A CN 201610999240 A CN201610999240 A CN 201610999240A CN 106531654 A CN106531654 A CN 106531654A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The invention provides a chip input pin test method and device. The method switches the current mode of a chip according to a control signal, inputs an excitation sequence to the to-be-tested pin of the chip, and then stores a value received by the to-be-tested pin in a storage unit by using a sampling unit, outputs the value of the storage unit by an output pin (another pin with a good output function and corresponding to the to-be-tested pin) corresponding to the to-be-tested pin, compares the output value with a preset output value mirror at a verifying unit so as to automatically check whether the input function of the to-be-tested pin of the chip is normal. Thus, testing can be carried out in a bare chip stage, which is equivalent to a whole test method, thereby greatly reducing test cost. In addition, the input excitation sequence can be customized according to actual needs, and has high flexibility and fault detection coverage.
Description
Technical field
The present invention relates to chip testing field, more particularly to a kind of chip input pin method of testing and device.
Background technology
In current chip testing technology, it is impossible to easily the pin of chip is tested.Generally need when core
After piece encapsulation is finished, configure correlated serieses completely to test the pin function of chip in whole machine running software.With
Also more and more easily there are yield issues in the fast development of chip features process, chip pin, thus to chip pin
Test just becomes a particularly significant ring in chip testing field.If pin test does not pass through, chip will be unable to accurately input
Or output data, the performance for directly influencing chip is used.If also according to existing method of testing, when whole machine is verified
Chip pin could be verified, if pin breaks down, because it is found that the time of problem is too late, now chip is complete
Into encapsulation, re-replace chip and will waste a large amount of financial resource and material resource, substantially increase cost.
The content of the invention
For this reason, it may be necessary to provide a kind of technical scheme of chip input pin test, survey to solve existing chip pin
Method for testing, is tested to the function of chip pin on whole machine that can only be after chip is installed again, causes testing cost height, core
The problems such as piece changes complicated, waste a large amount of physical resources and financial resources.
For achieving the above object, a kind of chip input pin test device is inventor provided, the chip is included at least
One pin to be measured, described device include that output valve setting unit, mode setting unit, pin setting unit, excitation generate list
Unit, sampling unit, memory element, output unit and verification unit；
The output valve setting unit is used for arranging output preset value；
The mode setting unit is used for receiving test signal, allows chip in test pattern, the pin setting unit
For the pin to be measured of chip is set to input state；
The excitation signal generating unit is used for generating activation sequence, and activation sequence is transmitted to the pin to be measured of chip；It is raw
Into activation sequence it is identical with output preset value, the activation sequence includes at least one digit number value, and each pin correspondence to be measured connects
Receive the one digit number value in activation sequence；
The mode setting unit is additionally operable to receive sampled signal, allows chip in sampling configuration, and the sampling unit is used
Sample in the numerical value received to each pin correspondence to be measured, and sampled result is stored in memory element；
The mode setting unit is used for receiving sampled output signal, allows chip in sampling output mode, the output
, for the sampled result stored in memory element is transmitted to verification unit by output pin, each pin to be measured is corresponding for unit
One output pin, output pin are used for exporting one digit number value；
The verification unit is used for judging whether the numerical value of output unit output to be identical with output preset value, if then verifying
Pass through, otherwise verify and do not pass through.
Further, the memory element is depositor group, and the depositor group includes posting for multiple preset orders arrangement
Storage, each depositor are used for storage from the numerical value of a pin up-sampling to be measured.
Further, the activation sequence is the sequence being made up of numerical value " 0 " or " 1 ".
Further, the verification unit is additionally operable to differ with output preset value in the numerical value for judging output unit output
When, identify numerical value and the output preset value digit that different numerical value are located between the two of output unit output.
Further, the quantity of the chip is for multiple, and the model of chip is identical, and the excitation signal generating unit is used for giving birth to
Into activation sequence, and the activation sequence of generation is transmitted to the pin to be measured of the different chips of same model.
Inventor additionally provides a kind of chip input pin method of testing, and methods described is applied to chip input pin test
Device, the chip include at least one pin to be measured, and described device includes output valve setting unit, mode setting unit, draws
Foot setting unit, excitation signal generating unit, sampling unit, memory element, output unit and verification unit；Methods described includes following
Step：
Output valve setting unit arranges output preset value；
Mode setting unit receives test signal, allows chip in test pattern, and pin setting unit is by the to be measured of chip
Pin is set to input state；
Excitation signal generating unit generates activation sequence, and activation sequence is transmitted to the pin to be measured of chip；The excitation of generation
Sequence is identical with output preset value, and activation sequence includes at least one digit number value, and each pin correspondence to be measured is received in activation sequence
One digit number value；
Mode setting unit receives sampled signal, allows chip in sampling configuration, and sampling unit is to each pin pair to be measured
The numerical value that should be received is sampled, and sampled result is stored in memory element；
Mode setting unit receives sampled output signal, allows chip in sampling output mode, and output unit will store single
The sampled result stored in unit is transmitted to verification unit by output pin, one output pin of each pin correspondence to be measured, output
Pin is used for exporting one digit number value；
Verification unit judges whether the numerical value of output unit output is identical with output preset value, if then verification passes through, no
Then verify and do not pass through.
Further, the memory element is depositor group, and the depositor group includes posting for multiple preset orders arrangement
Storage, each depositor are used for storage from the numerical value of a pin up-sampling to be measured.
Further, the activation sequence is the sequence being made up of numerical value " 0 " or " 1 ".
Further, methods described also includes：
Verification unit identifies output unit defeated when the numerical value for judging output unit output is differed with output preset value
The numerical value for going out and the output preset value digit that different numerical value are located between the two.
Further, the quantity of the chip is for multiple, and the model of chip is identical, and methods described includes：
Excitation signal generating unit generates activation sequence, and the activation sequence of generation is transmitted to the different cores of same model
The pin to be measured of piece.
Chip input pin method of testing and device described in above-mentioned technical proposal, methods described are applied to chip input and draw
Foot test device, the chip include at least one pin to be measured, and it is single that described device includes that output valve setting unit, pattern are arranged
Unit, pin setting unit, excitation signal generating unit, sampling unit, memory element, output unit and verification unit；Methods described bag
Include following steps：Output valve setting unit arranges output preset value first；Then mode setting unit receives test signal, allows core
Piece is in test pattern, and the pin to be measured of chip is set to input state by pin setting unit；Signal generating unit life is encouraged then
Into activation sequence, and activation sequence is transmitted to the pin to be measured of chip；Then mode setting unit receives sampled signal, allows core
Piece is in sampling configuration, and sampling unit is sampled to the numerical value that each pin correspondence to be measured is received, and sampled result is stored
In memory element；Then mode setting unit receives sampled output signal, allows chip in sampling output mode, output unit
The sampled result stored in memory element is transmitted to verification unit by output pin；Then verification unit judges output unit
Whether the numerical value of output is identical with output preset value, if then verification passes through, otherwise verifies and does not pass through.So, it is in chip
Just its pin can be tested during unencapsulated nude film, it will filter out when chip is also unencapsulated with the presence of pin failure
Chip, is reduced because finding that failure problems cause unnecessary waste too late, effectively save testing cost.
Description of the drawings
The schematic diagram of the chip input pin test device that Fig. 1 is related to for an embodiment of the present invention；
Fig. 2 is the schematic diagram of the chip input pin test device that another embodiment of the invention is related to；
Fig. 3 is the schematic diagram of the self testing circuit that another embodiment of the invention is related to；
The schematic diagram of the chip input pin method of testing that Fig. 4 is related to for an embodiment of the present invention；
Description of reference numerals：
101st, output valve setting unit；
102nd, mode setting unit；
103rd, pin setting unit；
104th, encourage signal generating unit；
105th, sampling unit；
106th, memory element；
107th, output unit；
108th, verification unit.
Specific embodiment
By describing the technology contents of technical scheme, structural features in detail, realizing purpose and effect, below in conjunction with concrete reality
Apply example and coordinate accompanying drawing to be explained in detail.
Fig. 1 is referred to, the schematic diagram of the chip input pin test device described in an embodiment of the present invention.
The chip includes at least one pin to be measured, and it is single that described device includes that output valve setting unit 101, pattern is arranged
Unit 102, pin setting unit 103, excitation signal generating unit 104, sampling unit 105, memory element 106, output unit 107 and school
Verification certificate unit 108.Pin (pin), is called pin, is the wiring from the extraction of integrated circuit (chip) internal circuit with peripheral circuit,
All of pin just constitutes the external interface of this chip block.
The output valve setting unit 101 is used for arranging output preset value；
The mode setting unit 102 is used for receiving test signal, allows chip in test pattern, and the pin arranges single
Unit 103 is for being set to input state by the pin to be measured of chip；
The excitation signal generating unit 104 is used for generating activation sequence, and activation sequence is transmitted to the pin to be measured of chip；
The activation sequence of generation is identical with output preset value, and the activation sequence includes at least one digit number value, each pin correspondence to be measured
Receive the one digit number value in activation sequence；
The mode setting unit 102 is additionally operable to receive sampled signal, allows chip in sampling configuration, the sampling unit
105 for sampling to the numerical value that each pin correspondence to be measured is received, and sampled result is stored in memory element 106；
The mode setting unit 102 is used for receiving sampled output signal, allows chip in sampling output mode, described defeated
Go out unit 107 for the sampled result stored in memory element 106 is transmitted to verification unit 108 by output pin, it is each
One output pin of pin correspondence to be measured, output pin are used for exporting one digit number value；
The verification unit 108 is used for judging whether the numerical value of output unit output to be identical with output preset value, if then
Verification passes through, and otherwise verifies and does not pass through.
When using chip input pin test device, output valve setting unit 101 arranges output preset value first.It is described
Output preset value is idea output, if the value through the pin output of chip is identical with output preset value, illustrates to meet expection,
The chip pin function is normal, and an otherwise chip at least pin function has obstacle.Output arranges value can pass through technical staff
Input is obtained according to actual needs.
Then mode setting unit 102 receives test signal, allows chip in test pattern, the pin setting unit
The pin to be measured of chip is set to input state by 103.Mode setting unit can be realized with corresponding switching logic, be surveyed
Die trial formula is that, for functional mode, in chip under test pattern, the control signal of test pattern is set to high electricity
Flat, the control signal of functional mode (normal mode of operation) is set to low level.In the present embodiment, the object of test is
Whether the pin under input state, the i.e. input function of test chip pin are normal, so that pin to be measured is arranged
For input state.Pin setting unit can be realized by ternary output control circuit, in test mode, tri-state control end
Being worth and effective status being exported for high resistant, the outfan of the ternary output control circuit of PAD is high-impedance state, pin to be measured now is subject to
The driving of activation sequence and be in input state.
Then encourage signal generating unit 104 to generate activation sequence, and activation sequence is transmitted to the pin to be measured of chip.Generate
Activation sequence it is identical with output preset value, the activation sequence includes at least one digit number value, and each pin correspondence to be measured is received
One digit number value in activation sequence.In the present embodiment, the activation sequence is the sequence being made up of numerical value " 0 " or " 1 ".Example
If a certain chip pin number to be measured is 20, then the activation sequence being input into is served as reasons the word for amounting to 20 that " 0 " or " 1 " constitute
Symbol string, each pin to be measured are used for receiving one " 0 " or " 1 " numerical value.Activation sequence is arranged to into identical with output preset value, this
Sample is after activation sequence is transmitted by pin to be measured, then the value of output is compared with output preset value, it is possible to sentence
Whether the input function of disconnected pin to be measured is normal.
Then mode setting unit 102 receives sampled signal, allows chip in sampling configuration, the sampling unit 105 pairs
The numerical value that each pin correspondence to be measured is received is sampled, and sampled result is stored in memory element 106.Chip is in and adopts
Original mold formula, represents that the pin to be measured of chip has received activation sequence completely, i.e., on each pin to be measured, correspondence have received one
The numerical value of position activation sequence.On circuit realiration, high level can be set in the control signal of test pattern, chip is in test
During pattern, sampling configuration is in by the control signal of sampling configuration is set to high level by chip.Preferably, sampling configuration
Control signal can be by being separately provided (be different from test control circuit) sampling control circuit to realize.
In the present embodiment, the memory element 106 is depositor group, and the depositor group includes multiple preset orders
The depositor of arrangement, each depositor are used for storage from the numerical value of a pin up-sampling to be measured.Sampling unit can be with sampling
Circuit is sampled to the numerical value received by each pin to be measured, and the numerical value of sampling is stored in the pin to be measured realizing
Corresponding depositor.Such as Fig. 2, it is a certain chip input pin test device schematic diagram, the chip includes multiple pins to be measured,
One self testing circuit of each pin correspondence to be measured, the schematic diagram of self testing circuit are as shown in Figure 3.The quantity of such as pin to be measured is
3, including pin A to be measured, pin B to be measured and pin C to be measured；Pin A correspondences depositor a to be measured, pin B correspondences to be measured are deposited
Device b, pin C correspondences depositor c to be measured；The activation sequence of input is " 101 ", and wherein, the numerical value received by pin A to be measured is
" 1 ", the numerical value received by pin B to be measured are " 0 ", and the numerical value received by pin C to be measured is " 1 ", then sampling unit draws to be measured
After the numerical value received by foot is sampled, the value of depositor a can be entered as " 1 ", the value of depositor b is entered as " 0 ", depositor
The value of c is entered as " 1 ".
Then the mode setting unit 102 receives sampled output signal, allows chip in sampling output mode, described defeated
Go out unit 107 to transmit to verification unit 108 sampled result stored in memory element 106 by output pin.Chip is in
Sampling output mode, represents that the numerical value that received of pin to be measured of chip has been sampled and finishes, i.e., on each pin to be measured
The numerical value of the activation sequence for receiving is stored in corresponding depositor.Test pattern is relative to normal operating conditions
Under functional mode for, include sampling configuration and sampling output mode.From on circuit realiration, can be using controlling of sampling electricity
, come the switching realizing sampling between output mode and sampling configuration, the sampling control circuit is used for defeated for road and test control circuit
Enter sampling configuration control signal, the test control circuit is used for input testing mode control signal.Test pattern control signal
High level is set to, sampling configuration control signal is low level, represents chip in sampling output mode；Test pattern control signal
For high level, sampling configuration control signal is high level, represents that chip is in sampling configuration.
In the present embodiment, one output pin of each pin correspondence to be measured, output pin are used for exporting one digit number value.This
Invention is that the input function to chip pin is tested, but each pin can be only in a certain state in synchronization
(input, or output).When pin to be measured is in input state, each pin to be measured can receive an activation sequence
Numerical value；When needing to export the numerical value of each pin to be measured of sampling from depositor, then need by output pin come complete
Into test.The output pin is to have passed through the pin that output is tested, output function is good.In this manner it is ensured that from depositor
The numerical value of output will not be changed or accurately cannot be exported because the output function of pin is damaged.Such as a certain chip is present
100 pins, wherein 50 pins are to be measured, 50 pins in addition are normal through test output function, can draw to be measured
Foot is corresponded with the normal pin of output function, number of a certain pin through samples storage in the corresponding depositor of the pin
Value, is exported by the corresponding output pin of the pin.There are 101 pins, wherein 51 pins in a certain chip for another example
Input function it is to be measured, 50 pins are normal through test output functions, can be only done 50 pins in each clock cycle
Test, then can be divided to two clock cycle to complete the test of above-mentioned 51 pin input functions, first clock cycle with it is upper
One way of example is the same, and here is omitted；Second clock cycle, then select from the normal pin of 50 output functions
Select one it is corresponding with that pin to be measured for also not carrying out input function test.Also do not carry out input function test that
The numerical value stored in the corresponding depositor of individual pin to be measured, is exported by the selected normal pin of output function.
Then verification unit 108 judges whether the numerical value of output unit output is identical with output preset value, if then verifying
Pass through, otherwise verify and do not pass through.In the present embodiment, the verification unit and excitation signal generating unit are chip testing board,
Chip testing board is a kind of chip testing devices of specialty, can be used for producing test and excitation and observation checks chip output
Response sequence.In further embodiments, the verification unit is additionally operable to pre- with output in the numerical value for judging output unit output
If value is differed, numerical value and the output preset value digit that different numerical value are located between the two of output unit output are identified.
Such as pin number to be measured is 3, and output preset value is " 101 ", and activation sequence is also " 101 ", and exports single
The numerical value of unit's output is " 111 ", as second input and the output of activation sequence are mismatched, then can identify second presence
Problem.Again as the second bit value is to obtain output, and the pin to be measured corresponding to depositor b from depositor b for drawing
Foot b, then illustrate that pin b has that technical staff can do to pin b and further detect, take measures on customs clearance and located
Reason.
In certain embodiments, the quantity of the chip is for multiple, and the model of chip is identical, the excitation signal generating unit
For generating activation sequence, and the activation sequence of generation is transmitted to the pin to be measured of the different chips of same model.Survey
Commissioning stage can be to the chip of same model simultaneously output drive sequence, to accelerate testing efficiency.For example now with A, B, C tri-
Chip block is to be detected, and the model of tri- chip block of A, B, C is identical, so that tester table can pass through identical activation sequence pair
This three chip block can be tested simultaneously.Assume that the corresponding pin number to be measured of chip A, B, C is 50, then tester table
The activation sequence of 50 will be generated, and the activation sequence for being generated is respectively sent to into chip A, chip B and chip C.Each core
The each of piece treats that pin correspondence receives the one digit number value in activation sequence, specific to for example aforementioned side of testing process of every chip piece
Described in formula, here is omitted.
Said apparatus current chip can be switched according to control signal residing for pattern, and input stimulus sequence is to chip
Pin to be measured, then the numerical value that pin to be measured is received is stored in memory element by sampling unit, then by be measured
The value of the corresponding output pin of pin (output function is good, another pin corresponding with pin to be measured) output memory element,
And verification unit by export value with default output valve image ratio compared with so as to the input function of automatic Verification chip pin to be measured
It is whether normal so that test can be carried out under the nude film stage in chip, equivalent to the mode of system test, greatly reduced
Testing cost.Additionally, the activation sequence of input completely can self-defined confirmation according to the actual requirements, with very high motility and
Failure checking cover ratio.
Fig. 4 is referred to, is the schematic diagram of the chip input pin method of testing that an embodiment of the present invention is related to.The side
Method is applied to chip input pin test device, and the chip includes at least one pin to be measured, and described device includes output valve
Setting unit, mode setting unit, pin setting unit, excitation signal generating unit, sampling unit, memory element, output unit and
Verification unit；The method comprising the steps of：
Initially enter step S301 output valve setting unit and output preset value is set.The output preset value is preferable output
Value, if the value through the pin output of chip is identical with output preset value, illustrates to meet expection, and the chip pin function is normal,
There is obstacle in an otherwise chip at least pin function.Output arranges value can be input into according to actual needs by technical staff
Arrive.
Then enter step S302 mode setting unit and receive test signal, allow chip in test pattern, pin is arranged
The pin to be measured of chip is set to input state by unit.Mode setting unit can be realized with corresponding switching logic,
For test pattern is comparable to functional mode, in chip under test pattern, the control signal of test pattern is set to height
Level, the control signal of functional mode (normal mode of operation) are set to low level.In the present embodiment, the object of test
It is the pin under input state, i.e., whether the input function of test chip pin is normal, so that pin to be measured is set
It is set to input state.Pin setting unit can be realized by ternary output control circuit, in test mode, tri-state control end
Value be that high resistant exports effective status, the outfan of the ternary output control circuit of PAD is high-impedance state, and pin to be measured now is received
Input state is in the driving of activation sequence.
Then enter step S303 excitation signal generating unit and generate activation sequence, and activation sequence is transmitted to be measured to chip
Pin.The activation sequence of generation is identical with output preset value, and the activation sequence includes at least one digit number value, each pin to be measured
Correspondence receives the one digit number value in activation sequence.In the present embodiment, the activation sequence is to be made up of numerical value " 0 " or " 1 "
Sequence.Such as a certain chip pin number to be measured is 20, then what the activation sequence being input into served as reasons that " 0 " or " 1 " constitute is total to
The character string of meter 20, each pin to be measured are used for receiving one " 0 " or " 1 " numerical value.Activation sequence is arranged to into pre- with output
If value is identical, so after activation sequence is transmitted by pin to be measured, then the value of output is compared with output preset value
Compared with, it is possible to judge whether the input function of pin to be measured is normal.
Then enter step S304 mode setting unit and receive sampled signal, chip is allowed in sampling configuration, sampling unit
The numerical value that each pin correspondence to be measured is received is sampled, and sampled result is stored in memory element.Chip is in and adopts
Original mold formula, represents that the pin to be measured of chip has received activation sequence completely, i.e., on each pin to be measured, correspondence have received one
The numerical value of position activation sequence, can be by being set to high level by the control signal of sampling configuration, by the control signal of test pattern
Low level is set to, allows chip to be in sampling configuration.
In the present embodiment, the memory element is depositor group, and the depositor group includes multiple preset orders row
The depositor of row, each depositor are used for storage from the numerical value of a pin up-sampling to be measured.Sampling unit can be with sampling electricity
The numerical value received by each pin to be measured is sampled, and the numerical value of sampling is stored in into the pin pair to be measured realizing in road
The depositor answered.The quantity of such as pin to be measured is 3, including pin A to be measured, pin B to be measured and pin C to be measured；It is to be measured to draw
Foot A correspondence depositor a, pin B correspondences depositor b to be measured, pin C correspondences depositor c to be measured；The activation sequence of input is
" 101 ", wherein, the numerical value received by pin A to be measured be " 1 ", the numerical value received by pin B to be measured be " 0 ", pin C institutes to be measured
The numerical value of reception is " 1 ", then, after sampling unit is sampled to the numerical value received by pin to be measured, can assign the value of depositor a
It is worth for " 1 ", the value of depositor b is entered as " 0 ", and the value of depositor c is entered as " 1 ".
Then enter step S305 mode setting unit and receive sampled output signal, chip is allowed in sampling output mode,
The sampled result stored in memory element is transmitted to verification unit by output unit by output pin.Chip is in sampling output
Pattern, represents that the numerical value that received of pin to be measured of chip has been sampled and finishes, i.e., for receiving on each pin to be measured
The numerical value of position activation sequence is stored in corresponding depositor.Test pattern is relative to the function under normal operating conditions
For pattern, sampling configuration and sampling output mode is included.From on circuit realiration, sampling control circuit and test can be adopted
Control circuit is used for input sample mould the switching realizing sampling between output mode and sampling configuration, the sampling control circuit
Formula control signal, the test control circuit are used for input testing mode control signal.Test pattern control signal is set to high electricity
Flat, sampling configuration control signal is low level, represents chip in sampling output mode；Test pattern control signal is high electricity
Flat, sampling configuration control signal is high level, represents that chip is in sampling configuration.
In the present embodiment, one output pin of each pin correspondence to be measured, output pin are used for exporting one digit number value.This
Invention is that the input function to chip pin is tested, but each pin can be only in a certain state in synchronization
(input, or output).When pin to be measured is in input state, each pin to be measured can receive an activation sequence
Numerical value；When needing to export the numerical value of each pin to be measured of sampling from depositor, then need by output pin come complete
Into test.The output pin is to have passed through the pin that output is tested, output function is good.In this manner it is ensured that from depositor
The numerical value of output will not be changed or accurately cannot be exported because the output function of pin is damaged.Such as a certain chip is present
100 pins, wherein 50 pins are to be measured, 50 pins in addition are normal through test output function, can draw to be measured
Foot is corresponded with the normal pin of output function, number of a certain pin through samples storage in the corresponding depositor of the pin
Value, is exported by the corresponding output pin of the pin.There are 101 pins, wherein 51 pins in a certain chip for another example
Input function it is to be measured, 50 pins are normal through test output functions, can be only done 50 pins in each clock cycle
Test, then can be divided to two clock cycle to complete the test of above-mentioned 51 pin input functions, first clock cycle with it is upper
One way of example is the same, and here is omitted；Second clock cycle, then select from the normal pin of 50 output functions
Select one it is corresponding with that pin to be measured for also not carrying out input function test.Also do not carry out input function test that
The numerical value stored in the corresponding depositor of individual pin to be measured, is exported by the selected normal pin of output function.
Then enter step S306 verification unit and judge whether the numerical value of output unit output is identical with output preset value, if
It is to pass through into the verification of step S307, does not otherwise pass through into the verification of step S308.In the present embodiment, the verification is single
Unit and excitation formation sequence are chip testing board, and chip testing board is a kind of chip testing devices of specialty, be can be used for
Produce the response sequence that test and excitation and observation check chip output.In further embodiments, the verification unit is additionally operable to
When the numerical value for judging output unit output is differed with output preset value, the numerical value for identifying output unit output is pre- with output
If the value digit that different numerical value are located between the two.
Such as pin number to be measured is 3, and output preset value is " 101 ", and activation sequence is also " 101 ", and exports single
The numerical value of unit's output is " 111 ", as second input and the output of activation sequence are mismatched, then can identify second presence
Problem.Again as the second bit value is to obtain output, and the pin to be measured corresponding to depositor b from depositor b for drawing
Foot b, then illustrate that pin b has that technical staff can do to pin b and further detect, take measures on customs clearance and located
Reason.
In certain embodiments, the quantity of the chip is for multiple, and the model of chip is identical, and methods described includes：Swash
Encourage signal generating unit and generate activation sequence, and the to be measured of different chips that the activation sequence of generation is transmitted to same model is drawn
Foot.Tester table can be to the chip of same model simultaneously output drive sequence, to accelerate testing efficiency.For example now with A,
Tri- chip block of B, C is to be detected, and the model of tri- chip block of A, B, C is identical, so that tester table can be encouraged by identical
Sequence pair this three chip block can be tested simultaneously.Assume that the corresponding pin number to be measured of chip A, B, C is 50, then survey
Commissioning stage will generate the activation sequence of 50, and the activation sequence for being generated is respectively sent to chip A, chip B and chip C.
Each chip it is each treat pin correspondence receive activation sequence in one digit number value, specific to every chip piece testing process such as
Described in aforementioned manner, here is omitted.
Said method current chip can be switched according to control signal residing for pattern, and input stimulus sequence is to chip
Pin to be measured, then the numerical value that pin to be measured is received is stored in memory element by sampling unit, then by be measured
The value of the corresponding output pin of pin (output function is good, another pin corresponding with pin to be measured) output memory element,
And verification unit by export value with default output valve image ratio compared with so as to the input function of automatic Verification chip pin to be measured
It is whether normal so that test can be carried out under the nude film stage in chip, equivalent to the mode of system test, greatly reduced
Testing cost.Additionally, the activation sequence of input completely can self-defined confirmation according to the actual requirements, with very high motility and
Failure checking cover ratio.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation are made a distinction with another entity or operation, and are not necessarily required or implied these entities or deposit between operating
In any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to
Nonexcludability is included, so that a series of process, method, article or terminal unit including key elements not only includes those
Key element, but also including other key elements being not expressly set out, or also include for this process, method, article or end
The intrinsic key element of end equipment.In the absence of more restrictions, limited by sentence " including ... " or " including ... "
Key element, it is not excluded that also there is other key element in the process including the key element, method, article or terminal unit.This
Outward, herein, " more than ", " less than ", " more than " etc. are interpreted as not including this number；" more than ", " below ", " within " etc. understand
It is to include this number.
Those skilled in the art are it should be appreciated that the various embodiments described above can be provided as method, device or computer program product
Product.These embodiments can adopt complete hardware embodiment, complete software embodiment or with reference to the embodiment in terms of software and hardware
Form.All or part of step in the method that the various embodiments described above are related to can be instructed by program correlation hardware come
Complete, described program can be stored in the storage medium that computer equipment can read, for performing the various embodiments described above side
All or part of step described in method.The computer equipment, including but not limited to：Personal computer, server, general-purpose computations
Machine, special-purpose computer, the network equipment, embedded device, programmable device, intelligent mobile terminal, intelligent home device, Wearable
Smart machine, vehicle intelligent equipment etc.；Described storage medium, including but not limited to：RAM, ROM, magnetic disc, tape, CD, sudden strain of a muscle
Deposit, USB flash disk, portable hard drive, storage card, memory stick, webserver storage, network cloud storage etc..
The various embodiments described above are with reference to the method according to embodiment, equipment (system), and computer program
Flow chart and/or block diagram are describing.It should be understood that can by computer program instructions flowchart and/or block diagram in it is every
The combination of one flow process and/or square frame and flow chart and/or the flow process in block diagram and/or square frame.These computers can be provided
Programmed instruction to computer equipment processor producing a machine so that by the finger of the computing device of computer equipment
Order is produced for realizing what is specified in one flow process of flow chart or one square frame of multiple flow processs and/or block diagram or multiple square frames
The device of function.
These computer program instructions may be alternatively stored in the computer that computer equipment can be guided to work in a specific way and set
In standby readable memory so that the instruction being stored in the computer equipment readable memory produces the manufacture for including command device
Product, the command device are realized in one flow process of flow chart or one square frame of multiple flow processs and/or block diagram or multiple square frame middle fingers
Fixed function.
These computer program instructions can be also loaded on computer equipment so that performed on a computing device a series of
Operating procedure to produce computer implemented process, so as to the instruction for performing on a computing device provide for realize in flow process
The step of function of specifying in one flow process of figure or one square frame of multiple flow processs and/or block diagram or multiple square frames.
Although being described to the various embodiments described above, those skilled in the art once know basic wound
The property made concept, then can make other change and modification to these embodiments, so embodiments of the invention are the foregoing is only,
Not thereby the scope of patent protection of the present invention, the equivalent structure made by every utilization description of the invention and accompanying drawing content are limited
Or equivalent flow conversion, or other related technical fields are directly or indirectly used in, the patent of the present invention is included in the same manner
Within protection domain.
Claims (10)
1. a kind of chip input pin test device, the chip include at least one pin to be measured, it is characterised in that the dress
Put single including output valve setting unit, mode setting unit, pin setting unit, excitation signal generating unit, sampling unit, storage
Unit, output unit and verification unit；
The output valve setting unit is used for arranging output preset value；
The mode setting unit is used for receiving test signal, allows chip in test pattern, and the pin setting unit is used for
The pin to be measured of chip is set to into input state；
The excitation signal generating unit is used for generating activation sequence, and activation sequence is transmitted to the pin to be measured of chip；Generate
Activation sequence is identical with output preset value, and the activation sequence includes at least one digit number value, and each pin correspondence to be measured is received and swashed
Encourage the one digit number value in sequence；
The mode setting unit is additionally operable to receive sampled signal, allows chip in sampling configuration, and it is right that the sampling unit is used for
The numerical value that each pin correspondence to be measured is received is sampled, and sampled result is stored in memory element；
The mode setting unit is used for receiving sampled output signal, allows chip in sampling output mode, the output unit
For the sampled result stored in memory element is transmitted to verification unit by output pin, each pin correspondence one to be measured is defeated
Go out pin, output pin is used for exporting one digit number value；
The verification unit is used for judging whether the numerical value of output unit output to be identical with output preset value, if then verifying logical
Cross, otherwise verify and do not pass through.
2. chip input pin test device as claimed in claim 1, it is characterised in that the memory element is depositor
Group, the depositor group include the depositor of multiple preset order arrangements, and each depositor is used for storage from a pin to be measured
The numerical value of up-sampling.
3. chip input pin test device as claimed in claim 1 or 2, it is characterised in that the activation sequence is by counting
The sequence that value " 0 " or " 1 " constitute.
4. chip input pin test device as claimed in claim 1, it is characterised in that the verification unit is additionally operable to sentencing
Determine output unit output numerical value with output preset value differ when, identify output unit output numerical value with output preset value
The digit that different numerical value are located between the two.
5. chip input pin test device as claimed in claim 1, it is characterised in that the quantity of the chip be it is multiple,
And the model of chip is identical, the excitation signal generating unit is used for generating activation sequence, and the activation sequence parallel transmission that will be generated
To the pin to be measured of the different chips of same model.
6. a kind of chip input pin method of testing, methods described are applied to chip input pin test device, the chip bag
Include at least one pin to be measured, it is characterised in that described device includes that output valve setting unit, mode setting unit, pin set
Put unit, excitation signal generating unit, sampling unit, memory element, output unit and verification unit；Methods described includes following step
Suddenly：
Output valve setting unit arranges output preset value；
Mode setting unit receives test signal, allows chip in test pattern, and pin setting unit is by the pin to be measured of chip
It is set to input state；
Excitation signal generating unit generates activation sequence, and activation sequence is transmitted to the pin to be measured of chip；The activation sequence of generation
Identical with output preset value, activation sequence includes at least one digit number value, and each pin correspondence to be measured receives in activation sequence one
Bit value；
Mode setting unit receives sampled signal, allows chip in sampling configuration, and sampling unit is connect to each pin correspondence to be measured
The numerical value of receipts is sampled, and sampled result is stored in memory element；
Mode setting unit receives sampled output signal, allows chip in sampling output mode, and output unit is by memory element
The sampled result of storage is transmitted to verification unit by output pin, one output pin of each pin correspondence to be measured, output pin
For exporting one digit number value；
Verification unit judges whether the numerical value of output unit output is identical with output preset value, if then verify passing through, otherwise school
Test and do not pass through.
7. chip input pin method of testing as claimed in claim 6, it is characterised in that the memory element is depositor
Group, the depositor group include the depositor of multiple preset order arrangements, and each depositor is used for storage from a pin to be measured
The numerical value of up-sampling.
8. chip input pin method of testing as claimed in claims 6 or 7, it is characterised in that the activation sequence is by counting
The sequence that value " 0 " or " 1 " constitute.
9. chip input pin method of testing as claimed in claim 6, it is characterised in that methods described also includes：
Verification unit identifies output unit output when the numerical value for judging output unit output is differed with output preset value
Numerical value and the output preset value digit that different numerical value are located between the two.
10. chip input pin method of testing as claimed in claim 6, it is characterised in that the quantity of the chip be it is multiple,
And the model of chip is identical, methods described includes：
Excitation signal generating unit generation activation sequence, and the activation sequence of generation is transmitted to the different chips of same model
Pin to be measured.
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| CN107957541A (en) * | 2017-11-21 | 2018-04-24 | 华北电力大学 | A kind of power semiconductor modular internal parallel cDNA microarray method and system |
| CN108226749A (en) * | 2017-12-11 | 2018-06-29 | 天津津航计算技术研究所 | A kind of SIP failure of chip detecting system and detection method |
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| CN112380119A (en) * | 2020-11-12 | 2021-02-19 | 上海东软载波微电子有限公司 | Chip, programming debugger, system and method for locking programming debugging entry |
| CN113255271A (en) * | 2021-05-17 | 2021-08-13 | 厦门紫光展锐科技有限公司 | Automatic verification system and method for IO pin of chip |
| CN113255271B (en) * | 2021-05-17 | 2022-09-09 | 厦门紫光展锐科技有限公司 | Automatic verification system and method for IO pin of chip |
| CN113407408A (en) * | 2021-06-11 | 2021-09-17 | 海光信息技术股份有限公司 | Data transmission rule verification method, device, equipment and storage medium |
| CN113407408B (en) * | 2021-06-11 | 2024-01-26 | 海光信息技术股份有限公司 | Data transmission rule verification method, device, equipment and storage medium |
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| CN117233516B (en) * | 2023-11-13 | 2024-03-01 | 朗思传感科技(深圳)有限公司 | Pin detection method and pin detection device |
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Address after: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |