CN106527100A - Adjusting time-counting circuit resistant to electric leakage interference - Google Patents
Adjusting time-counting circuit resistant to electric leakage interference Download PDFInfo
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- CN106527100A CN106527100A CN201610948469.7A CN201610948469A CN106527100A CN 106527100 A CN106527100 A CN 106527100A CN 201610948469 A CN201610948469 A CN 201610948469A CN 106527100 A CN106527100 A CN 106527100A
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- external capacitor
- logic circuit
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/02—Apparatus for measuring unknown time intervals by electric means using oscillators with passive electric resonator, e.g. lumped LC
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Abstract
The invention provides an adjustable time-counting circuit resistant to electric leakage interference. The adjustable time-counting circuit resistant to the electric leakage interference comprises a comparator, a logic circuit and a controlled counter, wherein the comparator compares the voltage of an externally connected capacitor with a preset voltage threshold value, and outputs a comparison result; the logic circuit comprises a port used to receive clock signals, can receive enable signals, output signals of the comparator and the clock signals and can output control signals; the logic circuit counts the clock signals during the period since validity of the enable signals and the externally connected capacitor starts charging till the voltage of the externally connected capacitor reaches the preset voltage threshold value, and a first counting value can be obtained; the logic circuit adjusts the first counting value and outputs the control signals; the controller counter receives to-be-delayed input signals and the control signals and conducts counting according to the control signals; and the controlled controller will output the input signals when the counting is continued to a second counting value, wherein the second counting value is determined by the control signals output by the logic circuit.
Description
Technical field
The present invention relates to IC design fields, more particularly to the IC circuits for needing clocking capability.
Background technology
Some chips need the clocking capability of adjustable time for application demand.If will be after chip package to meter
When be adjusted, can typically utilize chip PIN or change the connect external devices of PIN and be selected, or utilize chip
Communicate to be adjusted.Chip internal timing is adjusted for by changing external devices, it is the more commonly used in prior art
It is to utilize to external capacitor charge and discharge (I*t=C*V) to realize.But this mode can be present on external capacitor when timing is longer
The little problem of pull-down current.For example in lithium electric protection product, the realization of overcurrent protection function needs the timing up to 1s, if sharp
Realized with to external capacitor charge and discharge, in the case where pull-up upset point voltage is 5V, it is upper that the external capacitor of 0.1uF needs
Sourcing current is only 0.5uA (0.5uA=0.1uF*5V/1s).Such pull-up current very little, if in the port of external capacitor
There is electric leakage or external capacitor has electric leakage, then timing is just affected and is likely to come into force.
Figure 1A is the timing oscillogram of the port (COFF) without electric leakage of external capacitor in prior art.
Figure 1B is the timing oscillogram that there is electric leakage the port (COFF) of external capacitor in prior art.
Wherein, VTR is the voltage of COFF when timing stops.When there is electric leakage in port (COFF) place of external capacitor, meter
When be likely to just come into force forever, as shown in Figure 1B.
Therefore, for using electric capacity charge realize adjust clocking capability mode, how to increase charging current to realize
The scheme of tracking-resistant interference is that current industry is needed badly and sought.
The content of the invention
In order to solve this problem, the invention discloses a kind of adjustable timing circuit of tracking-resistant interference.The circuit can be with
It is widely used in the various chips for needing internal clocking.
In one embodiment, the invention provides a kind of adjustable timing circuit of tracking-resistant interference, it is characterised in that institute
The adjustable timing circuit for stating tracking-resistant interference includes：
Comparator, compares for the voltage of external capacitor is compared and be exported with one default voltage threshold (VTR)
As a result；
Logic circuit, port of the logic circuit with reception clock signal, the logic circuit reception enable signal,
The output signal of the comparator and the clock signal (CLK), and output control signal, wherein, the logic circuit from
Enable signal effectively and external capacitor starts to charge up beginning, until the voltage of external capacitor reaches the default voltage threshold
(VTR) clock signal (CLK) is counted in this period, and obtains the first count value；The logic circuit pair
First count value is adjusted, and exports the control signal；
Controlled enumerator, input signal (IN) and the logic circuit that the controlled enumerator to be postponed for reception
The control signal of output, and counted according to the control signal, when the second count value is counted up to, controlled enumerator
The input signal is exported, wherein, second count value is determined by the control signal that the logic circuit is exported.
In one embodiment, the adjustable timing circuit of the tracking-resistant interference also includes：
For connecting the port (COFF) of external capacitor.
In one embodiment, voltage threshold (VTR) is determined by actual demand and circuit realiration.
In one embodiment, the control signal is the function of first count value, for the controlled counting
Device is adjusted.
In one embodiment, the adjustable counting circuit of the tracking-resistant interference also includes：
Pull-up circuit, at least including current source or resistance, the pull-up circuit and it is described connection external capacitor port
(COFF) it is connected；
Pull-down circuit, at least including current source or resistance, the pull-down circuit and it is described connection external capacitor port
(COFF) it is connected.
In one embodiment, when the enable signal is effective, the pull-down circuit quits work, the pull-up circuit
Start working and the current potential to the external capacitor is pulled up.
Beneficial effects of the present invention are as follows：
For the circuit in the present invention, as the cycle that can realize CLK is sufficiently small, therefore pull-up circuit just can be with strong
Pull-up current, realizes timing, needs to reduce external electrical when timing is longer so as to solve using to outside capacitor charge and discharge
The problem of pull-down current in appearance.
Still by taking the overcurrent protection function of lithium electric protection product as an example, functional realiey needs the timing up to 1s, using external
Realizing, in the case where pull-up upset point is for 5V, the pull-up current that the external capacitive of 0.1uF needs is only portion's capacitor charge and discharge
0.5uA.As shown in figure 4, under external capacitor 0.1uF, VTR=5V, traditional timing circuit pull-up current is 0.5uA, resistive when having
During electric leakage, the voltage on COFF is from being changed into can only increase to certain between 0V～VTR without the VTR that linearly increases to during resistive electric leakage
Individual level, so that cause loss of timing；And for the timing circuit in the present invention, timing includes pulling up external capacitor and controlled meter
Number device timing this two parts, it is 5ms (=1s/200) to distribute the time that external capacitor is pulled to VTR, during controlled counter counts
995ms (=1s*199/200) is adjusted to by logic circuit, such pull-up current can just be increased to 100uA, even if now there is resistance
Property electric leakage, the also very little of the impact to timing.If clk cycle is sufficiently small, then the external capacitor pull-up time just can with shorter, on
Sourcing current just can be bigger, and the impact leaked electricity to timing is just less.Due to external capacitor pull up the time and during controlled counter counts all
It is related to external capacitor size, changes the size that external capacitor size can change timing.
Description of the drawings
The above content of the invention and detailed description below of the present invention can be obtained when being read in conjunction with the accompanying more preferably
Understanding.It should be noted that example of the accompanying drawing only as claimed invention.In the accompanying drawings, identical reference
Represent same or similar element.
Port (COFF) timing oscillograms without electric leakage of the Figure 1A for external capacitor；
Figure 1B is the timing oscillogram that there is electric leakage the port (COFF) of external capacitor；
Fig. 2 is a kind of adjustable timing circuit of the tracking-resistant interference according to one embodiment of the invention；
Fig. 3 is the circuit working timing figure according to one embodiment of the invention；
Fig. 4 is the port (COFF) of the external capacitor according to one embodiment of the invention in different pull-up currents, different electric leakages
Timing oscillogram under state.
Description of reference numerals
201 pull-up circuits
202 pull-down circuits
203 comparators
204 logic circuits
205 enumerators
206 chips are input into PIN
EN enables signal
VTR voltage ratios are compared with threshold value
CMP_O comparators are exported
CLK clock signals
The output of LOGIC_O logic circuits, control signal
IN needs the signal for postponing
Signal after OUT delays
The port of COFF external capacitors
Specific embodiment
Hereinafter detailed detailed features and advantage of the narration present invention in a specific embodiment, its content be enough to make any
Skilled in the art realises that the technology contents of the present invention implement according to this, and the description according to disclosed by this specification, power
Profit is required and accompanying drawing, skilled person readily understands that the related purpose of the present invention and advantage.
Fig. 2 is a kind of adjustable timing circuit of the tracking-resistant interference according to one embodiment of the invention.This is adjustable timing circuit
Include, but not limited to pull-up circuit (PULL UP) 201, pull-down circuit (PULL DOWN) 202, comparator (CMP) 203, logic
Circuit (LOGIC) 204, controlled enumerator (COUNTER) 205, chip inputs PIN (COFF) 206.
Pull-up circuit 201, includes, but are not limited to current source, resistance etc..
Pull-down circuit 202, includes, but are not limited to current source, resistance etc..
Chip input PIN (COFF) 206 is used for connecing off-chip capacitive appearance.
Comparator (CMP) 203 is for by the voltage and a default electricity in PIN (COFF, for connecting external capacitor)
Pressure threshold value VTR is compared, and voltage threshold VTR can be determined by actual demand and circuit realiration.
Logic circuit (LOGIC) 204 is for defeated to comparator from 0 change 1 (i.e., 1 represents effective) to enabling signal (EN)
Go out (CMP_O) and the first count value n is counted and obtained from the clock signal clk between 0 change 1, and first count value n is entered
Row adjustment (carrying out functional transformation to first count value n), and output control signal LOGIC_O, it is right that the control signal is used for
Controlled enumerator (COUNTER) 205 is adjusted, and wherein control signal is the function of the first count value n.
Controlled enumerator (COUNTER) 205 is believed for the control for receiving the signal IN and logic circuit output to be postponed
Number, and counted according to the control signal (count value of controlled enumerator is referred to as the second count value), second count value with
The control signal of logic circuit output is related, when second count value is counted up to, controlled enumerator output input signal IN
Rising edge, equivalent to being postponed to input signal IN, the time delay is with the first count value n into functional dependence for this.
The traditional utilization of contrast realizes timing to external capacitor charge and discharge, present invention adds patrolling with clock CLK ports
Collect circuit (LOGIC) 204 and controlled enumerator (COUNTER) 205.
When signal EN is enabled when 0 is changed into 1, pull-down circuit (PULL DOWN) 202 quits work, by pull-up circuit (PULL
UP) external capacitor of 201 pairs of chips is pulled up, and when the voltage of external capacitor port COFF206 is more than default voltage threshold
During value VTR, there is upset and be changed into 1 from 0 in the output CMP_O of comparator (CMP) 203, logic circuit (LOGIC) 204 is just to EN (0
→ 1) and in CMP_O (0 → 1) this period (namely the voltage of external capacitor charges from 0 and is raised in the time period of VTR)
CLK rising edges (or trailing edge) are counted, and obtain count value n.Meanwhile, 204 pairs of count values n of logic circuit enter line translation,
One control signal related to n of output, for example, the control signal is the function of n.The control signal is to the controlled of chip internal
Enumerator (COUNTER) is controlled regulation so that arbitrary input IN will be through prolonging with the functional dependence of count value n
OUT could be exported late, it is achieved thereby that timing is adjustable.The clock signal clk that the present invention is provided is that, in chip, its cycle can
To be designed to very little, thus no matter the voltage at COFF ends by 0 to default threshold V T R time, (i.e. external capacitor fills
The electric time) how short have, CLK always can carry out sample count to the time period.And very short capacitor charging time, it is meant that on
Puller circuit (PULL UP) 201 can use strong pull-up electric current, realize meter so as to solve tradition using to external capacitor charge and discharge
When, when timing is longer the little problem of pull-down current on external capacitor.Now, if there is leakage current, due to pull-up current
Very big, electric leakage is nearly free from interference to the pull-up current.
Circuit working timing figure is as shown in Figure 3.When signal EN is enabled when 0 becomes 1, chip external capacitor is by PULL UP
Draw, the voltage on COFF is more than VTR, and the output CMP_O of comparator CMP also becomes 1 by 0, logic circuit (LOGIC) 204 pairs
Clock signal clk rising edge in EN (0 → 1) and CMP_O (0 → 1) this period is counted.In one embodiment, patrol
Collect circuit to count the trailing edge of clock signal clk.The parameter related to count value (is entered after the completion of counting
The second count value after row adjustment) it is sent to COUNTER to adjust timing；If the count value in Fig. 3 is n, logic circuit is adjusted
The timing of controlled counter circuit is n clk cycle (Fig. 3 is a special case, can be the arbitrary function related to n), then
Input signal IN (can arbitrarily need to postpone the signal of output) is sent to output OUT through the delay of n clk cycle.
In one embodiment, the invention provides a kind of tracking-resistant interference adjustable timing circuit, the tracking-resistant do
The adjustable timing circuit disturbed includes：
Comparator, compares for the voltage of external capacitor is compared and be exported with one default voltage threshold (VTR)
As a result；
Logic circuit, port of the logic circuit with reception clock signal, the logic circuit reception enable signal,
The output signal of the comparator and the clock signal (CLK), and output control signal, wherein, the logic circuit from
Enable signal effectively and external capacitor starts to charge up beginning, until the voltage of external capacitor reaches the default voltage threshold
(VTR) clock signal (CLK) is counted in this period, and obtains the first count value；The logic circuit pair
First count value is adjusted, and exports the control signal；
Controlled enumerator, input signal (IN) and the logic circuit that the controlled enumerator to be postponed for reception
The control signal of output, and counted according to the control signal, when the second count value is counted up to, controlled enumerator
The input signal is exported, wherein, second count value is determined by the control signal that the logic circuit is exported.
In one embodiment, the adjustable timing circuit of the tracking-resistant interference also includes：
For connecting the port (COFF) of external capacitor.
In one embodiment, voltage threshold (VTR) is determined by actual demand and circuit realiration.
In one embodiment, the control signal is the function of first count value, for the controlled counting
Device is adjusted.
In one embodiment, the adjustable counting circuit of the tracking-resistant interference also includes：
Pull-up circuit, at least including current source or resistance, the pull-up circuit and it is described connection external capacitor port
(COFF) it is connected；
Pull-down circuit, at least including current source or resistance, the pull-down circuit and it is described connection external capacitor port
(COFF) it is connected.
In one embodiment, when the enable signal is effective, the pull-down circuit quits work, the pull-up circuit
Start working and the current potential to the external capacitor is pulled up.
With reference to foregoing description, for the circuit in the present invention, as long as the cycle of clock signal clk is little, it is possible to allow pull-up
Circuit strong pull-up electric current, realizes timing, needs to subtract when timing is longer so as to solve using to external capacitor charge and discharge
The problem of pull-down current on little external capacitor.
It should be appreciated by those skilled in the art that technical scheme can apply to need any of clocking capability
IC.Understand for convenience, as a example by this sentences the overcurrent protection function of lithium electric protection product, functional realiey needs the meter up to 1s
When, realize using to external capacitor charge and discharge, in the case where pull-up upset point (i.e. VTR) is 5V, the external capacitor of 0.1uF
The pull-up current of needs is only 0.5uA.As shown in Figure 4, under external capacitor 0.1uF, VTR=5V, traditional timing circuit pull-up
Electric current is 0.5uA, when there is resistive electric leakage, the voltage on COFF from without linearly increasing to during resistive electric leakage VTR is changed into can only
Certain level between 0V～VTR is increased to, so as to cause loss of timing；And for the timing circuit in the present invention, timing bag
Pull-up external capacitor and controlled enumerator (COUNTER) timing this two parts are included, distributes the time that external capacitor is pulled to VTR
For 5ms (=1s/200), controlled enumerator (COUNTER) timing is adjusted to 995ms (=1s*199/ by logic circuit (LOGIC)
200), such pull-up current can just be increased to 100uA, even if now there is resistive electric leakage, the also very little of the impact to timing.If
Clk cycle is sufficiently small, then the external capacitor pull-up time just can be with shorter, and pull-up current just can be bigger, the shadow leaked electricity to timing
Sound is just less.All it is related to external capacitor size as external capacitor pulls up time and controlled enumerator (COUNTER) timing
, change the size that external capacitor size can change timing.
Here the term and form of presentation for adopting is only intended to description, and the present invention should not be limited to these terms and table
State.It is not meant to exclude any signal using these terms and statement and describes the equivalent features of (or which part), should recognizes
Knowing various modifications that may be present also should be comprising within the scope of the claims.Other modifications, variations and alternatives also likely to be present.
Accordingly, claim should be regarded as covering all these equivalents.
Equally, it should be pointed out that although the present invention is described with reference to current specific embodiment, this technology neck
Those of ordinary skill in domain it should be appreciated that the embodiment of the above is intended merely to the explanation present invention, without departing from the present invention
Various equivalent change or replacement can be also made in the case of spirit, therefore, as long as right in the spirit of the present invention
The change of above-described embodiment, modification will all fall in the range of following claims.
Claims (6)
1. a kind of adjustable timing circuit that tracking-resistant is disturbed, it is characterised in that the adjustable counting circuit bag of the tracking-resistant interference
Include：
Comparator, for the voltage of external capacitor and one default voltage threshold (VTR) to be compared and export comparative result；
Logic circuit, the logic circuit have a port for receiving clock signal, and the logic circuit is received and enables signal, described
The output signal of comparator and the clock signal (CLK), and output control signal, wherein, the logic circuit is from enable
Signal is effectively and external capacitor starts to charge up beginning, until the voltage of external capacitor reaches this section of the default voltage threshold
The clock signal (CLK) is counted in time, and obtain the first count value；The logic circuit is counted to described first
Value is adjusted, and exports the control signal；
Controlled enumerator, input signal (IN) and logic circuit output that the controlled enumerator to be postponed for reception
The control signal, and counted according to the control signal, when the second count value is counted up to, controlled enumerator is just defeated
Go out the input signal, wherein, second count value is determined by the control signal that the logic circuit is exported.
2. adjustable timing circuit as claimed in claim 1, it is characterised in that the adjustable timing circuit of the tracking-resistant interference is also
Including：
For connecting the port (COFF) of external capacitor.
3. adjustable timing circuit as claimed in claim 1, it is characterised in that the voltage threshold is by actual demand and circuit reality
Now determine.
4. adjustable timing circuit as claimed in claim 1, it is characterised in that the control signal is first count value
Function, for being adjusted to the controlled enumerator.
5. adjustable timing circuit as claimed in claim 1, it is characterised in that the adjustable timing circuit of the tracking-resistant interference is also
Including：
Pull-up circuit, at least including current source or resistance, the pull-up circuit and it is described connection external capacitor port
(COFF) it is connected；
Pull-down circuit, at least including current source or resistance, the pull-down circuit and it is described connection external capacitor port
(COFF) it is connected.
6. adjustable timing circuit as claimed in claim 1, it is characterised in that when the enable signal is effective, described drop-down
Circuit quits work, and the pull-up circuit is started working and the external capacitor is pulled up.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610948469.7A CN106527100B (en) | 2016-10-26 | 2016-10-26 | A kind of adjustable timing circuit of tracking-resistant interference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610948469.7A CN106527100B (en) | 2016-10-26 | 2016-10-26 | A kind of adjustable timing circuit of tracking-resistant interference |
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| Publication Number | Publication Date |
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| CN106527100A true CN106527100A (en) | 2017-03-22 |
| CN106527100B CN106527100B (en) | 2019-01-15 |
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| CN201610948469.7A Active CN106527100B (en) | 2016-10-26 | 2016-10-26 | A kind of adjustable timing circuit of tracking-resistant interference |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110035581A (en) * | 2019-04-22 | 2019-07-19 | 上海芯荃微电子科技有限公司 | Slow timing module |
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| CN104660022A (en) * | 2015-02-02 | 2015-05-27 | 昂宝电子（上海）有限公司 | System and method for providing overcurrent protection for power converter |
| CN104883159A (en) * | 2015-04-20 | 2015-09-02 | 成都岷创科技有限公司 | Clock phase control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87100999A (en) * | 1987-03-03 | 1988-02-10 | 周洪璋 | Long-time controller with pump-type staircase wave generator |
| EP1041464A2 (en) * | 1999-03-03 | 2000-10-04 | Seiko Epson Corporation | Electronic device and method of controlling the same |
| US6181649B1 (en) * | 1999-07-14 | 2001-01-30 | Guide Technology, Inc. | Time interval analyzer having current boost |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110035581A (en) * | 2019-04-22 | 2019-07-19 | 上海芯荃微电子科技有限公司 | Slow timing module |
| CN110035581B (en) * | 2019-04-22 | 2023-10-13 | 上海芯荃微电子科技有限公司 | Slow timing module |
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| Publication number | Publication date |
|---|---|
| CN106527100B (en) | 2019-01-15 |
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