CN203554401U - Reset circuit with high responding speed and low temperature coefficients - Google Patents
Reset circuit with high responding speed and low temperature coefficients Download PDFInfo
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- CN203554401U CN203554401U CN201320631535.XU CN201320631535U CN203554401U CN 203554401 U CN203554401 U CN 203554401U CN 201320631535 U CN201320631535 U CN 201320631535U CN 203554401 U CN203554401 U CN 203554401U
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Abstract
This utility model discloses a reset circuit with high responding speed and low temperature coefficients, relating to the integrated circuit technology field. The reset circuit with high responding speed and low temperature coefficients comprises a voltage sampling circuit, a voltage detection circuit and an output circuit which are connected successively. The voltage sampling circuit comprises a first resistor, a first NMOS transistor and a drain electrode of a second NMOS transistor. The voltage detection circuit comprises a first CMOS inverter and a first capacitor. The first CMOS inverter comprises a first PMOS transistor and a third NMOS transistor. The output circuit comprises a first Schmitt trigger, a second CMOS inverter and a third CMOS inverter which are connected successively. The output of the output circuit is connected to the input terminal of a time delay circuit which adjusts the length of the outputted reset signal and performs shaping on the reset signal according to the reset requirements of the circuit system. The reset circuit with high responding speed and low temperature coefficients has high responding speed and the temperature coefficients which are close to zero, which can fully guarantee reliability of the preset circuit.
Description
Technical field
The utility model relates to technical field of integrated circuits, particularly can be integrated into the high response speed of chip internal, the reset circuit of low-temperature coefficient.
Background technology
Along with the high speed development of large scale integrated circuit, reset circuit can be described as the circuit module having in each IC chip circuit, be used for digital system and do asynchronous reset signal, detect the whether normal upper and lower electricity of supply voltage, guarantee the correctness of inside circuit Digital Logic.
Resetting voltage requires on power supply is various, in lower electric situation, can provide correct reset signal, so the voltage detecting circuit that this circuit comprises just can not adopt conventional supply voltage being sampled by sample circuit, the method of utilizing analog comparator that the reference voltage of sampled voltage and BANDGAP output is compared realizes, this is because BANDGAP circuit itself exists starting resistor, lower than starting resistor in the situation that, GANDGAP can not provide correct reference voltage, can cause comparator Output rusults incorrect in supply voltage power up, system reset can accurately be provided.
Referring to Fig. 1, in prior art, in integrated circuit, conventional reset circuit comprises bleeder circuit and voltage detecting circuit.Bleeder circuit is comprised of with the nmos pass transistor that drain electrode is connected with grid current-limiting resistance (or active pull-up, current source), and because reset resistor will meet the requirement of low-power consumption, current-limiting resistance R1 must be very large, so flow through the transistorized electric current of M1
very little, and pass through saturation region transistor current formula:
Can obtain
, due to the cut-in voltage of nmos pass transistor
there is negative temperature coefficient, so the output voltage of supply voltage sample circuit
also there is negative temperature coefficient; Voltage detecting circuit is comprised of CMOS inverter, supposes that its turn threshold voltage is
, when VDD is more than or equal to voltage
time, CMOS inverter is output as high level, otherwise is low level; Its input voltage has negative temperature coefficient
, when VDD reaches turn threshold voltage (the reset threshold voltage of CMOS inverter
) time,
, flow through the transistorized electric current of M0 and M2 and equate, by:
As can be seen from Figure 1,
transistor and
the relation of transistor proportional (K) mirror image, can be listed as:
Further release and flow through
transistorized electric current
:
Obviously,
,
all relevant with temperature, and
present larger negative temperature coefficient (with
become square relation), finally cause the output reset signal of voltage detecting circuit to there is very large temperature coefficient, can not meet the requirement of Circuits System to reset signal now.
The lower electroresponse speed of above-mentioned traditional circuit is very low, and when supply voltage is normal, PORN is high level, and in Fig. 1, B point is also high level, and M2 transistor is in saturation region and M0, M2 transistor path Continuous-flow mistake
.When quick power-down conditions appears in power supply, vdd voltage reduces, and A point node potential, due to the impact of the transistorized parasitic capacitance of M0, there will be large voltage fluctuation, and M0, M2 are transistorized
also there is large voltage fluctuation thereupon.M0 is transistorized
reduce and finally cause M0 transistor cut-off, M2 transistor due to
unstable decline causes B node can not become fast low level.
In sum, reset circuit temperature of the prior art is very large on its impact, and lower electroresponse speed is slow, and these all can not finely meet the requirement of the reset signal of present integrated circuit to high response speed, low-temperature coefficient.
Summary of the invention
For above-mentioned the deficiencies in the prior art, the purpose of this utility model is to provide the reset circuit of a kind of high response speed, low-temperature coefficient.It is a kind of reset circuit that possesses high response speed, approaches zero-temperature coefficient, can fully guarantee the reliability of reset circuit work.
In order to reach foregoing invention object, the technical solution of the utility model realizes as follows:
The reset circuit of high response speed, low-temperature coefficient.Its design feature is that it comprises the voltage sampling circuit, voltage detecting circuit and the output circuit that are connected successively.Described voltage sampling circuit comprises the first resistance, one termination power vd D of the first resistance, the drain and gate of another termination the first nmos pass transistor of the first resistance, the source electrode of the first nmos pass transistor connects the drain electrode of the second nmos pass transistor, the grid of the second nmos pass transistor connects the drain electrode of the first nmos pass transistor, the grid of the grid of the first nmos pass transistor and the second nmos pass transistor is connected to the drain electrode of the first nmos pass transistor, the source ground VSS of the second nmos pass transistor.Described voltage detecting circuit comprises a CMOS inverter and the first electric capacity, and the input of a CMOS inverter is received the drain electrode of source electrode and second nmos pass transistor of the first nmos pass transistor in voltage sampling circuit.The one CMOS inverter comprises a PMOS transistor and the 3rd nmos pass transistor.The input of one termination the one CMOS inverter of the first electric capacity, the other end ground connection VSS of the first electric capacity.Described output circuit comprises the first Schmidt trigger, the 2nd CMOS inverter and the 3rd CMOS inverter that are connected successively.The output of the input termination voltage detecting circuit of the first Schmidt trigger, an effective reset signal of output output of the 3rd CMOS inverter.The 2nd CMOS inverter comprises the 4th PMOS transistor and the 5th nmos pass transistor, and the 3rd CMOS inverter comprises the 7th PMOS transistor and the 6th nmos pass transistor.The output of output circuit is connected to the input of delay circuit, and delay circuit requires the length of regulation output reset signal time according to the reset of Circuits System and to reset signal shaping.
In above-mentioned reset circuit, described the first nmos pass transistor is primary nmos pass transistor, first nmos pass transistor adopt low turn-on voltage value at 0～0.3V, second nmos pass transistor adopt standard cut-in voltage value at 0.3V～0.7V.
In above-mentioned reset circuit, described the first resistance adopts current source, passive resistance or active device PMOS transistor.
In above-mentioned reset circuit, the first electric capacity in described voltage detecting circuit adopts primary electric capacity.
The utility model, owing to having adopted above-mentioned structure, compared with existing technical scheme, has following advantage:
1) the first nmos pass transistor in the utility model voltage sampling circuit, has low turn-on voltage, and its cut-in voltage value is at 0～0.3V.The second nmos pass transistor, has standard cut-in voltage, and its cut-in voltage value is at 0.3V～0.7V.The output voltage of voltage sampling circuit just becomes like this
,
with
temperature coefficient be all by cut-in voltage separately
the negative temperature coefficient that (having negative temperature coefficient) introduces, both subtract each other can offset mutual negative temperature coefficient.Due to the variation of voltage sampling circuit, the turn threshold of the inverter of the first nmos pass transistor in voltage detecting circuit and PMOS transistor composition can be adjusted temperature coefficient by the ratio of the breadth length ratio of change respective tubes, suitable the first nmos pass transistor and the transistorized device parameters of a PMOS of design, can obtain the resetting voltage threshold value close to zero-temperature coefficient like this
.
2) when supply voltage is normal, the reset signal PORN of output is high level, and the first nmos pass transistor in voltage detecting circuit is in saturation region.The 3rd nmos pass transistor in voltage detecting circuit and a PMOS transistor path Continuous-flow mistake, when quick power-down conditions appears in power supply, vdd voltage reduces, and owing to there being the first electric capacity effect, there is not large voltage fluctuation in A point node potential.The 3rd nmos pass transistor in voltage detecting circuit
stable, the PMOS in voltage detecting circuit is transistorized
reduce and finally cause a PMOS transistor cut-off, the 3rd nmos pass transistor is pulled down to fast B node and becomes low level.The discharging current of the 3rd nmos pass transistor in voltage detecting circuit is several uA, B node only has the little by little capacitive load of device parasitism, general tens fF of capacitance are to tens fF, so within reaching 100ns the discharge time of B, improved the speed of time reset circuit.
Below in conjunction with the drawings and specific embodiments, the utility model is described further.
Accompanying drawing explanation
Fig. 1 is reset circuit schematic diagram in prior art;
Fig. 2 is the reset circuit schematic diagram in the utility model embodiment;
Fig. 3 is the delay circuit schematic diagram in the utility model embodiment;
Fig. 4 be reset circuit in the utility model embodiment reset threshold voltage (
) variation schematic diagram.
Embodiment
Referring to Fig. 2, the utility model reset circuit comprises the voltage sampling circuit 101, voltage detecting circuit 102 and the output circuit 103 that are connected successively.Voltage sampling circuit 101 comprises a termination power vd D who adopts current source, passive resistance or transistorized the first resistance R 1, the first resistance R 1 of active device PMOS, the drain and gate of another termination first nmos pass transistor M1 of the first resistance R 1.The source electrode of the first nmos pass transistor M1 connects the drain electrode of the second nmos pass transistor M2.The grid of the second nmos pass transistor M2 connects the drain electrode of the first nmos pass transistor M1, the source ground VSS of the second nmos pass transistor M2.The grid of the grid of the first nmos pass transistor M1 and the second nmos pass transistor M2 is connected to the drain electrode of the first nmos pass transistor M1.The first nmos pass transistor M1 is primary nmos pass transistor, first nmos pass transistor M1 adopt low turn-on voltage value at 0～0.3V, second nmos pass transistor M2 adopt standard cut-in voltage value at 0.3V～0.7V.Voltage detecting circuit 102 comprises that the input of a CMOS inverter and the first capacitor C 1, the one CMOS inverter receives the drain electrode of source electrode and the second nmos pass transistor M2 of the first nmos pass transistor M1 in voltage sampling circuit 101.The one CMOS inverter comprises a PMOS transistor M0 and the 3rd nmos pass transistor M3.The input of one termination the one CMOS inverter of the first capacitor C 1, the other end ground connection VSS of the first capacitor C 1.Output circuit 103 comprises the first Schmidt trigger S1, the 2nd CMOS inverter and the 3rd CMOS inverter that are connected successively.The output of the input termination voltage detecting circuit 102 of the first Schmidt trigger S1, an effective reset signal PORN of output output of the 3rd CMOS inverter.The 2nd CMOS inverter comprises the 4th PMOS transistor M4 and the 5th nmos pass transistor M5, and the 3rd CMOS inverter comprises the 7th PMOS transistor M7 and the 6th nmos pass transistor M6.The output of output circuit 103 is connected to the input of delay circuit, and delay circuit requires the length of regulation output reset signal time according to the reset of Circuits System and to reset signal shaping.
Referring to Fig. 2 and Fig. 3, the course of work of the utility model reset circuit is:
1) in electrification reset process: the initial condition supply voltage VDD increase of starting from scratch, when vdd voltage lower than voltage sampling circuit 101 in during the cut-in voltage of the second nmos pass transistor M2, the one PMOS transistor M0 of voltage detecting circuit 102 is in cut-off region, the first nmos pass transistor M1 is in sub-threshold region, so the pull-down current ability of a CMOS inverter is greater than pull-up current ability in voltage detecting circuit 102, the output reset signal that makes the output of voltage detecting circuit 102 is low level.
When the value of supply voltage VDD is greater than the cut-in voltage of the second nmos pass transistor M2 in voltage sampling circuit 101, the first nmos pass transistor M1 and second all conductings of nmos pass transistor M2, two of voltage detecting circuit 102 is managed also conducting, but the first resistance R 1 is larger, so the electric current flowing through is very little, passes through formula:
Can obtain:
Obviously,
section 1
in
technological parameter temperature influence, but skew in the same way, Section 2
having negative temperature coefficient, is to be also offset in the same way, thus in the same way two of skew subtract each other and can offset the impact of mutual temperature.
The threshold voltage of a CMOS inverter in voltage detecting circuit 102
, when
time, inverter upset, now a PMOS transistor M0
with the 3rd nmos pass transistor M3's
electric current equates, can obtain:
Can be designed to
Obviously, 1-12 formula
in
technological parameter temperature influence, but skew in the same way, in 1-13 formula
having negative temperature coefficient, is to be also offset in the same way, thus in the same way two of skew subtract each other and can offset the impact of mutual temperature.
Voltage detecting circuit 102 is exported a signal that approaches zero-temperature coefficient, be entered into again the 2nd CMOS inverter of output circuit 103, the input of output termination the 3rd CMOS inverter of the 2nd CMOS inverter, the output of the 3rd CMOS inverter is exported effective reset signal PORN, supplies with chip and effectively resets.
2) in lower electric process: when supply voltage is normal, reset signal PORN is high level, in Fig. 2, B point is also high level, the first nmos pass transistor M1 in voltage sampling circuit 101 is in saturation region, and the 3rd nmos pass transistor M3 in voltage detecting circuit 102 and a PMOS transistor M0 path Continuous-flow mistake.When quick power-down conditions appears in power supply, vdd voltage reduces, and A point node potential, owing to there being electric capacity effect, does not occur large voltage fluctuation, the 3rd nmos pass transistor M3's
stable, a PMOS transistor M0's
reduce and finally cause a PMOS transistor M0 cut-off, the 3rd nmos pass transistor M3 is pulled down to fast B node and becomes low level.The discharging current of the 3rd nmos pass transistor M3 is several uA, B node only has the little by little capacitive load of device parasitism, general tens fF of capacitance are to tens fF, so within reaching 100ns the discharge time of B, improved the speed of electrify restoration circuit, much more no longer with power up, equally descend reset signal also to have the characteristic that approaches temperature coefficient, principle is the same with power up, to state here.
In sum, workflow of the present utility model is that power up is done preliminary judgement to supply voltage VDD, when detected supply voltage is the threshold voltage of voltage detecting circuit lower than the operating voltage of system requirements
time provide low level and approach the reset signal of zero-temperature coefficient.Lower electric process is when detected supply voltage VDD is higher than the threshold voltage of voltage detecting circuit
time provide rapidly high level too and approach the reset signal of zero-temperature coefficient.
Referring to Fig. 3, it is the selectable delay circuit of the utility model reset circuit.The reset signal PRON of the utility model embodiment output is as input, the second resistance R 2 one termination power vd D, the drain electrode of another termination the 8th nmos pass transistor M8; The grid of the 8th nmos pass transistor M8 connects the output of output circuit, source ground VSS.The drain electrode of one termination the 8th nmos pass transistor M8 of the second capacitor C 2, and connect the input of the second Schmidt trigger S2, other end ground connection VSS.Output termination the 4th CMOS inverter of the second Schmidt trigger S2, the input of output termination the 5th CMOS inverter of the 4th CMOS inverter, output output has and approaches long reset signal PORN2 of zero-temperature coefficient, resetting time.
Referring to Fig. 4, by emulated data, further illustrate result of the present utility model: in figure from right to left respectively the electrification reset threshold value of representative-40oC, 22.5 oC and 85 oC (
) simulation scenarios.By the simulation result on figure, can find out, reset threshold (
) within the scope of-40oC～85oC, deviation, within positive and negative 0.5%, illustrates that the utility model can well suppress the impact of temperature on reset circuit, meets the requirement of Circuits System to reset signal.
By to the follow-up connection delay circuit of the utility model reset circuit, the reset signal PORN that can export output circuit 103 carries out time of delay, and then effectively avoided because the reset signal PORN time is too short, causing carrying out active homing, further improved the antijamming capability of the utility model reset circuit.
It should be noted that, Fig. 1 to Fig. 4 only illustrates basic ideas of the present utility model in a schematic way, Fig. 1 to Fig. 4 only shows with built-up circuit relevant in the utility model but not built-up circuit number, shape, device arrangement mode, connected mode while implementing according to reality drawn, during its actual enforcement, kenel, quantity, connected mode, device arrangement mode, the device parameters of each circuit can be random change, and its each circuit compound mode also may be very complicated.
Above-described embodiment is only the utility model preferred embodiment, can not be used for limiting the utility model.Modification, equivalent variations and the apparent change etc. of any known technology that all genus those skilled in the art do on technical solutions of the utility model basis, within all should belonging to protection range of the present utility model.
Claims (4)
1. the reset circuit of high response speed, low-temperature coefficient, is characterized in that, it comprises the voltage sampling circuit (101), voltage detecting circuit (102) and the output circuit (103) that are connected successively, described voltage sampling circuit (101) comprises the first resistance (R1), one termination power vd D of the first resistance (R1), the drain and gate of another termination the first nmos pass transistor (M1) of the first resistance (R1), the source electrode of the first nmos pass transistor (M1) connects the drain electrode of the second nmos pass transistor (M2), the grid of the second nmos pass transistor (M2) connects the drain electrode of the first nmos pass transistor (M1), the grid of the grid of the first nmos pass transistor (M1) and the second nmos pass transistor (M2) is connected to the drain electrode of the first nmos pass transistor (M1), the source ground VSS of the second nmos pass transistor (M2), described voltage detecting circuit (102) comprises a CMOS inverter and the first electric capacity (C1), the input of the one CMOS inverter is received the drain electrode of source electrode and second nmos pass transistor (M2) of the first nmos pass transistor (M1) in voltage sampling circuit (101), and a CMOS inverter comprises a PMOS transistor (M0) and the 3rd nmos pass transistor (M3), the input of one termination the one CMOS inverter of the first electric capacity (C1), the other end ground connection VSS of the first electric capacity (C1), described output circuit (103) comprises the first Schmidt trigger (S1), the 2nd CMOS inverter and the 3rd CMOS inverter that are connected successively, the output of the input termination voltage detecting circuit (102) of the first Schmidt trigger (S1), an output effective reset signal of output (PORN) of the 3rd CMOS inverter, the 2nd CMOS inverter comprises the 4th PMOS transistor (M4) and the 5th nmos pass transistor (M5), and the 3rd CMOS inverter comprises the 7th PMOS transistor (M7) and the 6th nmos pass transistor (M6), the output of output circuit (103) is connected to the input of delay circuit, and delay circuit requires the length of regulation output reset signal time according to the reset of Circuits System and to reset signal shaping.
2. the reset circuit of high response speed according to claim 1, low-temperature coefficient, it is characterized in that, described the first nmos pass transistor (M1) is primary nmos pass transistor, the low turn-on voltage value that the first nmos pass transistor (M1) adopts is at 0～0.3V, and the second nmos pass transistor (M2) accepted standard cut-in voltage value is at 0.3V～0.7V.
3. the reset circuit of high response speed according to claim 1 and 2, low-temperature coefficient, is characterized in that, described the first resistance (R1) adopts current source, passive resistance or active device PMOS transistor.
4. the reset circuit of high response speed according to claim 3, low-temperature coefficient, is characterized in that, the first electric capacity (C1) in described voltage detecting circuit (102) adopts primary electric capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320631535.XU CN203554401U (en) | 2013-10-14 | 2013-10-14 | Reset circuit with high responding speed and low temperature coefficients |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320631535.XU CN203554401U (en) | 2013-10-14 | 2013-10-14 | Reset circuit with high responding speed and low temperature coefficients |
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| Publication Number | Publication Date |
|---|---|
| CN203554401U true CN203554401U (en) | 2014-04-16 |
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|---|---|---|---|
| CN201320631535.XU Withdrawn - After Issue CN203554401U (en) | 2013-10-14 | 2013-10-14 | Reset circuit with high responding speed and low temperature coefficients |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579263A (en) * | 2013-10-14 | 2015-04-29 | 北京同方微电子有限公司 | Reset circuit with high response speed and low temperature coefficient |
| CN106972846A (en) * | 2017-03-21 | 2017-07-21 | 上海华力微电子有限公司 | A kind of electrification reset circuit |
| CN107493097A (en) * | 2017-07-31 | 2017-12-19 | 天津大学 | Electrifying self-resetting circuit with long resetting time |
-
2013
- 2013-10-14 CN CN201320631535.XU patent/CN203554401U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579263A (en) * | 2013-10-14 | 2015-04-29 | 北京同方微电子有限公司 | Reset circuit with high response speed and low temperature coefficient |
| CN106972846A (en) * | 2017-03-21 | 2017-07-21 | 上海华力微电子有限公司 | A kind of electrification reset circuit |
| CN106972846B (en) * | 2017-03-21 | 2020-06-16 | 上海华力微电子有限公司 | Power-on reset circuit |
| CN107493097A (en) * | 2017-07-31 | 2017-12-19 | 天津大学 | Electrifying self-resetting circuit with long resetting time |
| CN107493097B (en) * | 2017-07-31 | 2020-02-07 | 天津大学 | Power-on self-reset circuit with long reset time |
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Address after: 100083 Beijing City, Haidian District Wudaokou Wangzhuang Road No. 1 Tongfang Technology Plaza D floor 18 West Patentee after: Beijing Tongfang Microelectronics Company Address before: 100083 Haidian District Tsinghua Tongfang Technology Plaza, block A, floor 29, Beijing Patentee before: Beijing Tongfang Microelectronics Company |
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Granted publication date: 20140416 Effective date of abandoning: 20180410 |