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CN106486446A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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Publication number
CN106486446A
CN106486446A CN201610730801.2A CN201610730801A CN106486446A CN 106486446 A CN106486446 A CN 106486446A CN 201610730801 A CN201610730801 A CN 201610730801A CN 106486446 A CN106486446 A CN 106486446A
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CN
China
Prior art keywords
pad electrode
pad
opening
wiring
semiconductor device
Prior art date
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Pending
Application number
CN201610730801.2A
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English (en)
Inventor
矢岛明
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Renesas Electronics Corp
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Renesas Electronics Corp
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Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN106486446A publication Critical patent/CN106486446A/zh
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract

提供一种半导体装置的制造方法及半导体装置，在半导体装置的测试中抑制焊锡接合不良而提高测试的可靠性。半导体装置的制造方法中，准备具有具备第一罩膜(2r)的第一焊盘电极(2aa)和具备第二罩膜(2t)的第二焊盘电极(2ab)的半导体晶圆(1)，而且形成在第一焊盘电极(2aa)上具有第一开口且在第二焊盘电极(2ab)上具有第二开口的聚酰亚胺层(2d)，然后形成经由第二开口与第二焊盘电极(2ab)连接的再配置布线(2e)。接着，以在第一焊盘电极(2aa)及再配置布线(2e)的凸块台(2ac)留下有机反应层(2ka、2kb)的方式在聚酰亚胺层(2f)形成开口，对半导体晶圆(1)实施热处理，然后在再配置布线(2e)上形成凸块。

Description

半导体装置的制造方法及半导体装置
技术领域
本发明涉及例如晶圆工艺封装等半导体装置的制造技术及半导体装置。
背景技术
在晶圆工艺封装(WPP：Wafer Process Package，或者也称作WLP：Wafer LevelPackage)中，将焊锡凸块接合于多个再配置布线(再布线)各自的终端。
此外，关于晶圆工艺封装的构造和组装，例如在日本特开2009-246218号公报(专利文献1)中有所记载，在该专利文献1中，公开了一种使探针接触晶圆工艺封装的电极来进行测试的技术。
现有技术文献
专利文献
专利文献1：日本特开2009-246218号公报
发明内容
发明所要解决的课题
在上述晶圆工艺封装中，在将非易失性存储器组装入半导体芯片的情况下，在其组装工序中存在测试非易失性存储器的工序。该测试工序包括被称作保持力烘烤工序的热处理工序，在向非易失性存储器写入数据之后，例如在250℃下施加72小时左右的热负荷。然后，在保持力烘烤工序之后确认写入存储器的数据是否消失。
在此，例如，若在存储器的测试工序之后形成再配置布线，则写入存储器的数据有可能在再配置布线形成时所实施的高温的热处理中消失。因此，为了防止写入存储器的数据消失，优选在形成再配置布线之后再进行对非易失性存储器的测试工序。
在该情况下，在上述非易失性存储器的测试工序中，会使探针接触再配置布线的焊盘来进行存储器测试，但由于在再配置布线的Cu层的表面形成的Ni层坚硬而与探针之间的接触电阻变大，所以测试的精度降低。此时，为了应对探针的接触电阻和确保焊锡凸块的润湿性，也可以考虑对再配置布线的焊盘实施镀Au，但Ni会因保持力烘烤而涌出到Au镀膜上并氧化，结果会招致探针的接触电阻增大、焊锡的润湿不良及接合不良。
其他的课题和新颖的特征将通过本说明书的记述及附图而变得明确。
用于解决课题的技术方案
一实施方式的半导体装置的制造方法中，准备半导体基板，该半导体基板具有：第一焊盘电极，形成于多个布线层的最上层，且在表面形成有第一金属膜；和第二焊盘电极，与上述第一焊盘电极电连接并且形成于上述多个布线层的最上层，且在表面形成有第二金属膜。而且，形成具有使上述第一焊盘电极的上述第一金属膜露出的第一开口和使上述第二焊盘电极的上述第二金属膜露出的第二开口的第一绝缘膜，形成经由上述第二开口与上述第二焊盘电极电连接的布线。而且，以在上述第一焊盘电极及上述布线各自的表面留下有机反应层的方式，在第二绝缘膜的上述第一焊盘电极上形成第三开口，且在上述第二绝缘膜的上述布线上形成第四开口。而且，在形成上述第四开口之后，对上述半导体基板实施热处理，然后，在上述第四开口的上述布线上形成凸块。
另外，一实施方式的半导体装置具有：半导体基板，具备主面，且形成有半导体电路；多个第一焊盘电极，在上述主面露出；多个第二焊盘电极，与上述多个第一焊盘电极电连接，且与上述多个第一焊盘电极形成于同一层；以及多个布线，覆盖上述多个第二焊盘电极，与上述多个第二焊盘电极电连接。而且，具有在上述多个布线上形成的绝缘膜和在上述多个布线的上述绝缘膜的开口部设置的多个凸块，上述多个第一焊盘电极的表面露出。
发明效果
根据上述一实施方式，在半导体装置的测试中，能够抑制焊锡接合不良，同时提高测试的可靠性。
附图说明
图1是透过内部而示出实施方式的半导体装置的主要部分的构造的一例的局部平面图。
图2是示出沿着图1所示的A-A线切断后的构造的剖视图。
图3是示出图1所示的半导体装置的主要部分的内部的构造的一例的放大局部剖视图。
图4是示出图1所示的半导体装置的主要部分的焊盘的构造的一例的放大局部平面图。
图5是示出图1所示的半导体装置的主要部分的焊盘排列和再布线的一例的平面图。
图6是示出图5的A部的构造的一例的放大局部平面图和放大局部剖视图。
图7是示出图5的B部的构造的一例的放大局部平面图和放大局部剖视图。
图8是示出图1的半导体装置的制造方法的一部分的流程图和剖视图。
图9是示出图1的半导体装置的制造方法的一部分的流程图和剖视图。
图10是示出图1的半导体装置的制造方法的一部分的流程图和剖视图。
图11是示出图1的半导体装置的制造方法的一部分的流程图和剖视图。
图12是示出图1的半导体装置的制造方法的一部分的流程图和剖视图。
图13是示出图1的半导体装置的制造方法中的氧化膜厚与有机反应层之间的关系的数据图。
图14是示出实施方式的变形例的构造的放大局部平面图。
图15是示出沿着图14所示的A-A线切断后的构造的局部剖视图。
图16是示出应用了实施方式的变形例的半导体装置的构造的剖视图。
具体实施方式
在以下的实施方式中，除了特别需要的情况以外，原则上不反复对同一或同样的部分进行说明。
而且，在以下的实施方式中，为了方便，在需要时分为多个部分或实施方式来进行说明，但除了特别明确说明的情况之外，它们并非彼此之间没有关系，一方是另一方的一部分或全部的变形例、详情、补充说明等。
另外，在以下的实施方式中，在提及要素的数量等(包括个数、数值、量、范围等)的情况下，除了特别明确说明的情况和在原理上明显限定于特定的数量的情况等之外，并不限于该特定的数量，也可以是特定的数量以上或以下。
另外，在以下的实施方式中，其构成要素(也包括要素步骤等)除了特别明确说明的情况和在原理上明显认为是必需的构成要素的情况等之外，当然不一定是必需的。
另外，在以下的实施方式中，关于构成要素等，在提到“由A构成”、“由A形成”、“具有A”、“包括A”时，除了特别明确说明了只有该要素的情况等之外，当然不排除除此以外的要素。同样，在以下的实施方式中，在提及构成要素等的形状、位置关系等时，除了特别明确说明的情况和在原理上认为明显不是这样的情况等之外，包括实质上与该形状等近似或类似的情形等。这一点关于上述数值及范围也是同样的。
以下，基于附图对本发明的实施方式进行详细说明。此外，在用于说明实施方式的所有附图中，对具有同一功能的部件标注同一标号，省略对其的反复说明。另外，为了使附图容易理解，即使是平面图，有时也附有影线。
<半导体装置的构造>
图1是透过内部而示出实施方式的半导体装置的主要部分的构造的一例的局部平面图，图2是示出沿着图1所示的A-A线切断后的构造的剖视图，图3是示出图1所示的半导体装置的主要部分的内部的构造的一例的放大局部剖视图，图4是示出图1所示的半导体装置的主要部分的焊盘的构造的一例的放大局部平面图。另外，图5是示出图1所示的半导体装置的主要部分的焊盘排列和再布线的一例的平面图，图6是示出图5的A部的构造的一例的放大局部平面图和放大局部剖视图，图7是示出图5的B部的构造的一例的放大局部平面图和放大局部剖视图。
图1所示的本实施方式的半导体装置是晶圆工艺封装体5，是与芯片尺寸大致同等的小型的半导体封装体。
使用图1和图2，对本实施方式的晶圆工艺封装体5的结构进行说明。晶圆工艺封装体5具有：半导体芯片2，具备主面2b，且在主面2b形成有半导体电路；多个第一焊盘电极2aa，与上述半导体电路电连接，且在主面2b露出；以及多个第二焊盘电极2ab，与多个第一焊盘电极2aa的各第一焊盘电极2aa电连接，且与多个第一焊盘电极2aa的各第一焊盘电极2aa形成于同一层。
也就是说，如图1所示，多个焊盘电极2a以排成两列的方式设置，其中，在外侧排列配置的是多个第一焊盘电极2aa，另一方面，在内侧排列配置的是多个第二焊盘电极2ab。
并且，多个第二焊盘电极2ab的各第二焊盘电极2ab连接有再配置布线(布线)2e。再配置布线2e是将多个第二焊盘电极2ab各自的位置变更配置于不同的位置的布线，也被称作再布线。
换言之，多个第一焊盘电极2aa的各第一焊盘电极2aa在半导体芯片2的主面2b的端部侧(周缘部侧)排列配置，另一方面，多个第二焊盘电极2ab的各第二焊盘电极2ab比多个第一焊盘电极2aa的各第二焊盘电极2ab靠内侧配置。并且，从在内侧配置的多个第二焊盘电极2ab的各第二焊盘电极2ab引出再配置布线2e。
具体地说，如图2所示，再配置布线2e覆盖多个第二焊盘电极2ab的各第二焊盘电极2ab，而且与多个第二焊盘电极2ab的各第二焊盘电极2ab电连接。并且，在再配置布线2e的与第二焊盘电极2ab相反的一侧的端部分别形成有凸块台2ac，在各凸块台2ac分别搭载有焊锡凸块(凸块)3作为晶圆工艺封装体5的外部端子。
具体地说，在多个再配置布线2e的各再配置布线2e之上形成有作为绝缘膜的聚酰亚胺层2f，而且在多个再配置布线2e的各再配置布线2e的聚酰亚胺层2f的开口部2m形成有凸块台2ac，在该凸块台2ac分别设置有焊锡凸块3。
此外，在外侧配置的多个第一焊盘电极2aa各自的表面露出。具体地说，如图2所示，在各第一焊盘电极2aa的表面形成有第一罩膜(第一金属膜)2r，而且在该第一罩膜2r上形成有有机反应层2ka。另外，第一罩膜2r延伸到多个第二焊盘电极2ab的各第二焊盘电极2ab之上。
详细地说，如图2所示，在第一焊盘电极2aa的Al焊盘2s的表面形成有第一罩膜2r，而且在第一罩膜2r的表面形成有作为有机薄膜的有机反应层2ka。并且，第一焊盘电极2aa的Al焊盘2s与第二焊盘电极2ab的Al焊盘2s相连。也就是说，第一焊盘电极2aa的Al焊盘2s与第二焊盘电极2ab的Al焊盘2s一体形成。换言之，本实施方式的Al焊盘2s也是带罩膜的Al焊盘2s。
并且，在第二焊盘电极2ab的区域中，也在Al焊盘2s的表面形成有第二罩膜(第二金属膜)2t。也就是说，在Al焊盘2s上，第一罩膜2r与第二罩膜2t也一体形成。
并且，该第二焊盘电极2ab连接有再配置布线2e。
此外，第一罩膜2r和第二罩膜2t例如是TiN。因此，由TiN构成的第一罩膜2r在第一焊盘电极2aa露出。
另外，再配置布线2e例如是三层构造，从下层侧朝向上层侧例如是Cu膜的晶种层2hb、Cu层2i、Ni层2n。
另外，如图3所示，在第一焊盘电极2aa的下层形成有多个布线层2u，各层的布线M经由插塞2w电连接。并且，在布线层2u的最下层，在漏极的插塞2w的两侧形成有存储器单元2v。该存储器单元2v例如是非易失性存储器(闪存)，在本实施方式的半导体芯片2形成有包括非易失性存储器电路的半导体电路。
另外，图4是第一焊盘电极2aa和第二焊盘电极2ab各自的平面视图，作为第一焊盘电极2aa的开口部的第一开口2ja的大小远大于作为第二焊盘电极2ab的开口部的第二开口2jb的大小(Y>X)。这是因为，如后所述，第一焊盘电极2aa是探针检查用或引线键合用的焊盘，另一方面，第二焊盘电极2ab是再配置布线连接用的焊盘。
这些焊盘的大小能够通过调整形成在焊盘上的绝缘膜的开口部的大小来容易地改变。
接着，对搭载于本实施方式的晶圆工艺封装体5的半导体芯片的焊盘构造进行说明。
图5所示的半导体芯片2示出安装图2所示的焊锡凸块3之前的构造。
在半导体芯片2的主面2b沿其周缘部呈两列地设置有焊盘电极2a。并且，呈两列配置的焊盘电极2a中，在内侧的列的第二焊盘电极2ab分别形成有再配置布线2e，多个再配置布线2e分别朝向主面2b的内方引出。而且，在各再配置布线2e的端部形成有凸块台2ac。
此外，各凸块台2ac在主面2b上沿X方向和Y方向以分别相等的间距排列设置。即，多个凸块台2ac在主面2b上呈格子状地排列设置。
由此，在多个凸块台2ac分别搭载有焊锡凸块3时，多个焊锡凸块3也呈格子状地配置。
另外，图6示出第一焊盘电极2aa和第二焊盘电极2ab的平面图和剖视图，本实施方式的第一焊盘电极2aa和第二焊盘电极2ab是相对于平面形状为细长的长方形的Al焊盘2s以中间隔着绝缘膜的方式形成两个绝缘膜的开口而得到的电极。因此，通过第一焊盘电极2aa和第二焊盘电极2ab，将一体形成的Al焊盘2s分为两个电极区域来使用。
由此，Al焊盘2s从第一焊盘电极2aa到第二焊盘电极2ab一体地相连，而且在该Al焊盘2s上配置有一体形成的第一罩膜2r和第二罩膜2t。也就是说，Al焊盘2s是带罩膜的Al焊盘2s。此外，第一罩膜2r和第二罩膜2t例如是TiN。
并且，在第一焊盘电极2aa的第一罩膜2r的表面形成有例如厚度为数百nm左右的极薄的有机反应层2ka。
另外，如上所述，在第一焊盘电极2aa的下层如图3所示那样形成有多个布线层2u，而且在其最下层形成有存储器单元2v，该存储器单元2v例如是非易失性存储器(闪存)。
另外，如图7所示，在从第二焊盘电极2ab引出的再配置布线2e的端部形成有凸块台2ac。在搭载图2所示的焊锡凸块3之前的凸块台2ac，在其最上层的Ni层2n的表面形成有作为有机薄膜的有机反应层2kb。
此外，在将焊锡凸块3搭载于凸块台2ac时，在该凸块台2ac的表面形成的有机反应层2kb例如通过灰化(ashing)而除去。由此，能够将焊锡凸块3沾到凸块台2ac上，能够使焊锡凸块3相对于凸块台2ac的连接良好。
在本实施方式的晶圆工艺封装体5中，在半导体芯片2的主面2b的周缘部呈两列设置的多个焊盘电极2a中的外侧(端部侧)的第一焊盘电极2aa就那样留着，内侧的列的第二焊盘电极2ab连接有再配置布线2e。
因而，通过在主面2b的周缘部(端部)设置与安装凸块用不同的另外的多个第一焊盘电极2aa，即使在搭载焊锡凸块之后，也能够使用第一焊盘电极2aa来实施探针测试。即，即使在组装晶圆工艺封装体5之后，也能够不使探针接触焊锡凸块3而是使探针接触第一焊盘电极2aa来进行探针测试。
此外，关于第一焊盘电极2aa和第二焊盘电极2ab，既可以如本实施方式这样通过将在细长的一个Al焊盘2s的上层形成的绝缘膜的开口分为两个来形成，也可以预先形成独立的Al焊盘2s并在这些Al焊盘2s形成第一焊盘电极2aa和第二焊盘电极2ab。
<半导体装置的制造方法>
接着，对本实施方式的半导体装置的制造方法进行说明。图8～图12是分别示出图1的半导体装置的制造方法的一部分的流程图和剖视图。
首先，进行图8所示的焊盘开口(留下罩)。在上述焊盘开口中，准备包括分别形成有第一区域2x和与第一区域2x不同的第二区域2y的多个半导体芯片2的半导体晶圆(半导体基板)1。此外，在半导体晶圆1的各半导体芯片2的区域形成有图3所示的多个布线层2u、在第一区域2x具备在多个布线层2u的最上层形成的第一罩膜2r的第一焊盘电极2aa、以及在第二区域2y具备在多个布线层2u的最上层形成的第二罩膜2t的第二焊盘电极2ab。
而且，在第一焊盘电极2aa及第二焊盘电极2ab中，形成有一体相连地形成的Al焊盘2s。具体地说，对于平面形状为细长的长方形的Al焊盘2s，以中间隔着绝缘膜的方式形成两个绝缘膜的开口，通过第一焊盘电极2aa和第二焊盘电极2ab，将一体形成的Al焊盘2s分为两个电极区域来使用。
也就是说，在作为在细长的Al焊盘2s上形成的绝缘膜的保护膜2z中，以分别留下第一罩膜2r和第二罩膜2t的方式形成第一焊盘电极2aa用的开口和第二焊盘电极2ab用的开口。此外，在Al焊盘2s上配置有一体形成的第一罩膜2r和第二罩膜2t。也就是说，Al焊盘2s是带罩膜的Al焊盘2s。在此，第一罩膜2r和第二罩膜2t例如是TiN。
另外，在第一焊盘电极2aa的下层如图3所示那样形成有多个布线层2u，而且在其最下层形成有存储器单元2v，该存储器单元2v例如是非易失性存储器(闪存)。
接着，进行图8所示的聚酰亚胺层图案化。在该聚酰亚胺层图案化中，在半导体晶圆1的主面1a上的保护膜2z上形成聚酰亚胺层2d，之后，通过图案化使第一焊盘电极2aa及第二焊盘电极2ab各自的上方开口。换言之，形成具有使第一罩膜2r在第一焊盘电极2aa上露出的第一开口2ja和使第二罩膜2t在第二焊盘电极2ab上露出的第二开口2jb的聚酰亚胺层(第一绝缘膜)2d。
此时，如图4所示，第一开口2ja的平面视图中的大小比第二开口2jb的平面视图中的大小大。即，第一焊盘电极2aa是探针检查用或引线键合用的焊盘，另一方面，第二焊盘电极2ab是再配置布线2e连接用的焊盘。由此，第一开口2ja>第二开口2jb。此外，这些焊盘的大小能够通过调整在焊盘上形成的绝缘膜(聚酰亚胺层2d)的开口部的大小来容易地改变。
在上述聚酰亚胺层图案化之后，进行图8所示的灰化。在上述灰化中，通过灰化除去在第二焊盘电极2ab的第二罩膜2t的表面形成的有机膜(有机反应层)。
在上述灰化之后，进行图8所示的晶种层溅射。在该晶种层溅射中，在聚酰亚胺层2d、第一焊盘电极2aa及第二焊盘电极2ab上通过溅射形成(堆积)晶种层2hb。由此，第一焊盘电极2aa和第二焊盘电极2ab分别与晶种层2hb电连接。首先，形成Cr膜2ha作为阻挡层(导体层)，然后在其上形成Cu膜2hb作为晶种层。另外，阻挡层(导体层)使用由与第一罩膜2r及第二罩膜2t不同的材料构成的膜，既可以是上述Cr膜2ha，也可以是由钛(TiN)构成的膜。
在上述晶种层溅射之后，进行图9所示的抗蚀剂图案化，在该抗蚀剂图案化中，留下将在之后的工序中形成的再配置布线2e的部位，利用抗蚀剂2g覆盖除此以外的区域。详细地说，隔着晶种层2hb在聚酰亚胺层(第一绝缘膜)2d上形成覆盖第一开口2ja且使第二开口2jb露出的作为掩膜层的抗蚀剂2g。也就是说，第一焊盘电极2aa的第一开口2ja上被抗蚀剂2g覆盖，而且第二焊盘电极2ab的第二开口2jb上不被抗蚀剂2g覆盖，使第二开口2jb露出。
在上述抗蚀剂图案化之后，进行图9所示的再配置布线-Cu/Ni电镀形成。在该再配置布线-Cu/Ni电镀形成中，形成经由第二开口2jb与第二焊盘电极2ab电连接且以Cu为主的再配置布线(布线)2e。在再配置布线2e的形成中，首先进行Cu的电镀形成，之后进行Ni的电镀形成。
详细地说，首先，在由抗蚀剂(掩膜层)2g包围的区域内的晶种层2hb上通过电镀形成Cu层2i。由此，在晶种层2hb上形成以Cu为主成分的再配置布线(Cu层2i)2e。之后，在再配置布线2e的表面上通过电镀形成Ni层2n。由此，形成晶种层2hb、再配置布线2e(Cu层2i)以及Ni层2n。
其结果，在第二焊盘电极2ab形成再配置布线2e，但在第一焊盘电极2aa不形成再配置布线2e。
在上述再配置布线-Cu/Ni电镀形成之后，进行图10所示的抗蚀剂除去·湿法蚀刻。在该抗蚀剂除去·湿法蚀刻中，除去包围再配置布线2e的抗蚀剂2g，而且除去第一焊盘电极2aa上(抗蚀剂2g的下方)的晶种层2hb和Cr膜2ha。
即，除去作为掩膜层的抗蚀剂2g而使第一开口2ja露出，而且以留下第一焊盘电极2aa的第一罩膜2r的方式，通过湿法蚀刻除去第一罩膜2r上的Cu膜(晶种层)2hb和Cr膜(导体层)。
此时，由于阻挡层为Cr膜2ha，第一罩膜2r为TiN膜，所以即使通过湿法蚀刻除去Cr膜2ha，第一罩膜2r也不会被除去，而会留在Al焊盘2s上。也就是说，Al焊盘2s维持着被第一罩膜2r覆盖的状态。
因此，能够防止Al焊盘2s腐蚀。
在上述抗蚀剂除去·湿法蚀刻之后，进行图10所示的聚酰亚胺层图案化。在该聚酰亚胺层图案化中，首先，在再配置布线2e上和第一焊盘电极2aa上形成聚酰亚胺层(第二绝缘膜)2f。然后，通过图案化使再配置布线2e的端部的上方和第一焊盘电极2aa上开口。
详细地说，以在第一焊盘电极2aa的表面留下有机反应层2ka的方式在聚酰亚胺层2f的第一焊盘电极2aa上形成第三开口2ma，且以在再配置布线2e的端部(凸块台2ac)的表面留下有机反应层2kb的方式在聚酰亚胺层2f的端部(凸块台2ac)上形成第四开口2mb。即，通过不进行灰化，在第一焊盘电极2aa的表面形成有机反应层2ka，而且在凸块台2ac的表面形成有机反应层2kb。此外，在仅将聚酰亚胺开口的情况下，能够形成表面具有防锈剂那样的效果的有机反应层2ka、2kb。由此，凸块台2ac的Ni层2n几乎不会被氧化，只要不进行灰化就可维持该效果。此时形成的有机反应层2ka和有机反应层2kb的厚度例如是100nm左右。
通过以上方式，在第一焊盘电极2aa处的第三开口2ma的表面形成了有机反应层2ka，另一方面，在再配置布线2e的端部的凸块台2ac处的第四开口2mb的表面形成了有机反应层2kb。
因此，Al焊盘2s上的第一罩膜2r没有露出到第一焊盘电极2aa的第三开口2ma，另一方面，在再配置布线2e的凸块台2ac的第四开口2mb处，再配置布线2e的Ni层2n也没有露出。
并且，在本实施方式中，能够通过有机反应层2kb来防止凸块台2ac的表面氧化，所以不对凸块台2ac的表面进行镀Au(金)形成(置换金)。
在此，使用图13，对基于有机反应层的有无的镀膜形成的可否进行说明。图13是示出图1的半导体装置的制造方法中的氧化膜厚与有机反应层之间的关系的数据图，针对存储器测试用热处理的初期和处理后以及有机反应层的“有”和“无”示出了氧化膜厚的比。此外，图13中的纵轴以能够形成镀Au的最大氧化膜厚(Ni氧化膜厚)为基准1，在图13中，表示在该基准1以下的范围内能够形成镀Au。
根据图13的氧化膜厚比，在存储器测试用热处理(保持力烘烤)之后，在有有机反应层的情况下，低于基准1而为0.5，相对于此，在无有机反应层的情况下，大幅超过基准1而为4.0。即，图13表示：若在金属表面形成有有机反应层，则即使是在存储器测试用热处理之后，也能够形成镀Au。
在本实施方式中，虽然如上所述对不对凸块台2ac的表面进行镀Au的情况进行说明，但若不考虑成本，则也可以形成镀Au。
在上述聚酰亚胺层图案化之后，进行图11所示的探针检查、写入。在本探针检查(第一探针检查)中，使探针4接触第一焊盘电极2aa来进行电检查，并且向非易失性存储器(存储器单元2v)写入数据。详细地说，在第一焊盘电极2aa的表面，利用探针4刺破有机反应层2ka和第一罩膜2r，使探针4接触Al焊盘2s，在该状态下实施探针检查(第一探针检查、对非易失性存储器的数据写入)。
这样，在本实施方式的半导体装置的组装中，除了连接再配置布线2e的第二焊盘电极2ab以外，不同于该第二焊盘电极2ab的另外的第一焊盘电极2aa形成为露出到外部，所以能够使探针4接触该第一焊盘电极2aa来进行探针检查。
在上述探针检查、写入之后，进行图11所示的烘烤250℃12h。即，对半导体晶圆1实施热处理。该热处理是形成于半导体芯片2的非易失性存储器(闪存)的烘烤测试(热负荷测试)，也被称作保持力烘烤测试，例如，在250℃下对半导体晶圆1加热12小时(在很多情况下也会进行72小时的测试)。在该情况下，上述热处理的温度250℃比焊锡凸块3的熔点(例如，在无铅焊锡的情况下是230℃)高。
因此，非易失性存储器的保持力烘烤测试若在搭载了焊锡凸块3之后进行则会导致焊锡凸块3熔融，所以必须在搭载焊锡凸块3之前实施。
另外，在保持力烘烤测试中，由于在250℃下长时间加热，所以担心会在再配置布线2e的凸块台2ac的表面形成氧化膜，但由于在再配置布线2e的凸块台2ac的表面形成了有机反应层2kb，所以Ni层2n的氧化不会发展。即，能够防止由高温烘烤(保持力烘烤)引起的凸块台2ac处的Ni的氧化(能够利用有机反应层2kb来保护再配置布线2e的Ni层2n)。
在上述烘烤250℃12h之后，进行图11所示的探针检查、保持测试。在本探针检查中，使探针4接触第一焊盘电极2aa来进行第二探针检查。上述第二探针检查是非易失性存储器(存储器单元2v)的高温烘烤后的测试，检查所写入的存储器的数据是否消失、或者是否产生了数据不良等。
此外，与第一探针检查同样，在本第二探针检查中，由于不同于连接有再配置布线2e的第二焊盘电极2ab的另外的第一焊盘电极2aa形成为露出到外部，所以也能够使探针4接触该第一焊盘电极2aa来进行第二探针检查。
在上述探针检查、保持测试之后，进行图12所示的灰化。在本工序中，通过灰化除去在再配置布线2e的凸块台2ac的表面形成的有机反应层2kb，由此，使凸块台2ac的Ni层2n露出。此外，也可以为了提高焊锡凸块3的润湿性而在凸块台2ac的表面形成镀金。
在上述灰化之后，进行图12所示的凸块形成。在本凸块形成中，在通过再配置布线2e的第四开口2mb而露出的凸块台2ac上搭载焊锡凸块3。此时，使用使Ni层2n活性化的焊剂来进行凸块搭载，之后进行回流(reflow)，由此使焊锡凸块3升温，使焊锡凸块3熔融。其结果，将焊锡凸块3与凸块台2ac的Ni层2n连接。
通过以上工序，凸块形成完成。由此，半导体芯片2的Al焊盘2s与焊锡凸块3经由再配置布线2e而电连接。
在上述凸块形成之后，进行图12所示的外观·抗剪测试。在该工序中，实施对半导体晶圆1的外观检查，并且使用剪切应力来检查焊锡凸块3的连接强度。
在上述外观·抗剪测试之后，通过切割来进行从半导体晶圆1切出各半导体芯片2的单片化，图1所示的晶圆工艺封装体5的组装完成。
在此，本实施方式的晶圆工艺封装体5具有在该半导体芯片2形成有非易失性存储器的构造。在这样形成有非易失性存储器的半导体基板的探针测试中，有时需要有非易失性存储器的存储器保持测试，但该测试温度例如在250℃下进行8小时，温度比无铅焊锡凸块的熔点230℃高，所以无法在凸块搭载后实施测试。另外，即使在再布线形成之前实施测试，由于再布线工艺的Max温度为350℃，所以也会产生存储器消失而没有意义。基于这样的背景，需要有能够在再布线形成之后且凸块搭载之前进行存储器测试的晶圆工艺封装体。
而且，在上述存储器测试中，使探针4接触再配置布线2e的焊盘来进行存储器测试，但在再配置布线2e的Cu层2i的表面形成的Ni层2n的接触电阻大而测试精度降低。此时，为了应对探针4的接触电阻和确保焊锡凸块3的润湿性，也可以考虑对再配置布线2e的焊盘实施镀Au，但Ni会因保持力烘烤而涌出到镀Au膜上并氧化，因此，结果会招致探针4的接触电阻增大、焊锡的润湿不良以及接合不良。
另外，作为应对Ni涌出到镀Au膜上的对策，也可以考虑在保持力烘烤之后在再配置布线2e的焊盘再次进行镀Au形成，但在该情况下，会因两次形成镀Au而招致成本增加。
于是，在本实施方式的半导体装置的制造方法中，对于需要进行存储器保持测试那样的超过焊锡熔点的高温的、长时间的测试的半导体芯片2，除了再布线构造之外，还新追加了带金属罩的Al焊盘。详细地说，在半导体芯片2的主面2b分别设置有测试用的第一焊盘电极2aa和引出再配置布线(再布线)2e的第二焊盘电极2ab。例如，如图4所示，靠近芯片端部的第一焊盘电极2aa设置成用于探针检查，且在第一焊盘电极2aa的内侧设置有再配置布线2e用的第二焊盘电极2ab。
此时，在第一焊盘电极2aa和第二焊盘电极2ab各自的Al焊盘2s上，第一罩膜2r与第二罩膜2t相连地一体形成，并且各电极的开口的大小根据探针检查用和再配置布线2e用而调整成了不同的尺寸(探针检查用的开口的大小>再配置布线2e用的开口的大小)。除此之外，第一焊盘电极2aa和第二焊盘电极2ab的Al焊盘2s由金属罩膜(第一罩膜2r和第二罩膜2t)覆盖，所以即使进行保持力烘烤等高温·长时间的测试，Al焊盘2s也会由金属罩膜(金属膜)保护。
另一方面，设置于再配置布线2e(再布线)的凸块台2ac由极薄的有机反应层2kb罩住。由此，能够防止凸块台2ac在保持力烘烤等热处理的期间氧化或腐蚀。
此外，在设置成用于探针检查的第一焊盘电极2aa，通过不进行在上层的聚酰亚胺层2f形成了开口之后的有机残渣处理即灰化，也在第一罩膜2r上留下了薄的有机反应层2ka，其结果，在形成再配置布线2e的工艺中，能够保护Al焊盘2s。
如以上那样，通过使用本实施方式的工艺和构造，能够同时获得所希望的耐热性和焊锡润湿性、焊锡接合性，能够在凸块形成之前实施超过焊锡凸块3的熔点的高温下的长时间的存储器保持测试。
此外，在本实施方式的半导体装置的制造方法中，无需对凸块台2ac实施镀金，所以能够抑制测试中的成本增加。因此，在半导体装置(半导体芯片2)的测试中，能够抑制成本的增加、焊锡接合不良，同时实现测试的稳定化而提高测试的可靠性。
另外，保持力烘烤等测试利用在半导体芯片2的主面2b的端部设置的第一焊盘电极2aa来进行，但此时由于利用悬臂来进行，所以穿透薄的有机反应层2ka和第一罩膜2r而使探针4接触。因此，不会产生测试中的导通的不良状况。
另外，搭载焊锡凸块3的再配置布线2e的凸块台2ac在进行灰化而除去有机反应层2kb从而使凸块台2ac的Ni层2n露出之后搭载焊锡凸块3，所以能够不妨碍针对焊锡凸块3的合金化反应地进行凸块搭载。
另外，从第二焊盘电极2ab引出再配置布线2e并形成了凸块台2ac，所以能够应对凸块台2ac的窄间距化。
另外，将测试用(探针检查用)的第一焊盘电极2aa和凸块搭载用的凸块台2ac分开，所以即使在保持力烘烤等高温放置试验之后进行凸块搭载，也不会使凸块搭载品质劣化。而且，在本实施方式的晶圆工艺封装体5中，即使在凸块搭载之后也能够使用测试用的第一焊盘电极2aa进行测试。
<变形例>
图14是示出实施方式的变形例的构造的放大局部平面图，图15是示出沿着图14所示的A-A线切断后的构造的局部剖视图，图16是示出应用了实施方式的变形例的半导体装置的构造的剖视图。
本变形例是将上述实施方式的半导体芯片2组装入图16所示的SIP(System InPackage)6，且使用线8将芯片之间电连接的构造。
即，是将线(金属线)8与图14所示的探针检查用的第一焊盘电极2aa连接，并如图16所示那样将相邻的半导体芯片2之间用线连接的构造的半导体装置。
也就是说，如图15所示，将金线等线8连接于靠近半导体芯片2的端部(外周部)配置的测试用(探针检查用)的第一焊盘电极2aa。通过使用第一焊盘电极2aa作为引线键合用焊盘，能够应用于如图16所示的作为COC(Chip On Chip)的SIP6。
图16所示的SIP6中，小形的半导体芯片7经由多个焊锡凸块3以倒装芯片连接的方式搭载于在封装基板9上搭载的多个半导体芯片2的各半导体芯片2之上。详细地说，在封装基板9上，多个半导体芯片2以各自的背面2c与封装基板9相对的方式面朝上安装，而且在各半导体芯片2上分别经由多个焊锡凸块3而倒装芯片连接有小形的半导体芯片7。
并且，利用半导体芯片2与半导体芯片7之间的平面尺寸的差，通过线8将相邻的半导体芯片2之间电连接。而且，各半导体芯片和多个线8被由树脂构成的密封体11树脂密封。另外，在封装基板9的下表面设置有多个球形电极10作为外部端子。即，图16所示的SIP6是混合了倒装芯片安装和引线键合安装的类型的半导体装置。
在SIP6中，上段侧的半导体芯片7例如是存储器芯片，下段侧的半导体芯片2例如是控制半导体芯片7的控制芯片。
在这样的SIP6中，如图14及图15所示，在半导体芯片2形成第一焊盘电极2aa和第二焊盘电极2ab，第一焊盘电极2aa用于连接线，第二焊盘电极2ab用于引出再配置布线2e。并且，将形成于再配置布线2e的凸块台2ac用于上段侧的半导体芯片7的倒装芯片连接，通过多个焊锡凸块3将下段侧的半导体芯片2与上段侧的半导体芯片7电连接。
如以上那样，通过在半导体芯片2形成第一焊盘电极2aa和第二焊盘电极2ab，能够在COC构造和SIP构造中采用本实施方式的半导体芯片2。
以上，虽然基于实施方式对由本发明人完成的发明进行了具体说明，但本发明不限定于此前所记载的实施方式，当然能够在不脱离其要旨的范围内进行各种变更。
在上述实施方式中，虽然对半导体装置为晶圆工艺封装体的情况进行了说明，但上述半导体装置只要具备具有再配置布线且设置有连接该再配置布线的第二焊盘电极2ab和不同于该第二焊盘电极2ab的另外的第一焊盘电极2aa的半导体芯片2即可，也可以是其他的半导体封装体。
另外，在上述实施方式中，虽然对第一焊盘电极2aa和第二焊盘电极2ab设置在一体形成的一个Al焊盘2s上的情况进行了说明，但也可以是第一焊盘电极2aa和第二焊盘电极2ab形成在不同的Al焊盘2s上且两者通过内部布线而连接的构造的焊盘。
而且，在不脱离上述实施方式中所说明的技术思想的要旨的范围内，可以将变形例彼此组合来进行应用。
标号说明
2：半导体芯片
2aa：第一焊盘电极
2ab：第二焊盘电极
2ac：凸块台
2d：聚酰亚胺层(第一绝缘膜)
2e：再配置布线(布线)
2f：聚酰亚胺层(第二绝缘膜)
2ha：Cr膜(导体层)
2hb：Cu膜(晶种层)
2ja：第一开口
2jb：第二开口
2ma：第三开口
2mb：第四开口
2r：第一罩膜(第一金属膜)
2t：第二罩膜(第二金属膜)
3：焊锡凸块(凸块)
4：探针
5：晶圆工艺封装体(半导体装置)

Claims (14)

1.一种半导体装置的制造方法，具有：
(a)工序，准备半导体基板，该半导体基板具有：第一焊盘电极，形成于多个布线层的最上层，且在表面形成有第一金属膜；和第二焊盘电极，与所述第一焊盘电极电连接并且形成于所述多个布线层的最上层，且在表面形成有第二金属膜；
(b)工序，形成第一绝缘膜，该第一绝缘膜具有使所述第一焊盘电极的所述第一金属膜露出的第一开口和使所述第二焊盘电极的所述第二金属膜露出的第二开口；
(c)工序，在所述第一绝缘膜上形成覆盖所述第一开口且使所述第二开口露出的掩膜层；
(d)工序，形成经由所述第二开口与所述第二焊盘电极电连接的布线；
(e)工序，在所述第一焊盘电极上和所述布线上形成第二绝缘膜；
(f)工序，以在所述第一焊盘电极及所述布线各自的表面留下有机反应层的方式，在所述第二绝缘膜的所述第一焊盘电极上形成第三开口，且在所述第二绝缘膜的所述布线上形成第四开口；
(g)工序，在所述(f)工序之后对所述半导体基板实施热处理；以及
(h)工序，在所述第四开口的所述布线上形成凸块。
2.根据权利要求1所述的半导体装置的制造方法，
在所述(d)工序之后，除去所述掩膜层而使所述第一开口露出，而且以留下所述第一焊盘电极的所述第一金属膜的方式，通过蚀刻除去所述第一金属膜上的导体层。
3.根据权利要求2所述的半导体装置的制造方法，
所述导体层由与所述第一金属膜不同的材料构成。
4.根据权利要求1所述的半导体装置的制造方法，
所述(g)工序的所述热处理的温度比所述凸块的熔点高。
5.根据权利要求1所述的半导体装置的制造方法，
在所述(f)工序与所述(g)工序之间，使探针接触所述第一焊盘电极来进行第一探针检查。
6.根据权利要求1所述的半导体装置的制造方法，
在所述(g)工序之后，使探针接触所述第一焊盘电极来进行第二探针检查。
7.根据权利要求1所述的半导体装置的制造方法，
在所述(g)工序之后且所述(h)工序之前，除去所述布线的表面的所述有机反应层。
8.根据权利要求1所述的半导体装置的制造方法，
所述(g)工序的所述热处理是在所述半导体基板的半导体芯片的区域形成的非易失性存储器的烘烤测试。
9.根据权利要求1所述的半导体装置的制造方法，
所述第一开口的平面视图中的大小比所述第二开口的平面视图中的大小大。
10.一种半导体装置，具有：
半导体芯片，具备主面，且形成有半导体电路；
多个第一焊盘电极，与所述半导体电路电连接，且在所述主面露出；
多个第二焊盘电极，与所述多个第一焊盘电极的各第一焊盘电极电连接，且与所述多个第一焊盘电极的各第一焊盘电极形成于同一层；
多个布线，覆盖所述多个第二焊盘电极的各第二焊盘电极，且与所述多个第二焊盘电极的各第二焊盘电极电连接；
绝缘膜，形成在所述多个布线上；以及
多个凸块，设置于所述多个布线的各布线的所述绝缘膜的开口部，所述多个第一焊盘电极的各第一焊盘电极的表面露出。
11.根据权利要求10所述的半导体装置，
在所述多个第一焊盘电极的各第一焊盘电极的表面形成有金属膜，所述金属膜延伸到所述多个第二焊盘电极的各第二焊盘电极之上。
12.根据权利要求10所述的半导体装置，
所述多个第一焊盘电极的各第一焊盘电极配置于所述半导体芯片的端部侧，且所述多个第二焊盘电极的各第二焊盘电极比所述多个第一焊盘电极的各第一焊盘电极靠内侧配置，
从配置于所述内侧的所述多个第二焊盘电极的各第二焊盘电极引出所述布线。
13.根据权利要求10所述的半导体装置，
所述半导体电路包含非易失性存储器电路。
14.根据权利要求10所述的半导体装置，
所述多个第一焊盘电极连接有金属线。
CN201610730801.2A 2015-08-27 2016-08-26 半导体装置的制造方法及半导体装置 Pending CN106486446A (zh)

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