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CN106486384A - 晶圆级封装的制作方法 - Google Patents

晶圆级封装的制作方法 Download PDF

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Publication number
CN106486384A
CN106486384A CN201610059629.2A CN201610059629A CN106486384A CN 106486384 A CN106486384 A CN 106486384A CN 201610059629 A CN201610059629 A CN 201610059629A CN 106486384 A CN106486384 A CN 106486384A
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CN
China
Prior art keywords
substrate
layer
wafer
level packaging
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610059629.2A
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English (en)
Inventor
吴铁将
施信益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Inotera Memories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inotera Memories Inc filed Critical Inotera Memories Inc
Publication of CN106486384A publication Critical patent/CN106486384A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种晶圆级封装的制作方法。先提供一基板，具有一上表面以及一下表面；在所述上表面形成一第一介电层；在所述第一介电层上形成一重分布层，其中所述包含至少一第二介电层与至少一金属层；在所述重分布层上形成一第一钝化层；在所述第一钝化层中形成凸块；将一芯片设置在所述重分布层上，其中所述芯片是通过所述凸块电连接所述重分布层中的所述金属层；形成一模塑料，位在所述第一钝化层上并且包围所述芯片；抛光所述基板的所述下表面，直到达到所述基板的一预定剩余厚度；以及在所述基板中形成多个穿板通孔。

Description

晶圆级封装的制作方法
技术领域
本发明是涉及半导体封装技术领域，特别是涉及一种晶圆级封装(waferlevel package,WLP)堆叠封装构件及其制作方法。
背景技术
随着半导体制造技术的进步，微电子器件的尺寸变得更小，器件中的电路也变得更密集。为了得到更小尺寸的微电子器件，其封装与安装到电路板上的结构都必须变得更紧密。
已知的CoWoS(Chip on Wafer on Substrate)工艺是利用穿硅通孔(ThroughSilicon Via,TSV)技术将多颗芯片整合成2.5D或3D集成电路装置，此架构能提供较高的内连结线密度、降低整体内连结线长度，并减轻RC负载，因此除了能达到较小的形状因子(form factor)，还能提升效能并减少耗电。其中，芯片可以通过形成在硅中介层(silicon interposer)或TSV中介层上的重分布层(redistribution layer,RDL)互连。上述TSV中介层由于工艺较复杂，所以成本通常较高。
重分布层是在晶圆表面上形成介电层与金属导线的叠层，将芯片原本的输入/输出(I/O)接垫重新布线分配到一个间距较宽松的布局范围。上述重布线的制作通常使用薄膜聚合物，例如苯并环丁稀(Benzocyclobutene,BCB)、聚亚酰胺(polyimind,PI)，或其他有机聚合物当作介电层材料，再以金属化工艺，例如铝或铜，形成金属导线，将芯片周围的接垫重新布线分配成阵列状连接垫。
晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一层相对较厚的模塑料。此模塑料与晶圆及芯片的热膨胀系数(CTE)的差异，容易导致封装翘曲或变形，也使得封装整体的厚度增加。晶圆翘曲(warpage)一直是本领域关注的问题。
晶圆翘曲使芯片与晶圆之间的接合不易维持，使“芯片对晶圆接合”(chipto wafer)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重分布层的晶圆级半导体封装工艺，问题更是严重。因此，本技术领域仍需要一个改良的晶圆级封装方法，可以解决上述问题。
发明内容
本发明的目的在于提供一种改良的晶圆级封装的制作方法，其中在芯片接合以及晶圆级模塑成型后，才进行穿硅通孔(或穿板通孔(through substratevia))的制作，如此可降低成本并减轻模塑成型后的翘曲情形。
根据本发明一实施例，本发明提供一种晶圆级封装的制作方法，包含有：提供一基板，具有一上表面以及一下表面；在所述上表面形成一第一介电层；在所述第一介电层上形成一重分布层，其中所述包含至少一第二介电层与至少一金属层；在所述重分布层上形成一第一钝化层；在所述第一钝化层中形成凸块；将一芯片设置在所述重分布层上，其中所述芯片是通过所述凸块电连接所述重分布层中的所述金属层；形成一模塑料，位在所述第一钝化层上并且包围所述芯片；抛光所述基板的所述下表面，直到达到所述基板的一预定剩余厚度；以及在所述基板中形成多个穿板通孔。其中所述基板的所述预定剩余厚度是根据所述晶圆级封装的翘曲程度及尺寸来决定。
毋庸置疑的，本领域的技术人员读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1到图10是根据本发明一实施例的剖面示意图，说明制作一晶圆级封装的方法。
其中，附图标记说明如下：
20 切割胶带
100 基板
100a 上表面
100b 下表面
101 穿孔
102 氧化衬垫层
110 介电层
200 重分布层
210 介电层
212 金属层
212a 凸块焊盘
310 钝化层
312 凸块
420 芯片(晶粒)
500 模塑料
520 介电层
610 穿硅通孔(穿板通孔)
710 钝化层
712 焊接锡球
t 剩余厚度
具体实施方式
接下来的详细说明须参考相关附图所示内容，用来说明可依据本发明具体实施的实施例。这些实施例提供足够的细节，可使本领域中的技术人员充分了解并具体实施本发明。在不悖离本发明的范围内，仍可稍做修改，应用在其他实施例上。
因此，接下来的详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义，也应属本发明涵盖的范围。本发实施例所参考的附图是示意图，并未按比例绘制，且相同或类似的特征通常以相同的附图标记描述。
本发明公开一种穿硅通孔后制(TSV-last)的晶圆级封装工艺，利用此工艺，可以弹性的设计基板的剩余厚度，可以有效的控制封装翘曲。前述穿硅通孔(或穿板通孔)是在芯片接合以及晶圆级模塑成型后，才开始制作。
请参考图1到图10。图1到图10是根据本发明一实施例的剖面示意图，说明制作一晶圆级封装的方法。根据图1所示，首先提供一基板100，例如，基板100可以包含硅基板，但不限于此。在基板100的上表面100a上，形成有至少一介电层110。其中，介电层110可以包含氧化硅，但不限于此。
根据图2所示，接着在介电层110上形成重分布层(RDL)200。重分布层200包含至少一介电层210与至少一金属层212。介电层210可包含例如氮化硅、氧化硅或类似的材料，但不限于此。金属层212可包含铝、铜、钨、钛、氮化钛或类似的材料。根据所述实施例，金属层212可包含多个凸块焊盘212a，自介电层212的上表面暴露出来。凸块焊盘212a设置在一芯片接合区域内。
根据图3所示，接着在重分布层200上方设置一钝化层(或介电层)310。然后，可以在重分布层200上形成多个凸块312，例如微凸块，当作后续连接使用。凸块312可以分别直接形成在金属层212的凸块焊盘212a上。
根据图4所示，形成凸块312后，个别的覆晶芯片或晶粒420以有源面朝下面对重分布层200的方式，通过凸块312安装到重分布层200上，形成“芯片对晶圆接合”(C2W)的层叠结构。这些个别的覆晶芯片或晶粒420是具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等等。上述步骤完成后，可选择性的在每一芯片或晶粒420下方填充底胶。接着，可进行热处理，使凸块312回焊。
晶粒接合完成后，接着在上方覆盖一模塑料500。模塑料500覆盖住安装好的芯片420与重分布层200的上表面。之后，会通过一固化工艺，使模塑料500固化。模塑料500例如是环氧树脂与二氧化硅填充剂的混和物，但并不限于此。可选择性的抛光移除部分模塑料500的上部，使芯片420的上表面暴露出来。
根据图5所示，在完成上述模塑成型(molding)工艺后，继续进行一抛光工艺，用来抛光基板100的一下表面100b，借此减少基板100的厚度。基板100的剩余厚度t可以视设计需求而定，例如，视翘曲程度而定。举例来说，基板100的剩余厚度t可以介于0到120微米之间。本发明的优点在于可以根据芯片封装的尺寸及所欲控制的翘曲程度，而弹性调整基板100的剩余厚度t，达到最佳翘曲控制结果。
根据图6所示，接着在基板100的下表面100b上沉积一介电层520，例如，硅氧层。
根据图7及图8所示，接着进行一穿硅通孔(或穿板通孔)工艺。首先，在基板100中形成多个穿孔101。例如，穿孔101可以利用现有的光刻工艺及蚀刻工艺来完成。接着，在穿孔101的侧壁上形成一氧化衬垫层102，如图7所示。接着，以导电材料，例如金属，将穿孔101填满。然后，将穿孔101外的多余金属抛光去除，如此形成穿硅通孔(或穿板通孔)610，如图8所示。
根据图9所示，接着在基板100的下表面100b上形成一钝化层710。钝化层710可包含例如氮化硅、氧化硅、氮氧化硅等无机材料，或例如聚亚酰胺(polyimide,PI)等有机材料。接着，可以继续在穿硅通孔610上分别形成焊接锡球712。例如，可利用现有的光刻工艺及蚀刻工艺在钝化层710中形成开口，再将锡球设置在各开口内，然后进行回焊。
本领域的技术人员应该可以理解图9中的基板100下表面100b所绘示的结构只是例示。例如，焊接锡球712不一定是直接形成在各个穿硅通孔610的底端。在其它实施例中，还可以在钝化层710上形成背面重分布层，可以用来进一步连结。上述钝化层710上的背面重分布层可以包含至少一金属层或多层金属层，而焊接锡球712可以设置在所述金属层所定义的金属焊盘上。此外，所述背面重分布层也可以与穿硅通孔610同时以铜镶嵌工艺来形成。
根据图10所示，进行切割工艺，分隔出个别的晶圆级封装10。例如，进行切割前，可先使用切割胶带20当作载体。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (7)

1.一种晶圆级封装的制作方法，其特征在于，包含有：
提供一基板，具有一上表面以及一下表面；
在所述上表面形成一第一介电层；
在所述第一介电层上形成一重分布层，其中所述重分布层包含至少一第二介电层与至少一金属层；
在所述重分布层上形成一第一钝化层；
在所述第一钝化层中形成凸块；
将一芯片设置在所述重分布层上，其中所述芯片是通过所述凸块电连接所述重分布层中的所述金属层；
形成一模塑料，位在所述第一钝化层上并且包围所述芯片；
抛光所述基板的所述下表面，直到达到所述基板的一预定剩余厚度；以及
在所述基板中形成多个穿板通孔。
2.根据权利要求1所述的晶圆级封装的制作方法，其特征在于，所述基板的所述预定剩余厚度是根据所述晶圆级封装的翘曲程度及尺寸来决定。
3.根据权利要求1所述的晶圆级封装的制作方法，其特征在于，所述基板是一硅基板。
4.根据权利要求1所述的晶圆级封装的制作方法，其特征在于，所述第一介电层包含氧化硅。
5.根据权利要求1所述的晶圆级封装的制作方法，其特征在于，所述第二介电层包含氮化硅或氧化硅。
6.根据权利要求1所述的晶圆级封装的制作方法，其特征在于，在所述基板中形成所述多个穿板通孔的步骤包含有：
在所述基板的所述下表面形成一第三介电层；
在所述基板及所述第三介电层中形成多个穿孔；
在所述多个穿孔的侧壁上形成一氧化衬垫层；
在所述多个穿孔内填入一导电材料；以及
抛光所述导电材料。
7.根据权利要求1所述的晶圆级封装的制作方法，其特征在于，另包含有：
在所述基板的所述下表面形成一第二钝化层；以及
在所述第二钝化层中形成焊接锡球，电连接所述穿板通孔。
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