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CN106257658A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN106257658A
CN106257658A CN201510744361.1A CN201510744361A CN106257658A CN 106257658 A CN106257658 A CN 106257658A CN 201510744361 A CN201510744361 A CN 201510744361A CN 106257658 A CN106257658 A CN 106257658A
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CN
China
Prior art keywords
layer
semiconductor device
passivation layer
interlayer dielectric
passivation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510744361.1A
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English (en)
Inventor
施信益
施能泰
姜序
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Inotera Memories Inc
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Filing date
Publication date
Application filed by Inotera Memories Inc filed Critical Inotera Memories Inc
Priority to CN202110375997.9A priority Critical patent/CN113113365B/zh
Publication of CN106257658A publication Critical patent/CN106257658A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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Abstract

本发明涉及一半导体器件，包括一中介层，具有一第一面及相对于第一面的第二面，其中所述中介层包括一重分布层，所述重分布层包括一位于所述第一面的第一钝化层与一位于所述第二面的第二钝化层；至少一芯片，通过多个贯穿所述第一钝化层的第一凸块安装在所述第一面的所述第一钝化层上；一模塑料，设置在所述第一面上，覆盖住所述芯片与所述第一钝化层的上表面；以及多个焊接凸块，设置在所述第二面的所述第二钝化层上。

Description

半导体器件
技术领域
本发明涉及半导体器件，特别涉及一种具有无衬底(substrate-less)或无穿硅通孔(through silicon via,TSV)中介层的晶圆级封装(wafer level package,WLP)的半导体器件及其制作方法。
背景技术
随着半导体制造技术的进步，微电子器件的尺寸变得更小，器件中的电路也变得更密集。为了得到更小尺寸的微电子器件，其封装与安装到电路板上的结构都必须变得更紧密。
半导体封装领域中所熟知的扇出晶圆级封装(FOWLP)，是通过位于衬底上的重分布层(RDL)，例如位于具有穿硅通孔(TSV)的衬底，将原本半导体晶粒的接垫重新布线分配到一较大的区域。
重分布层是在晶圆表面上形成介电层与金属导线的迭层，将芯片原本的输入/输出(I/O)接垫重新布线分配到一个间距较宽松的布局范围。上述重布线的制作通常使用薄膜高分子聚合物，例如苯并环丁稀(benzocyclobutene,BCB)、聚亚酰胺(polyimide,PI)，或其他有机高分子聚合物作为介电层材料，再以金属化工艺，例如铝或铜，形成金属导线，将芯片周围的接垫重新布线分配成阵列状连接垫。
由于工艺繁复，具有穿硅通孔的中介层衬底成本较高，因此，使用具有穿硅通孔中介层的扇出晶圆级封装也会比较昂贵，并不利于特定的应用场合。
发明内容
根据本发明提供的半导体器件，包括一中介层，具有一第一面及相对于第一面的第二面，其中所述中介层包括一重分布层，所述重分布层包括一位于所述第一面的第一钝化层与一位于所述第二面的第二钝化层；至少一芯片，通过多个贯穿所述第一钝化层的第一凸块安装在所述第一面的所述第一钝化层上；一模塑料，设置在所述第一面上，覆盖住所述芯片与所述第一钝化层的上表面；以及多个焊接凸块，设置在所述第二面的所述第二钝化层上。
根据本发明一实施例，所述重分布层还包括一第一层间介电层位于所述第一钝化层与第二钝化层之间，以及一第一介电阻挡层位于所述第一层间介电层与所述第二钝化层之间。
根据本发明一实施例，所述重分布层还包括一第二层间介电层位于所述第一钝化层与所述第一层间介电层之间，以及一第二介电阻挡层位于所述第一层间介电层与所述第二层间介电层之间。
毋庸置疑的，该领域的技术人士读完接下来本发明较优选施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1到图9为根据本发明实施例一使用无衬底或无穿硅通孔的中介层制作一晶圆级封装(WLP)的方法的示意性剖面图。
图10为本发明实施例二的晶圆级封装的示意性剖面图。
图11到图13为本发明实施例三的晶圆级封装的示意性剖面图。
其中，附图标记说明如下：
10/10a 晶圆级封装
300 载板
301 无穿硅通孔的中介层
302 黏着层、释放层
410 重分布层
420 晶粒
421 底胶
500 模塑料
518 凸块下金属层
520 锡球
600 切割胶带
610 有机介电层
310/510 钝化层
310a/310b/310c/610a 开口
312/316/324/328/332 介电阻挡层
314/322/326/330 层间介电层
401/403/405 介层插塞
402/404/406/408 镶嵌铜层
402a 焊盘
408a 凸块焊盘
610a 开口
具体实施方式
接下来的详细说明须参考相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例提供足够的细节，可使此领域中的技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细说明并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义者，也应属本发明涵盖的范围。
下面的描述须参考相关附图以便彻底理解本发明，其中相同或类似的特征通常以相同的附图标记描述，而且描述的结构并不必然按比例绘制。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具相同含意，可交替使用。
在本说明书中，“晶圆”与“基板”意指任何包括一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如重分布层(RDL)。须了解的是“基板”包括半导体晶圆，但并不限于此。"基板"在工艺中也意指包括制作于其上的材料层的半导体结构物。
请参考图1到图9，为根据本发明实施例一使用无衬底或无穿硅通孔中介层制作一晶圆级封装(WLP)的方法的示意性剖面图。
如图1所示，预备一载板300。载板300例如可为一晶圆状玻璃基板，包括一黏着层或释放层302层迭在所述玻璃基板的上表面上。释放层302上包括至少一钝化层310。钝化层310可包括氮化硅、氧化硅、氮氧化硅中的至少一种。接着，在钝化层310上方全面性的沉积一介电盖层或介电阻挡层312。介电阻挡层312可包括具有防止铜扩散的功能的材料，例如氮化硅，但并不限于此。
如图2所示，接着在介电阻挡层312上方设置一层间介电层(ILD)314。层间介电层314可包括氧化硅、硼硅酸玻璃、硼磷硅酸玻璃，或本领域现有的具有低介电系数的介电材料。接着，进行铜镶嵌工艺，在层间介电层314中形成镶嵌铜层402。然后，在层间介电层314与镶嵌铜层402上方沉积一介电阻挡层316。
铜镶嵌工艺为本领域的现有技术。例如，在层间介电层314中形成镶嵌铜层402包括下列步骤。首先，进行光刻工艺与蚀刻工艺，在层间介电层314中形成沟槽。接着，在沟槽中沉积金属阻挡层与铜层。然后，利用化学机械抛光工艺，去除掉沉积的金属多余的部分。镶嵌铜层402成为所述具有重分布层的中介层的第一金属层(M1)。
请参考图3。接着，进行如图2所描述的铜镶嵌工艺，在钝化层310上形成重分布层(RDL)410。例如，重分布层410可包括通过铜镶嵌工艺形成的四层金属(M1～M4/V1～V3)结构。须了解形成四层金属结构仅为说明目的，在一些实施例中，也可根据不同的设计需求，采用仅包括一层或两层金属的结构。
重分布层410可包括一介电层迭层，其中包括钝化层310、介电阻挡层312、层间介电层314、介电阻挡层316、层间介电层322、介电阻挡层324、层间介电层326、介电阻挡层328、层间介电层330以及介电阻挡层332。镶嵌铜层402、404、406、408以及介层插塞401、403、405设置在所述介电层迭层中。介层插塞401、403、405穿透个别对应的介电阻挡层316、324、328，与介电阻挡层下方的镶嵌铜层电性连接。
根据实施例一，镶嵌铜层408可包括多个自层间介电层330的上表面暴露出来的凸块焊盘408a。凸块焊盘408a设在芯片安装区域内。这时，镶嵌铜层408与层间介电层330会被一最顶部的介电阻挡层332覆盖住。
如图4所示，接着在最顶部的介电阻挡层332上方设置一钝化层510。钝化层510可包括氮化硅、氧化硅、氮氧化硅中的至少一种。须了解的是钝化层510也可包括有机材料，例如聚亚酰胺(polyimide,PI)、苯并环丁稀(benzocyclobutene,BCB)、聚苯恶唑(polybenzoxazole,PBO)，或其他类似材料。然后，可在凸块焊盘408a上形成多个凸块418，例如微凸块，作为后续连接使用。例如，以光刻工艺与蚀刻工艺，在钝化层510与最顶部介电阻挡层332中形成开口，使个别的凸块焊盘408a暴露出来。接着，可在开口中形成凸块下金属(UBM)，然后再形成焊接凸块或焊接球于个别的凸块焊盘408a上。
如图5所示，形成凸块418后，个别的覆晶芯片或晶粒420以有源面朝下面对重分布层410的方式，通过凸块418安装到重分布层410上，形成“芯片对晶圆接合”(C2W)的层迭结构。这些个别的覆晶芯片或晶粒420为具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等等。上述步骤完成后，可选择性地在每一芯片或晶粒420下方填充底胶421。然后，进行热处理，使凸块418回焊。
如图6所示，晶粒接合完成后，接着在上方覆盖一模塑料500。模塑料500覆盖住安装好的芯片420与重分布层410的上表面。模塑料500随后会通过一固化工艺使之固化。模塑料500例如为环氧树脂与二氧化硅填充剂的混和物，但并不限于此。可选择性地抛光移除部分模塑料500的上部，使芯片420的上表面暴露出来。
如图7所示，形成模塑料500后，再将载板300剥离，使钝化层310暴露出来，形成包括重分布层410的无穿硅通孔的中介层301。释放层302也被移除，使钝化层310的下表面暴露出来。可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。剥离载板300时，可以提供另一个暂时性的载板(图未示)固定于模塑料500上方。
之后，如图8所示，载板300剥离完成后，接着在钝化层310与介电阻挡层312形成开口，使个别焊盘402a暴露出来，然后在个别焊盘402a上形成焊锡凸块或锡球520。在一些实施例中，可在锡球520形成前，预先于开口中形成凸块下金属层(UBM)518。
之后，如图9所示，进行切割工艺，分隔出个别的晶圆级封装10。例如，进行切割前，可先将晶圆级封以锡球520朝向切割胶带600的方向固定在切割胶带600上，其中锡球520可能接触到切割胶带600。须了解的是，虽然图9中每个晶圆级封装10包括两个芯片，在一些实施例中，每个晶圆级封装10可能仅包括一个芯片。
图10为根据本发明实施例二的晶圆级封装的示意性剖面图。与图9中晶圆级封装10的不同处在于，图10所示晶圆级封装10a的焊盘402a上方包括多个开口310a、310b与310c，可释放锡球520造成的应力。
图11到图13为本发明实施例三的晶圆级封装的示意性剖面图。请参考图11，在形成模塑料500后，进行与前述实施例相似的步骤，将载板300剥离，使钝化层310暴露出来，形成包括重分布层410的无穿硅通孔的中介层301。释放层302也被移除，使钝化层310的下表面暴露出来。可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。剥离载板300时，可以提供另一个暂时性的载板(图未示)固定于模塑料500上方。
根据实施例三，当要形成具有相对较大尺寸的焊接球时，例如尺寸大于200微米(μm)的球栅阵列锡球，会先在暴露出来的钝化层310下表面形成一有机介电层610。根据所述实施例，有机介电层610可包括聚亚酰胺(polyimide,PI)、苯并环丁稀(Benzocyclobutene,BCB)、聚苯恶唑(polybenzoxazole,PBO)，或其他类似材料。
如图12所示，有机介电层610沉积完成后，接着在有机介电层610、钝化层310和介电阻挡层312中形成开口610a，使个别焊盘402a暴露出来。
如图13所示，接着在个别焊盘402a上形成焊锡凸块或锡球520。在一些实施例中，可在锡球520形成前先于开口610a中形成凸块下金属层(UBM)518。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

1.一半导体器件，其特征在于，包括:
一中介层，具有一第一面及相对于第一面的第二面，其中所述中介层包括一重分布层，所述重分布层包括一位于所述第一面的第一钝化层与一位于所述第二面的第二钝化层；
至少一芯片，通过多个贯穿所述第一钝化层的第一凸块安装在所述第一面的所述第一钝化层上；
一模塑料，设置在所述第一面上，覆盖住所述芯片与所述第一钝化层的上表面；以及
多个焊接凸块，设置在所述第二面的所述第二钝化层上。
2.根据权利要求1所述的半导体器件，其特征在于，所述第一钝化层包括氮化硅、氧化硅、氮氧化硅中的至少一种。
3.根据权利要求1所述的半导体器件，其特征在于，所述第二钝化层包括氮化硅、氧化硅、氮氧化硅中的至少一种。
4.根据权利要求1所述的半导体器件，其特征在于，所述重分布层还包括一位于所述第一钝化层与所述第二钝化层之间的第一层间介电层，以及一位于所述第一层间介电层与所述第二钝化层之间的第一介电阻挡层。
5.根据权利要求4所述的半导体器件，其特征在于，所述第一层间介电层包括氧化硅、硼硅酸玻璃或硼磷硅酸玻璃。
6.根据权利要求4所述的半导体器件，其特征在于，所述第一介电阻挡层包括氮化硅。
7.根据权利要求4所述的半导体器件，其特征在于，还包括一第一金属层镶嵌在所述第一层间介电层中。
8.根据权利要求7所述的半导体器件，其特征在于，所述重分布层还包括一位于所述第一钝化层与所述第一层间介电层之间的第二层间介电层，以及一位于所述第一层间介电层与所述第二层间介电层之间的第二介电阻挡层。
9.根据权利要求8所述的半导体器件，其特征在于，所述第二层间介电层包括氧化硅、硼硅酸玻璃或硼磷硅酸玻璃。
10.根据权利要求8所述的半导体器件，其特征在于，所述第二介电阻挡层包括氮化硅。
11.如权利要求8所述的半导体器件，其特征在于，所述重分布层还包括一位于所述第二层间介电层中的第二金属层以及第一介层插塞，其中所述第二金属层通过所述第一介层插塞与所述第一金属层电性连接。
12.根据权利要求8所述的半导体器件，其特征在于，所述重分布层还包括一第三介电阻挡层，位于所述第二层间介电层与所述第一钝化层之间。
13.根据权利要求12所述的半导体器件，其特征在于，所述第三介电阻挡层包括氮化硅。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108695166A (zh) * 2017-04-07 2018-10-23 台湾积体电路制造股份有限公司 封装件及其形成方法
CN108695176A (zh) * 2017-04-10 2018-10-23 台湾积体电路制造股份有限公司 封装件及其形成方法
CN109524314A (zh) * 2017-09-18 2019-03-26 台湾积体电路制造股份有限公司 封装件及其形成方法
CN109755206A (zh) * 2017-11-01 2019-05-14 三星电机株式会社 连接构件及其制造方法以及半导体封装件
CN113451140A (zh) * 2020-03-24 2021-09-28 合肥晶合集成电路股份有限公司 封装结构的形成方法
US11769718B2 (en) 2017-04-10 2023-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US12113005B2 (en) 2017-04-07 2024-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
WO2025045026A1 (zh) * 2023-08-29 2025-03-06 矽磐微电子(重庆)有限公司 半导体结构的制造方法及半导体结构

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170062240A1 (en) * 2015-08-25 2017-03-02 Inotera Memories, Inc. Method for manufacturing a wafer level package
US9704790B1 (en) * 2016-03-14 2017-07-11 Micron Technology, Inc. Method of fabricating a wafer level package
US9984995B1 (en) * 2016-11-13 2018-05-29 Nanya Technology Corporation Semiconductor package and manufacturing method thereof
US10177011B2 (en) * 2017-04-13 2019-01-08 Powertech Technology Inc. Chip packaging method by using a temporary carrier for flattening a multi-layer structure
KR102077455B1 (ko) 2017-07-04 2020-02-14 삼성전자주식회사 반도체 장치
US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
CN110235242B (zh) * 2017-10-23 2023-12-01 京东方科技集团股份有限公司 集成电路芯片、显示装置和制造集成电路芯片的方法
US11699651B2 (en) 2017-10-23 2023-07-11 Applied Materials, Inc. Fan-out interconnect integration processes and structures
KR102099750B1 (ko) 2017-11-01 2020-04-10 삼성전자주식회사 반도체 패키지
US10529693B2 (en) * 2017-11-29 2020-01-07 Advanced Micro Devices, Inc. 3D stacked dies with disparate interconnect footprints
KR102055595B1 (ko) * 2017-12-15 2019-12-16 삼성전자주식회사 반도체 패키지
TWI655739B (zh) * 2018-04-19 2019-04-01 南亞電路板股份有限公司 封裝結構及其形成方法
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
US10923421B2 (en) * 2019-04-23 2021-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11296062B2 (en) * 2019-06-25 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimension large system integration
TWI739413B (zh) * 2020-05-04 2021-09-11 力成科技股份有限公司 半導體裝置及其製造方法
KR20220033551A (ko) 2020-09-07 2022-03-17 삼성전자주식회사 반도체 패키지
US11973058B2 (en) 2021-11-25 2024-04-30 International Business Machines Corporation Multiple die assembly

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2612071Y (zh) * 2003-02-27 2004-04-14 威盛电子股份有限公司 芯片封装结构
US20040235220A1 (en) * 2003-05-22 2004-11-25 Renesas Technology Corp. Flip chip mounting method
US20100065954A1 (en) * 2005-04-18 2010-03-18 Chao-Chun Tu Bond pad structures and semiconductor devices using the same
US20100099250A1 (en) * 2008-10-21 2010-04-22 Samsung Electronics Co., Ltd. Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers
WO2010100706A1 (ja) * 2009-03-05 2010-09-10 パナソニック株式会社 半導体装置
US20110079917A1 (en) * 2009-10-06 2011-04-07 Broadcom Corporation Interposer structure with passive component and method for fabricating same
US20110266670A1 (en) * 2010-04-30 2011-11-03 Luke England Wafer level chip scale package with annular reinforcement structure
CN102637713A (zh) * 2012-03-31 2012-08-15 江阴长电先进封装有限公司 一种含有金属微凸点的图像传感器封装方法
CN102832188A (zh) * 2011-06-16 2012-12-19 台湾积体电路制造股份有限公司 具有厚聚合物层的焊球保护结构
CN103165477A (zh) * 2011-12-14 2013-06-19 新科金朋有限公司 形成垂直互连结构的方法和半导体器件
CN103579197A (zh) * 2012-07-19 2014-02-12 矽品精密工业股份有限公司 具有防电磁波干扰的半导体组件
US20140131858A1 (en) * 2012-11-14 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Control of Semiconductor Die Package
CN104051422A (zh) * 2013-03-14 2014-09-17 台湾积体电路制造股份有限公司 互连结构及其形成方法
CN104051411A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 叠层封装结构
US20140295661A1 (en) * 2008-02-11 2014-10-02 Infineon Technologies Ag Passivated Copper Chip Pads
US20140306341A1 (en) * 2013-02-08 2014-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Packages and Methods for Forming the Same
US20140311771A1 (en) * 2013-04-17 2014-10-23 Shinko Electric Industries Co., Ltd. Wiring board
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
TW200600975A (en) * 2004-02-20 2006-01-01 Jsr Corp Bilayer laminated film for bump formation and method of bump formation
KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법
US8426961B2 (en) * 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US9502390B2 (en) * 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8952533B2 (en) * 2012-09-10 2015-02-10 Futurewei Technologies, Inc. Devices and methods for 2.5D interposers
US10192796B2 (en) * 2012-09-14 2019-01-29 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP
US9385102B2 (en) * 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
US9543373B2 (en) * 2013-10-23 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
JP2015095482A (ja) * 2013-11-08 2015-05-18 アイメックＩｍｅｃ 半導体部品上へのマイクロバンプの作製方法
US9721922B2 (en) 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package
US9402312B2 (en) * 2014-05-12 2016-07-26 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US10490521B2 (en) * 2014-06-26 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced structure for info wafer warpage reduction

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2612071Y (zh) * 2003-02-27 2004-04-14 威盛电子股份有限公司 芯片封装结构
US20040235220A1 (en) * 2003-05-22 2004-11-25 Renesas Technology Corp. Flip chip mounting method
US20100065954A1 (en) * 2005-04-18 2010-03-18 Chao-Chun Tu Bond pad structures and semiconductor devices using the same
US20140295661A1 (en) * 2008-02-11 2014-10-02 Infineon Technologies Ag Passivated Copper Chip Pads
US20100099250A1 (en) * 2008-10-21 2010-04-22 Samsung Electronics Co., Ltd. Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers
WO2010100706A1 (ja) * 2009-03-05 2010-09-10 パナソニック株式会社 半導体装置
US20110079917A1 (en) * 2009-10-06 2011-04-07 Broadcom Corporation Interposer structure with passive component and method for fabricating same
US20110266670A1 (en) * 2010-04-30 2011-11-03 Luke England Wafer level chip scale package with annular reinforcement structure
CN102832188A (zh) * 2011-06-16 2012-12-19 台湾积体电路制造股份有限公司 具有厚聚合物层的焊球保护结构
CN103165477A (zh) * 2011-12-14 2013-06-19 新科金朋有限公司 形成垂直互连结构的方法和半导体器件
CN102637713A (zh) * 2012-03-31 2012-08-15 江阴长电先进封装有限公司 一种含有金属微凸点的图像传感器封装方法
CN103579197A (zh) * 2012-07-19 2014-02-12 矽品精密工业股份有限公司 具有防电磁波干扰的半导体组件
US20140131858A1 (en) * 2012-11-14 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Control of Semiconductor Die Package
US20140306341A1 (en) * 2013-02-08 2014-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Packages and Methods for Forming the Same
CN104051422A (zh) * 2013-03-14 2014-09-17 台湾积体电路制造股份有限公司 互连结构及其形成方法
CN104051411A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 叠层封装结构
US20140311771A1 (en) * 2013-04-17 2014-10-23 Shinko Electric Industries Co., Ltd. Wiring board
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12113005B2 (en) 2017-04-07 2024-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
CN108695166A (zh) * 2017-04-07 2018-10-23 台湾积体电路制造股份有限公司 封装件及其形成方法
US11610858B2 (en) 2017-04-07 2023-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
CN108695166B (zh) * 2017-04-07 2021-02-09 台湾积体电路制造股份有限公司 封装件及其形成方法
US11469166B2 (en) 2017-04-10 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
CN108695176A (zh) * 2017-04-10 2018-10-23 台湾积体电路制造股份有限公司 封装件及其形成方法
US11769718B2 (en) 2017-04-10 2023-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10748841B2 (en) 2017-04-10 2020-08-18 Taiwan Semiconductor Manufacturing Company, Co., Ltd. Packages with Si-substrate-free interposer and method forming same
CN108695176B (zh) * 2017-04-10 2020-12-22 台湾积体电路制造股份有限公司 封装件及其形成方法
US10685910B2 (en) 2017-09-18 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10971443B2 (en) 2017-09-18 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
CN112509931A (zh) * 2017-09-18 2021-03-16 台湾积体电路制造股份有限公司 封装件及其形成方法
US11527465B2 (en) 2017-09-18 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with Si-substrate-free interposer and method forming same
CN109524314B (zh) * 2017-09-18 2020-11-27 台湾积体电路制造股份有限公司 封装件及其形成方法
CN109524314A (zh) * 2017-09-18 2019-03-26 台湾积体电路制造股份有限公司 封装件及其形成方法
CN112509931B (zh) * 2017-09-18 2024-12-27 台湾积体电路制造股份有限公司 封装件及其形成方法
CN109755206B (zh) * 2017-11-01 2023-05-23 三星电子株式会社 连接构件及其制造方法以及半导体封装件
CN109755206A (zh) * 2017-11-01 2019-05-14 三星电机株式会社 连接构件及其制造方法以及半导体封装件
CN113451140A (zh) * 2020-03-24 2021-09-28 合肥晶合集成电路股份有限公司 封装结构的形成方法
WO2025045026A1 (zh) * 2023-08-29 2025-03-06 矽磐微电子(重庆)有限公司 半导体结构的制造方法及半导体结构

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US20160372395A1 (en) 2016-12-22

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