CN106455312A - Wiring board and manufacturing method thereof - Google Patents

Abstract

The present invention provides a wiring board and its manufacturing method. In the wiring board of the present disclosure, a wiring conductor is buried on the surface of the insulating layer so that the top surface is exposed, and the wiring conductor is buried in the insulating layer. inclined part.

Description

Wiring substrate and its manufacturing method

technical field

The present invention relates to a wiring substrate having high-density fine wiring and a method of manufacturing the same.

Background technique

Conventionally, a wiring board including a plurality of insulating layers has provided wiring conductors between the insulating layers and on the surface of the outermost insulating layer. A plurality of via holes are formed in each insulating layer. The inside of the via hole is covered with a via conductor integrally formed with the wiring conductor. The via conductors provide electrical conduction between the wiring conductors formed in the respective insulating layers. The uppermost wiring conductor is embedded in the insulating layer so that the top surface is exposed on the surface of the insulating layer. In addition, a part of the uppermost wiring conductor forms a semiconductor element connection pad. Electrodes of semiconductor elements such as semiconductor integrated circuit elements are connected to the semiconductor element connection pads via solder. A part of the wiring conductor formed in the lowermost layer forms a circuit board connection pad. The electrodes of the circuit board on which the wiring board is mounted are connected to the circuit board connection pads. In addition, the semiconductor element operates by transmitting electrical signals between the semiconductor element and the circuit board via the wiring conductor. Such a wiring board is described in JP-A-63-232483, for example.

Contents of the invention

In the wiring board of the present disclosure, a wiring conductor is buried on the surface of the insulating layer so that the top surface is exposed, and the wiring conductor is buried in the insulating layer. inclined part.

In the method of manufacturing a wiring board according to the present disclosure, a plating resist layer having an opening pattern having an opening step portion or an opening inclined portion whose width becomes narrower toward the base metal layer is formed on the base metal layer. filling the opening pattern with a plating metal layer for wiring conductors having a wiring step or a wiring slope corresponding to the opening step or opening slope, and removing the plating resist layer; An insulating layer is formed on the base metal layer and the plated metal layer to completely bury the plated metal layer, and the base metal layer is etched away to form a wiring conductor whose top surface is exposed from the insulating layer , and includes the plated metal layer having the wiring step portion or the wiring slope portion having a width wider than that of the top surface at a portion embedded in the insulating layer.

Description of drawings

FIG. 1 is a schematic cross-sectional view showing one embodiment of a wiring board according to the present disclosure.

2 is an enlarged cross-sectional view of main parts in one embodiment of the wiring board according to the present disclosure.

3A to 3D are schematic cross-sectional views illustrating one embodiment of a method for manufacturing a wiring board according to the present disclosure.

4E to I are schematic cross-sectional views illustrating one embodiment of a method for manufacturing a wiring board according to the present disclosure.

5J to L are schematic cross-sectional views illustrating one embodiment of a method for manufacturing a wiring board according to the present disclosure.

6M to 6O are schematic cross-sectional views illustrating one embodiment of a method for manufacturing a wiring board according to the present disclosure.

7 is an enlarged cross-sectional view of main parts showing another embodiment of a wiring board according to the present disclosure.

8 is an enlarged cross-sectional view of main parts for illustrating another embodiment of the method of manufacturing a wiring board according to the present disclosure.

9 is an enlarged cross-sectional view of a main part for illustrating yet another embodiment of a method of manufacturing a wiring board according to the present disclosure.

detailed description

As wiring conductors are miniaturized, the contact area between wiring conductors and insulating layers is reduced. As a result, the adhesive strength of a wiring conductor becomes small, and a wiring conductor becomes easy to peel off from an insulating layer. For this reason, electrical signals cannot be transmitted well through the wiring conductor, and the semiconductor element may not operate stably.

In the wiring board of the present disclosure, the wiring conductor is embedded so that the top surface is exposed on the surface of the insulating layer, and the portion embedded in the insulating layer has a wiring step portion or a wiring slope portion wider than the width of the top surface. In this way, since the wiring step portion or the wiring slope portion wider than the width of the top surface is embedded in the insulating layer, peeling of the wiring conductor from the insulating layer can be suppressed. Hereinafter, one embodiment of a wiring board according to the present disclosure will be described based on FIGS. 1 and 2 . FIG. 2 is an enlarged view of main parts of FIG. 1 .

As shown in FIG. 1, the wiring board A of one embodiment has, for example, a multilayer structure in which four insulating layers 1 are stacked, and wiring conductors 2 are formed between the insulating layers 1 and on the surface of the outermost insulating layer 1. . The insulating layer 1 can be formed of thermosetting resins such as epoxy resin and bismaleimide triazine resin, for example, and an inorganic insulating filler is dispersed therein. A plurality of via holes 3 are formed in the insulating layer 1 by, for example, laser processing, and the via holes are filled with via conductors 4 for achieving interlayer conduction. The via hole 3 may have a diameter of about 20 to 100 μm, for example. The inside of the via hole 3 is covered with the via conductor 4 integrally formed with the wiring conductor 2 .

The wiring conductor 2 is formed of, for example, a highly conductive material such as electroless plating or electrolytic plating. A part of the uppermost wiring conductor 2 forms a semiconductor element connection pad 5 . Electrodes of semiconductor elements such as semiconductor integrated circuit elements are connected to the semiconductor element connection pads 5 . A part of the wiring conductor 2 formed in the lowermost layer forms a circuit board connection pad 6 . The electrodes of the circuit board on which the wiring board A is mounted are connected to the circuit board connection pads 6 . Furthermore, the semiconductor element operates by transmitting electrical signals between the semiconductor element and the circuit board via the wiring conductor 2 . As shown in FIG. 2 , the uppermost wiring conductor 2 is buried in the insulating layer 1 so that the top surface is exposed on the surface of the insulating layer 1 . Furthermore, the portion buried in the insulating layer 1 is provided with a wiring slope portion 2a having a width wider than that of the top surface.

In this manner, according to the wiring board of the present disclosure, the wiring slope portion 2 a having a width wider than that of the top surface is embedded in the insulating layer 1 . Accordingly, even if the wiring conductor 2 is miniaturized, the adhesion strength of the wiring conductor 2 is hardly reduced, and the wiring conductor 2 can be prevented from peeling off from the insulating layer 1 . As a result, since electric signals can be favorably transmitted only by the wiring conductor 2, a wiring board in which semiconductor elements can stably operate can be provided.

Next, one embodiment of a method of manufacturing a wiring board according to the present disclosure will be described based on FIGS. 3 to 6 . In addition, the same code|symbol is attached|subjected to the same part as FIG. 1, and detailed description is abbreviate|omitted.

As shown in FIG. 3A , a prepreg 7 , two adhesive films 8 , and two separable metal foils 9 are prepared. The prepreg 7 is used to form a support substrate 10 for supporting the wiring substrate A in the process of being manufactured while maintaining a required flatness when the substrate A is manufactured. The prepreg 7 has a product-forming region X in the center and a spare region Y in the outer periphery.

The region X for product formation is a quadrangular region, and the wiring board A is formed on the region X for product formation. In this embodiment, only the product forming region X corresponding to one wiring board A is shown for simplicity. Actually, the product formation region has an area corresponding to several tens to several thousands of wiring substrates A. FIG. The surplus discarding area Y is a rectangular frame-shaped area surrounding the area X for product formation. The prepreg 7 has a substantially square shape, may have a thickness of approximately 0.1 to 0.2 mm, and may have a length of approximately 400 to 900 mm in length and width. The prepreg 7 has a plate shape in a semi-cured state by impregnating glass fibers with a thermosetting resin such as epoxy resin, for example.

The adhesive film 8 is inserted between the prepreg 7 and the separable metal foil 9 to bond the cured prepreg 7 and the separable metal foil 9 . The adhesive film 8 may have a thickness of approximately 24 to 50 μm, and may have a length of approximately 400 to 900 mm in length and width. The adhesive film 8 is formed of, for example, a heat-resistant film such as epoxy resin or polyimide resin.

The separable metal foil 9 includes a first metal foil 9a and a second metal foil 9b. The 1st metal foil 9a and the 2nd metal foil 9b are hold|maintained by the adhesive force so small that it can separate|separate through the adhesive layer (not shown). The 1st metal foil 9a has a dimension larger than the area|region X for product formation, and smaller than the 2nd metal foil 9b. The first metal foil 9 a may have a thickness of about 15 to 20 μm. The second metal foil 9 b has dimensions smaller than the prepreg 7 in length and width by about 5 mm. The first metal foil 9a may have a thickness of approximately 5 to 9 μm.

The separable metal foil 9 contains copper etc., for example. The adhesive layer may be formed of a heat-resistant adhesive material such as silicone resin or acrylic resin or a nickel-based metal layer in consideration of withstanding the heat load applied during the formation of the wiring board A. Such an adhesive layer may have a thickness of 1 to 9 N considering that the first metal foil 9 a and the second metal foil 9 b are separated from each other without peeling residue when the later-described buildup (buildup) portion 12 is separated from the support substrate 10 . /m degree of small adhesive force.

Next, as shown in FIG. 3B , the separable metal foil 9 is placed on the center of the upper and lower surfaces of the prepreg 7 via the adhesive film 8 so that the first metal foil 9 a faces the prepreg 7 side. The laminate shown in FIG. 3B was heated while being pressed from above and below. By applying pressure and heating in this way, as shown in FIG. 3C , support substrate 10 to which detachable metal foil 9 is fixedly bonded is formed on the upper and lower surfaces of cured prepreg 7 . Next, as shown in FIG. 3D , conductor layers 11 (underlying metal layers) are formed on both main surfaces of support substrate 10 including separable metal foil 9 . Conductive layer 11 can be formed by, for example, a known plating method, and has a thickness of approximately 0.01 to 0.1 μm.

As shown in FIG. 4E , the surface of the conductor layer 11 is coated with a plating resist R having a plurality of opening patterns P corresponding to the wiring patterns. The opening pattern P has an opening slope portion Pa whose width becomes narrower toward the conductor layer 11 side. Plating resist R is formed as follows, for example. First, a resin sheet or resin paste made of photosensitive resin is coated or applied on the surface of the conductor layer 11 . Next, the photosensitive resin is exposed through a mask that partially shields the portion corresponding to the opening pattern P from light. Next, the photosensitive resin is developed to remove the non-exposed portion, whereby the plating resist R having the opening pattern P is formed.

For example, the opening slope Pa is formed by flattening the surface of the conductor layer 11 . The conductor layer 11 may have a surface roughness (Ra) of 60 nm or less. By making the surface of the conductor layer 11 flat, incident light at the time of exposure that reaches the surface of the conductor layer 11 is not blocked by the protrusions on the surface of the conductor layer 11 . As a result, the light at the time of exposure enters the wiring pattern region, whereby the photosensitive resin in the vicinity of the conductor layer 11 is cured to form the opening inclined portion Pa.

As shown in FIG. 4F , the opening pattern P is filled with the plating metal layer 2P for wiring conductors having the wiring slope portion 2 a corresponding to the opening slope portion Pa. For example, a conductive pattern formed by electroless copper plating or electrolytic copper plating is applied to the surface of the conductor layer 11 by a known semi-additive method, thereby forming the plated metal layer 2P. Next, as shown in FIG. 4G , by removing the plating resist R, the side surface of the wiring inclined portion 2 a including the plating metal layer 2P is exposed.

As shown in FIG. 4H , the insulating layer 1 is laminated so as to cover the conductive layer 11 and the plated metal layer 2P. At this time, the insulating layer 1 enters between the conductive layer 11 and the inclined wiring portion 2a, and embeds the inclined wiring portion 2a. Next, as shown in FIG. 4I , via hole 3 having metal plating layer 2P as a bottom surface is formed in insulating layer 1 . Next, as shown in FIG. 5J , via conductor 4 is formed in via hole 3 , and wiring conductor 2 is formed on the surface of insulating layer 1 . Next, as shown in FIG. 5K , the insulating layer 1 and the wiring conductor 2 of the next layer are stacked in multiple layers in the same manner, thereby forming the build-up portion 12 for the wiring board.

The insulating layer 1 is formed of a thermosetting resin such as epoxy resin or bismaleimide triazine resin as described above. The insulating layer 1 is formed, for example, as follows. First, an inorganic insulating filler is dispersed in an uncured epoxy resin or bismaleimide triazine resin composition to form a thin film. The insulating layer 1 is formed by thermocompression bonding the formed thin film on the surface of the conductive layer 11 on both main surfaces of the supporting substrate 10 or the surface of the lower insulating layer 1 in a vacuum state. A plurality of via holes 3 are formed in the insulating layer 1 by, for example, laser processing, and the via holes are filled with via conductors 4 for achieving interlayer conduction.

As shown in FIG. 5L, by cutting the support substrate 10, the conductor layer 11, and the buildup portion 12 at the boundary between the product formation region X and the surplus discard region Y, the support substrate 10, the product formation region X, and the region X are cut out. The conductor layer 11 and the buildup part 12 . For cutting, for example, a dicing device may be used.

Next, as shown in FIG. 6M , the conductor layer 11 and the build-up portion 12 are separated from the first metal foil 9 a. Thereby, the laminated body 13 for wiring boards which fixedly bonded the 2nd metal foil 9b to the one surface of the conductor layer 11 is formed. The second metal foil 9 is held on the first metal foil 9a with an adhesive force so small that separation is possible via an adhesive layer. Thereby, it becomes possible to separate easily without damaging the laminated body 13 just by opening between the 1st metal foil 9a and the 2nd metal foil 9b.

Next, as shown in FIG. 6N, the second metal foil 9b is etched away. Finally, as shown in FIG. 6O, the conductor layer 11 is completely etched away with an etchant. As a result, the plated metal layer 2P is exposed. In this way, as shown in FIG. 1 , a wiring board A having a wiring conductor 2 whose top surface is exposed from the insulating layer 1 and has a width wider than that of the top surface at a portion buried in the insulating layer 1 is formed. Wiring inclined portion 2a.

As described above, according to the manufacturing method of the wiring board according to the present disclosure, the wiring conductor 2 is formed, the top surface of which is exposed from the insulating layer 1, and the part embedded in the insulating layer 1 is provided with a wiring wider than the width of the top surface. Inclined portion 2a. In this way, the inclined wiring portion 2 a having a width wider than that of the top surface is buried in the insulating layer 1 . Accordingly, even if the wiring conductor 2 is miniaturized, the adhesion strength of the wiring conductor 2 is hardly reduced, and the wiring conductor 2 can be prevented from peeling off from the insulating layer 1 . As a result, since electrical signals can be favorably transmitted through the wiring conductor 2, it is possible to provide a wiring board in which a semiconductor element can stably operate.

The wiring board and the manufacturing method of the wiring board of the present disclosure are not limited to the above-mentioned one embodiment, and various changes can be made as long as they do not depart from the gist of the invention.

For example, in the wiring board according to the above-mentioned one embodiment, the wiring conductor 2 has the wiring slope portion 2a having a width wider than that of the top surface. However, as shown in FIG. 7, the wiring conductor 2 may have the wiring step part 2b wider than the top surface width. In the wiring board according to the above-mentioned one embodiment, the surface of the outermost insulating layer is not covered with a solder resist layer. However, it may also be covered with a solder resist layer.

For example, in the manufacturing method according to the above-mentioned one embodiment, as shown in FIG. 4 , the insulating layer 1 is coated after the plating resist R is removed. However, after removing the plating resist R, a step of etching the conductor layer 11 and the plating metal layer 2P may be added as shown in FIGS. 8 and 9 .

By performing such etching treatment, the surface of the conductor layer 11 and the surface of the plating metal layer 2P are gradually dissolved. On the other hand, in the wiring slope part 2a formed in the plating metal layer 2P, etchant stays, and a dissolution rate becomes faster compared with a part. As a result, the area occupied by the wiring slope portion 2 a in the plated metal layer 2P is enlarged compared to the case where the etching process is not performed. Thus, by enlarging the wiring slope part 2a embedded in the insulating layer 1, the adhesion strength of the wiring conductor 2 can be further improved.

Claims (6)

1. A wiring substrate, characterized in that, A wiring conductor is buried on the surface of the insulating layer so that the top surface is exposed, and the wiring conductor has a wiring step portion or a wiring slope portion having a width wider than that of the top surface at a portion embedded in the insulating layer. 2. The wiring substrate according to claim 1, wherein, The insulating layer has a multi-layer structure, and a wiring conductor is buried so that the top surface is exposed at least on the surface of the insulating layer formed on the outermost layer, and a portion buried in the insulating layer has a width wider than the top surface. The width of the wiring step or wiring slope. 3. A method of manufacturing a wiring board, characterized in that, Forming a plating resist layer having an opening pattern on the base metal layer, the opening pattern having an opening step portion or an opening slope portion narrowed toward the base metal layer side, Filling the opening pattern with a wiring conductor plating layer having a wiring step or wiring slope corresponding to the opening step or opening slope, removing the plating resist layer, forming an insulating layer that completely embeds the plated metal layer on the base metal layer and the plated metal layer, and etching away the base metal layer, forming a wiring conductor whose top surface is exposed from the insulating layer and includes the wiring step portion or the wiring slope portion having a width wider than that of the top surface at a portion buried in the insulating layer; Plated metal layer. 4. The method of manufacturing a wiring board according to claim 3, wherein, The base metal layer has a flat surface. 5. The method of manufacturing a wiring board according to claim 4, wherein, A surface of the base metal layer has a surface roughness of 60 nm or less. 6. The method of manufacturing a wiring board according to claim 3, wherein, After the plating resist layer is removed, the plating metal layer and the base metal layer are further etched.