[go: up one dir, main page]

CN106449692A - Hall integrated device and preparation method thereof - Google Patents

Hall integrated device and preparation method thereof Download PDF

Info

Publication number
CN106449692A
CN106449692A CN201610736909.2A CN201610736909A CN106449692A CN 106449692 A CN106449692 A CN 106449692A CN 201610736909 A CN201610736909 A CN 201610736909A CN 106449692 A CN106449692 A CN 106449692A
Authority
CN
China
Prior art keywords
hall
collecting zone
electrode
hall element
signal amplification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610736909.2A
Other languages
Chinese (zh)
Other versions
CN106449692B (en
Inventor
胡双元
朱忻
黄勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SUZHOU MATRIX OPTICAL Co Ltd
Original Assignee
SUZHOU MATRIX OPTICAL Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SUZHOU MATRIX OPTICAL Co Ltd filed Critical SUZHOU MATRIX OPTICAL Co Ltd
Priority to CN201610736909.2A priority Critical patent/CN106449692B/en
Publication of CN106449692A publication Critical patent/CN106449692A/en
Application granted granted Critical
Publication of CN106449692B publication Critical patent/CN106449692B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B61/00Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00Hall-effect devices
    • H10N52/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00Hall-effect devices
    • H10N52/101Semiconductor Hall-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The invention belongs to the technical field of sensing, and discloses a Hall integrated device. The Hall integrated device comprises a compound semiconductor Hall element and a signal amplifying element formed above the Hall element, wherein the signal amplifying element is used for signal amplification of the Hall element; and the signal amplifying element is a compound semiconductor homojunction transistor or a compound semiconductor heterojunction transistor. The signal amplifying element is arranged above the Hall element, the integration level is high, the influence of substrate type on the signal amplifying element is avoided, the applicable type range of the Hall element is wide, and the manufacturing cost is effectively reduced. The invention also discloses a preparation method of the Hall integrated device, and the preparation method is mature in technology and low in preparation cost.

Description

A kind of Hall integrator part and preparation method thereof
Technical field
The present invention relates to sensory field is and in particular to a kind of compound semiconductor linear Hall integrated device and its preparation side Method.
Background technology
Hall element is a kind of Magnetic Sensor based on Hall effect, is generally used for detecting magnetic field and its change.Hall unit The sensitivity of part is closely related with the mobility of material.In order to lift the sensitivity of Hall element further, people adopt chemical combination Thing semiconductor substituted for silicon, obtains high sensitivity, high linearity and the high compound semiconductor Hall element of temperature stability.
At present, conventional compound semiconductor Hall element includes GaAs Hall element, indium arsenide Hall element, antimony Indium Hall element etc., has wide market.
However, the signal of Hall element output itself is weaker, in actual applications, need to mate with rear end amplifying circuit to make With.In order to reduce the size of Hall element product, it is developed the structure together with silicon amplifier package by Hall element. But this mode is relatively complicated, technique does not have compatibility, and because bi-material has different temperature, pressure characteristic Deng, in use, existence and stability and integrity problem.
At present it has been reported that Hall element be mainly with silicon amplifier integration mode:Using ion implantation technology, in arsenic Change and form Hall element functional areas and field-effect transistor functional areas on gallium substrate, signal is carried out by field-effect transistor and puts Greatly.However, this mode has problems in that, it is only used for manufacturing GaAs Hall device product, if be manufactured similarly to Indium arsenide hall device product, substrate need to be replaced with indium arsenide, then cannot manufacture field-effect transistor.
Content of the invention
For this reason, to be solved by this invention is the problem that existing Hall integrator part product is single, preparation cost is high.
For solving above-mentioned technical problem, the technical solution used in the present invention is as follows:
The present invention provides a kind of Hall integrator part, including compound semiconductor Hall element and be formed at described Hall Signal amplification component above element, the signal for described Hall element amplifies;
Described signal amplification component is compound semiconductor homogeneity junction transistors or compound semiconductor heterojunction transistor.
Alternatively, described signal amplification component is heterojunction transistor.
Alternatively, described Hall element includes substrate, functional layer and the first electrode being stacked.
Alternatively, described heterojunction transistor includes being stacked sub- collecting zone, collecting zone, base, launch site, contact Layer and second electrode, and it is respectively formed at the 3rd electrode on described Asia collecting zone and described collecting zone and the 4th electrode.
Alternatively, described base area is less than described collecting zone area, and described 4th electrode is formed directly into described current collection On the platform that area is formed with described base;Described collecting zone area is less than described Asia collecting zone area, and described 3rd electrode is direct It is formed on the platform that described collecting zone is formed with described Asia collecting zone.
Alternatively, projected area on described Hall element for the described signal amplification component is close less than described Hall element The surface area of described signal amplification component, described first electrode is formed directly into described signal amplification component and described Hall unit On the platform that part is formed;
Also include the corrosion barrier layer being formed between described Hall element and described signal amplification component.
Alternatively, also include the lattice graded bedding that is formed between described functional layer and described corrosion barrier layer.
Alternatively, described Hall element is in GaAs Hall element, indium arsenide Hall element or indium antimonide Hall unit One kind.
The present invention also provides the preparation method of described Hall integrator part, comprises the steps:
Form the compound structure in Hall element and signal amplification component;
Form electrode structure.
Alternatively, the described compound structure step being formed in Hall element and signal amplification component includes:
Stacked functional layer, sub- collecting zone, collecting zone, base, launch site, contact layer are sequentially formed on substrate;
Described Asia collecting zone, described collecting zone, described base, described launch site, described contact layer are patterned, shape Become epitaxial structure pattern;
Described formation electrode structure step includes:
Described functional layer forms first electrode, second electrode is formed on described contact layer, in described Asia collecting zone With the 3rd electrode and the 4th electrode are formed respectively on described collecting zone.
The technique scheme of the present invention has advantages below compared to existing technology:
1st, a kind of Hall integrator part described in the embodiment of the present invention, including compound semiconductor Hall element and formation Signal amplification component above described Hall element, the signal for described Hall element amplifies;Described signal amplification component For compound semiconductor homogeneity junction transistors or compound semiconductor heterojunction transistor.Signal amplification component is arranged on Hall unit Above part, not only integrated level is high, sense in small space, detect beneficial to Hall integrator part, and avoids substrate species Impact to signal amplification component, applicable Hall element category is wide, effectively reduces manufacturing cost.
2nd, preparation method, technical maturity and the processing compatibility of a kind of Hall integrator part described in the embodiment of the present invention Height, preparation cost is low, and product yield is high.
Brief description
In order that present disclosure is more likely to be clearly understood, specific embodiment below according to the present invention simultaneously combines Accompanying drawing, the present invention is further detailed explanation, wherein
Fig. 1 is the Hall integrator part structural representation described in the embodiment of the present invention;
Fig. 2 is the Hall integrator part epitaxial structure schematic diagram described in the embodiment of the present invention;
In figure reference is expressed as:1- substrate, 2- functional layer, 3- corrosion barrier layer, 4- Asia collecting zone, 5- collecting zone, 6- base, 7- launch site, 8- contact layer, 91- first electrode, 92- second electrode, 93- the 3rd electrode, 94- the 4th electrode.
Specific embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, below in conjunction with the reality to the present invention for the accompanying drawing The mode of applying is described in further detail.
The present invention can be embodied in many different forms, and should not be construed as limited to embodiment set forth herein. On the contrary, provide these embodiments so that the disclosure will be thorough and complete, and the design of the present invention will be fully conveyed to Those skilled in the art, the present invention will only be defined by the appended claims.In the accompanying drawings, for clarity, Ceng He area can be exaggerated The size in domain and relative size.It should be appreciated that when element such as layer, region or substrate are referred to as " being formed at " or " setting " another element " on " when, this element can be arranged directly on described another element, or can also there is intermediary element. On the contrary, when element is referred to as on " being formed directly into " or " being set directly at " another element, there is not intermediary element.
Embodiment 1
The present embodiment provides a kind of Hall integrator part, as shown in figure 1, including compound semiconductor Hall element and shape Become the signal amplification component above Hall element, the signal for Hall element amplifies;Also include being formed at Hall element and Corrosion barrier layer 3 between signal amplification component;Signal amplification component is compound semiconductor homogeneity junction transistors or compound Heterogeneous semiconductor junction transistors.
As one embodiment of the present of invention, in the present embodiment, signal amplification component is the heterogeneous crystallization of compound semiconductor Body pipe;Sub- collecting zone 4 that heterojunction transistor includes being stacked, collecting zone 5, base 6, launch site 7, contact layer 8 and second Electrode 92, and it is respectively formed at the 3rd electrode 93 on sub- collecting zone 4 and collecting zone 5 and the 4th electrode 94.
Specifically, sub- collecting zone 4 is gallium arsenide layer, and thickness is 500nm;Collecting zone 5 is gallium arsenide layer, and thickness is 500nm; Base 6 is gallium arsenide layer, and thickness is 90nm;Launch site 7 is indium gallium phosphorous layer, and thickness is 50nm;Contact layer 8 is gallium arsenide layer, thick Spend for 300nm;3rd electrode 93, the 4th electrode 94 are Mo electrode.
Base 6 area is less than collecting zone 5 area, and the 4th electrode 94 is formed directly into the platform that collecting zone 5 is formed with base 6 On;Collecting zone 5 area is less than sub- collecting zone 4 area, and the 3rd electrode 93 is formed directly into collecting zone 5 and sub- collecting zone 4 formation On platform.
As the convertible embodiment of the present invention, signal amplification component can also be the heterogeneous crystallization of other compound semiconductors The compound semiconductor homogeneity junction transistors such as body pipe, thin film field-effect pipe (TFT), all can realize the purpose of the present invention, belong to Protection scope of the present invention.
As one embodiment of the present of invention, in the present embodiment, Hall element includes substrate 1, the functional layer 2 being stacked With first electrode 91.Projected area on Hall element for the signal amplification component is less than Hall element near signal amplification component Surface area, first electrode 91 is formed directly on the platform that signal amplification component is formed with Hall element.
Specifically, substrate 1 is gallium arsenide substrate, and functional layer 2 is gallium arsenide layer, and thickness is 1 μm.
As the convertible embodiment of the present invention, Hall element can be GaAs Hall element, indium arsenide Hall element One of or indium antimonide Hall unit, all can realize the purpose of the present invention, belong to protection scope of the present invention.
In the present embodiment, signal amplification component is arranged on above Hall element, and not only integrated level is high, be beneficial to Hall integrator Part senses in small space, detects, and avoids the impact to signal amplification component for the substrate species, applicable Hall element Category is wide, effectively reduces manufacturing cost.Meanwhile, it is processed using same material, physicochemical properties are identical or phase Seemingly, stability and the reliability of device can be effectively improved.
The preparation method of above-mentioned Hall integrator part, as shown in Fig. 2 comprise the steps:
S1, sequentially form stacked functional layer 2, corrosion barrier layer 3, sub- collecting zone 4, collecting zone 5, base on substrate 1 6th, launch site 7, contact layer 8.
The preparation method of functional layer 2 is:With arsine (AsH3) for arsenic source, trimethyl gallium (TMGa) be gallium source, silane (SiH4) For doped source, hydrogen (H2) it is carrier gas, growth temperature is 650 DEG C, and pressure is 100mbar, and V/III ratio is 100, is grown.
The preparation method of corrosion barrier layer 3 is with phosphine (PH3) for phosphorus source, trimethyl indium (TMIn) be indium source, trimethyl Gallium (TMGa) is gallium source, hydrogen (H2) it is carrier gas, growth temperature is 650 DEG C, and pressure is 100mbar, and V/III ratio is 100, carries out Growth obtains indium gallium phosphorous layer.Corrosion barrier layer 3 is capable of each functional layer (Asia of Hall element functional layer 2 and signal amplification component Collecting zone 4 etc.) separate, when signal amplification component is carried out with technique preparation, corrosion barrier layer 3 can be with effective protection Hall element Functional layer 2, after the completion of signal amplification component technique, removes corrosion barrier layer, then the functional layer 2 of Hall element is carried out adding Work is it is ensured that signal amplification component preparation technology and Hall element preparation technology are mutually unaffected.
The preparation method of sub- collecting zone 4 is:With arsine (AsH3) for arsenic source, trimethyl gallium (TMGa) be gallium source, silane (SiH4) it is doped source, hydrogen (H2) it is carrier gas, growth temperature is 650 DEG C, and pressure is 100mbar, and V/III ratio is 100, carries out Growth.
The preparation method of collecting zone 5 is:With arsine (AsH3) for arsenic source, trimethyl gallium (TMGa) be gallium source, silane (SiH4) For doped source, hydrogen (H2) it is carrier gas, growth temperature is 650 DEG C, and pressure is 100mbar, and V/III ratio is 100, is grown.
The preparation method of base 6 is:With arsine (AsH3) for arsenic source, trimethyl gallium (TMGa) be gallium source, carbon tetrabromide (CBr4) it is doped source, hydrogen (H2) it is carrier gas, growth temperature is 650 DEG C, and pressure is 100mbar, and V/III ratio is 100, carries out Growth.
The preparation method of launch site 7 is:With phosphine (PH3) for phosphorus source, trimethyl indium (TMIn) be indium source, trimethyl gallium (TMGa) it is gallium source, silane (SiH4) is doped source, hydrogen (H2) it is carrier gas, growth temperature is 650 DEG C, and pressure is 100mbar, V/III ratio is 100, is grown.
The preparation method of contact layer 8 is:With arsine (AsH3) for arsenic source, trimethyl gallium (TMGa) be gallium source, silane (SiH4) For doped source, hydrogen (H2) it is carrier gas, growth temperature is 650 DEG C, and pressure is 100mbar, and V/III ratio is 100, is grown.
S2, by photoetching and etching technics, base 6, launch site 7, contact layer 8 are patterned, form collecting zone 5 flat Platform;
By photoetching and etching technics, sub- collecting zone 4, collecting zone 5 are patterned, form collecting zone 5 platform;
By selective corrosion, removing corrosion barrier layer 3, forming functional layer 2 platform, thus forming epitaxial structure pattern.
S3, in functional layer 2 formed first electrode 91, on contact layer 8 formed second electrode 92, in sub- collecting zone 4 He 3rd electrode 93 and the 4th electrode 94 are formed respectively on collecting zone 5.
The preparation method of above-mentioned Hall integrator part, also includes:
S4, connection chip internal circuits;
S5, thinning, scribing is carried out to substrate 1, pin is pulled out by gold thread routing;Carry out chip package.
All compared with technology, the present embodiment repeats no more step S4, S5.
The preparation method of above-mentioned Hall integrator part, technical maturity and same material processing compatibility are high, and preparation cost is low, Product yield is high.
Embodiment 2
The present embodiment provides a kind of Hall integrator part, its structure and preparation method with embodiment 1, except for the difference that:Function Layer 2 is indium arsenide layer, thickness 500nm.It is additionally provided with lattice graded bedding between functional layer 2 and corrosion barrier layer 3.
There is mismatch in the lattice due to indium arsenide and GaAs and its base material indium gallium phosphorous layer, if directly raw on indium arsenide Gallium arsenide layer in long signal amplification component or indium gallium phosphorous layer, then device performance meeting be greatly affected because of lattice mismatch, therefore, Add lattice graded bedding in the present embodiment, so that the lattice paprmeter of material is matched each other, effectively increase the sensitivity of device.
Obviously, above-described embodiment is only intended to clearly illustrate example, and the not restriction to embodiment.Right For those of ordinary skill in the art, can also make on the basis of the above description other multi-forms change or Change.There is no need to be exhaustive to all of embodiment.And the obvious change thus extended out or Change among still in protection scope of the present invention.

Claims (10)

1. a kind of Hall integrator part is it is characterised in that including compound semiconductor Hall element and being formed at described Hall Signal amplification component above element, the signal for described Hall element amplifies;
Described signal amplification component is compound semiconductor homogeneity junction transistors or compound semiconductor heterojunction transistor.
2. Hall integrator part according to claim 1 is it is characterised in that described signal amplification component is heterogeneous crystalline solid Pipe.
3. Hall integrator part according to claim 1 and 2 is it is characterised in that described Hall element includes being stacked Substrate, functional layer and first electrode.
4. the Hall integrator part according to Claims 2 or 3 is it is characterised in that described heterojunction transistor includes being laminated The sub- collecting zone of setting, collecting zone, base, launch site, contact layer and second electrode, and it is respectively formed at described Asia collecting zone With the 3rd electrode on described collecting zone and the 4th electrode.
5. Hall integrator part according to claim 4 is it is characterised in that described base area is less than described collecting zone face Long-pending, described 4th electrode is formed directly on the platform that described collecting zone is formed with described base;
Described collecting zone area be less than described Asia collecting zone area, described 3rd electrode be formed directly into described collecting zone with described On the platform that sub- collecting zone is formed.
6. the Hall integrator part according to any one of claim 1-5 is it is characterised in that described signal amplification component is in institute State projected area on Hall element and be less than the surface area near described signal amplification component for the described Hall element, described first Electrode is formed directly on the platform that described signal amplification component is formed with described Hall element;
Also include the corrosion barrier layer being formed between described Hall element and described signal amplification component.
7. Hall integrator part according to claim 6 it is characterised in that also include be formed at described functional layer with described Lattice graded bedding between corrosion barrier layer.
8. the Hall integrator part according to any one of claim 1-7 is it is characterised in that described Hall element is GaAs One of Hall element, indium arsenide Hall element or indium antimonide Hall unit.
9. a kind of preparation method of the Hall integrator part described in any one of claim 1-8 is it is characterised in that include following walking Suddenly:
Form the compound structure in Hall element and signal amplification component;
Form electrode structure.
10. Hall integrator part according to claim 9 is it is characterised in that described formation Hall element and signal amplify Compound structure step in element includes:
Stacked functional layer, sub- collecting zone, collecting zone, base, launch site, contact layer are sequentially formed on substrate;
Described Asia collecting zone, described collecting zone, described base, described launch site, described contact layer are patterned, is formed outer Prolong structure plan;
Described formation electrode structure step includes:
Described functional layer forms first electrode, second electrode is formed on described contact layer, in described Asia collecting zone and institute State and the 3rd electrode and the 4th electrode are formed respectively on collecting zone.
CN201610736909.2A 2016-08-26 2016-08-26 A kind of Hall integrator part and preparation method thereof Active CN106449692B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610736909.2A CN106449692B (en) 2016-08-26 2016-08-26 A kind of Hall integrator part and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610736909.2A CN106449692B (en) 2016-08-26 2016-08-26 A kind of Hall integrator part and preparation method thereof

Publications (2)

Publication Number Publication Date
CN106449692A true CN106449692A (en) 2017-02-22
CN106449692B CN106449692B (en) 2018-09-11

Family

ID=58182199

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610736909.2A Active CN106449692B (en) 2016-08-26 2016-08-26 A kind of Hall integrator part and preparation method thereof

Country Status (1)

Country Link
CN (1) CN106449692B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109301062A (en) * 2018-10-12 2019-02-01 苏州矩阵光电有限公司 A kind of hall device and preparation method thereof of integrated amplifier part
CN117594644A (en) * 2024-01-18 2024-02-23 常州承芯半导体有限公司 Semiconductor device and method of forming the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6903429B2 (en) * 2003-04-15 2005-06-07 Honeywell International, Inc. Magnetic sensor integrated with CMOS
CN102263121A (en) * 2011-07-19 2011-11-30 北京大学 Graphene-based Hall integrated circuit and its preparation method
CN103066098A (en) * 2012-12-26 2013-04-24 北京大学 Graphene Hoare integrated circuit and preparation method thereof
CN104035056A (en) * 2013-03-08 2014-09-10 美格纳半导体有限公司 Magnetic Sensor And Method Of Fabricating The Same
CN105355627A (en) * 2015-11-23 2016-02-24 中山德华芯片技术有限公司 Si-based GaN Bi-HEMT chip and preparation method thereof
CN105355779A (en) * 2015-12-02 2016-02-24 苏州矩阵光电有限公司 Hall element and preparation method
CN206134685U (en) * 2016-08-26 2017-04-26 苏州矩阵光电有限公司 Hall integrated device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6903429B2 (en) * 2003-04-15 2005-06-07 Honeywell International, Inc. Magnetic sensor integrated with CMOS
CN102263121A (en) * 2011-07-19 2011-11-30 北京大学 Graphene-based Hall integrated circuit and its preparation method
CN103066098A (en) * 2012-12-26 2013-04-24 北京大学 Graphene Hoare integrated circuit and preparation method thereof
CN104035056A (en) * 2013-03-08 2014-09-10 美格纳半导体有限公司 Magnetic Sensor And Method Of Fabricating The Same
CN105355627A (en) * 2015-11-23 2016-02-24 中山德华芯片技术有限公司 Si-based GaN Bi-HEMT chip and preparation method thereof
CN105355779A (en) * 2015-12-02 2016-02-24 苏州矩阵光电有限公司 Hall element and preparation method
CN206134685U (en) * 2016-08-26 2017-04-26 苏州矩阵光电有限公司 Hall integrated device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109301062A (en) * 2018-10-12 2019-02-01 苏州矩阵光电有限公司 A kind of hall device and preparation method thereof of integrated amplifier part
CN109301062B (en) * 2018-10-12 2024-04-16 苏州矩阵光电有限公司 Hall device integrated with amplifying device and preparation method thereof
CN117594644A (en) * 2024-01-18 2024-02-23 常州承芯半导体有限公司 Semiconductor device and method of forming the same
CN117594644B (en) * 2024-01-18 2024-05-28 常州承芯半导体有限公司 Semiconductor device and method for forming the same

Also Published As

Publication number Publication date
CN106449692B (en) 2018-09-11

Similar Documents

Publication Publication Date Title
JP2522214B2 (en) Semiconductor device and manufacturing method thereof
US9673294B2 (en) Bipolar transistor structure and a method of manufacturing a bipolar transistor structure
US9887139B2 (en) Integrated heterojunction semiconductor device and method for producing an integrated heterojunction semiconductor device
CN105374861A (en) Heterojunction bipolar transistor with barrier layer structure
CN106449692A (en) Hall integrated device and preparation method thereof
CN206134685U (en) Hall integrated device
CN108519174B (en) GaN bridge type absolute pressure sensor and manufacturing method thereof
CN208422914U (en) Thermal-shutdown circuit
CN101459130A (en) Parasitic vertical PNP and manufacturing process thereof in BiCMOS process
CN106328802B (en) A piezoelectric bipolar transistor
WO2012120871A1 (en) Semiconductor substrate, semiconductor device, and method for manufacturing semiconductor substrate
US20130134562A1 (en) Semiconductor device and method for fabricating semiconductor buried layer
TWI523219B (en) Compound semiconductor lateral PNP bipolar transistor
JPS6095966A (en) Hetero-junction bipolar transistor and manufacture thereof
CN105405913A (en) Low dark current InGaAs detector and preparation method thereof
JP3128808B2 (en) Semiconductor device
CN100395883C (en) CMOS image sensing device and method using independent source formation
JP2564856B2 (en) Semiconductor device
KR101475732B1 (en) Silicon nanowire device
CN106653826B (en) A kind of compound semiconductor heterojunction bipolar transistor
CN112397637A (en) High-sensitivity Hall element and preparation method thereof
US6580139B1 (en) Monolithically integrated sensing device and method of manufacture
US11646348B2 (en) Double mesa heterojunction bipolar transistor
JPS63175463A (en) Bi-MOS integrated circuit manufacturing method
CN117174784A (en) Preparation method of on-chip integrated bias circuit photoelectric detector

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
PE01 Entry into force of the registration of the contract for pledge of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Hall integrated device and preparation method thereof

Effective date of registration: 20211029

Granted publication date: 20180911

Pledgee: Bank of China Limited Zhangjiagang branch

Pledgor: SUZHOU JUZHEN PHOTOELECTRIC Co.,Ltd.

Registration number: Y2021980011576

PC01 Cancellation of the registration of the contract for pledge of patent right
PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20221018

Granted publication date: 20180911

Pledgee: Bank of China Limited Zhangjiagang branch

Pledgor: SUZHOU JUZHEN PHOTOELECTRIC Co.,Ltd.

Registration number: Y2021980011576