CN106409796A - Array substrate, manufacturing method thereof, display device and manufacturing method thereof - Google Patents
Array substrate, manufacturing method thereof, display device and manufacturing method thereof Download PDFInfo
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- CN106409796A CN106409796A CN201610985205.9A CN201610985205A CN106409796A CN 106409796 A CN106409796 A CN 106409796A CN 201610985205 A CN201610985205 A CN 201610985205A CN 106409796 A CN106409796 A CN 106409796A
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- 239000000758 substrate Substances 0.000 title claims abstract description 102
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 48
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 17
- 230000008020 evaporation Effects 0.000 claims description 14
- 238000001704 evaporation Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000004205 dimethyl polysiloxane Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000002294 plasma sputter deposition Methods 0.000 description 2
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- -1 polydimethylsiloxane Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides an array substrate, a manufacturing method thereof, a display device and a manufacturing method thereof and belongs to the display technical field. The manufacturing method of the array substrate includes the following steps that: a substrate is provided; a plurality of through holes passing through the substrate are formed; electric conductive columns are formed in the through holes; and gate lines and data lines are formed on the first surface of the substrate, each of the gate lines and/or data lines is electrically connected with one electric conductive column. With the array substrate provided by the technical schemes of the invention adopted, a narrow-frame display device, an ultra-narrow frame display device or even a frameless display device can be realized.
Description
Technical field
The present invention relates to display technology field, particularly relate to a kind of array base palte and preparation method thereof, display device and its
Manufacture method.
Background technology
The narrow frame design of display device is a trend of display field development, if the frame of display device narrows,
Then spectators' bound degree of vision when watching this kind of display product substantially reduces, and vision is more loosened it is easier to make one to produce
A kind of appreciation aesthetic feeling on the spot in person.
And existing display device needs to arrange cabling and various integrated electricity component at the edge of display floater, therefore,
Display device remains a need for retaining the frame of one fixed width, is difficult to frame design is narrow.
Content of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and preparation method thereof, display device and its making
Method, is capable of narrow frame, ultra-narrow frame or even the Rimless of display device.
For solving above-mentioned technical problem, embodiments of the invention provide technical scheme as follows：
On the one hand, a kind of manufacture method of array base palte is provided, including：
One underlay substrate is provided；
Form the multiple vias running through described underlay substrate；
Form conductive pole in described via；
Grid line data line is formed on the first surface of underlay substrate, each data wire and/or each grid line respectively with
One conductive pole electrical connection.
Further, the described step forming conductive pole in described via includes：
Evaporation binding material and conductive material on the underlay substrate being formed with described via, described binding material and described
Conductive material sticks to described in the hole of crossing and forms described conductive pole.
Further, form the grid conductive layer figure of described conductive pole and array base palte by patterning processes, described
Grid conductive layer figure includes the gate electrode of thin film transistor (TFT) and described grid line, forms described conductive pole and described grid conductive layer figure
Step include：
Evaporation binding material and conductive material on the underlay substrate being formed with described via, the first of described underlay substrate
Towards evaporation source, described binding material and described conductive material stick to described in the hole of crossing and form described conductive pole, described on surface
Binding material and described conductive material stick to described first surface and form the first conductive layer；
Described first conductive layer coats photoresist, using mask plate, described photoresist is exposed, shape after development
Become photoresist reservation region and the non-reservation region of photoresist, described photoresist reservation region corresponds to described grid conductive layer figure；
Described first conductive layer is performed etching, removes the first conductive layer of the non-reservation region of photoresist；
The photoresist of stripping photoresist reservation region, forms described grid conductive layer figure.
Further, the described step forming conductive pole in described via includes：
Insulating barrier, adhesion layer, barrier layer and plating seed layer are sequentially formed on the inwall of described via, and by plating
Technique filler metal in described via, forms described conductive pole.
Further, after forming described conductive pole, described manufacture method also includes：
The conduction being connected with described conductive pole in the second surface formation opposite with described first surface of described array base palte
Lead.
Further, the step forming described conductive lead wire includes：
Evaporation binding material and conductive material on the underlay substrate being formed with described conductive pole, the of described underlay substrate
Towards evaporation source, described binding material and described conductive material stick to described second surface and form the second conductive layer on two surfaces；
Described second conductive layer coats photoresist, using mask plate, described photoresist is exposed, shape after development
Become photoresist reservation region and the non-reservation region of photoresist, the figure of the corresponding described conductive lead wire of described photoresist reservation region；
Described second conductive layer is performed etching, removes the second conductive layer of the non-reservation region of photoresist；
The photoresist of stripping photoresist reservation region, forms described conductive lead wire.
The embodiment of the present invention additionally provides a kind of array base palte, is made using manufacture method as above and obtains, described
Array base palte includes underlay substrate, and described underlay substrate includes the multiple vias running through described underlay substrate, shape in described via
Become to have conductive pole, the first surface of described underlay substrate form grid line data line, each data wire and/or grid line respectively with
One conductive pole electrical connection.
Further, described array base palte also includes：
It is arranged on the conductive lead wire on the second surface opposite with described first surface of described underlay substrate, described conduction
Lead is connected with described conductive pole.
The embodiment of the present invention additionally provides a kind of manufacture method of display device, including：
The array base palte as above second surface opposite with described first surface adheres at least one and drives electricity
Road, the drive circuit on described second surface is connected with described conductive pole by conductive lead wire.
The embodiment of the present invention additionally provides a kind of display device, is to make using manufacture method as above to obtain, institute
State the grid line of display device, data wire, be located at the first of underlay substrate by multiple pixel cells that grid line data line limits
Surface, at least one drive circuit of described display device is located at described underlay substrate second table opposite with described first surface
Face.
Embodiments of the invention have the advantages that：
In such scheme, multiple vias running through underlay substrate are formed on underlay substrate, form conductive pole crossing in the hole,
Grid line, data wire and pixel cell are formed on a surface of underlay substrate, grid line and/or data wire are connected with conductive pole,
So drive circuit can be adhered on another surface of underlay substrate, and by conductive lead wire and conductive pole realize drive circuit and
Connection between grid line, data wire, thus realizing drive signal is loaded in pixel cell, drives pixel cell to be shown
Show, due to the technical scheme is that, drive circuit and pixel cell be separately positioned on the different surfaces of underlay substrate,
Therefore, it is not necessary to reserve larger region to place drive circuit such that it is able to realize display device at the edge of viewing area
Narrow frame, ultra-narrow frame or even Rimless.
Brief description
Fig. 1 forms the schematic diagram of conductive pole and grid conductive layer figure for the embodiment of the present invention；
Fig. 2 forms the schematic diagram of conductive pole for the embodiment of the present invention；
Fig. 3 is the structural representation of embodiment of the present invention array base palte；
Fig. 4 is the schematic diagram of embodiment of the present invention array base palte second surface.
Reference
1 underlay substrate 2,20 via, 3 tack coat 4 conductive layer
5 photoresist 6 conductive pole 7,18 grid line 8 gate electrode
9 gate insulation layer, 10 active layer, 11 source electrode 12 drain electrode
13 pixel electrodes 14,15 conductive lead wire 16 source electrode drive circuit
17 gate driver circuit, 19 data wire 20 via
31 insulating barrier, 32 adhesion layer, 33 barrier layer, 34 plating seed layer 35 metal
Specific embodiment
For making embodiments of the invention technical problem to be solved, technical scheme and advantage clearer, below in conjunction with
Drawings and the specific embodiments are described in detail.
Embodiments of the invention are directed to display device in prior art to be needed to arrange cabling and each at the edge of display floater
Plant integrated electricity component, therefore, display device remains a need for retaining the frame of one fixed width, is difficult to frame design is narrow
Problem, provides a kind of array base palte and preparation method thereof, display device and preparation method thereof, is capable of the narrow side of display device
Frame, ultra-narrow frame or even Rimless.
Embodiment one
The present embodiment provides a kind of manufacture method of array base palte, including：
One underlay substrate is provided；
Form the multiple vias running through described underlay substrate；
Form conductive pole in described via；
Grid line data line is formed on the first surface of underlay substrate, each data wire and/or each grid line respectively with
One conductive pole electrical connection.
In the present embodiment, multiple vias running through underlay substrate are formed on underlay substrate, form conductive pole crossing in the hole,
Grid line, data wire and pixel cell are formed on a surface of underlay substrate, grid line and/or data wire are connected with conductive pole,
So drive circuit can be adhered on another surface of underlay substrate, and by conductive lead wire and conductive pole realize drive circuit and
Connection between grid line, data wire, thus realizing drive signal is loaded in pixel cell, drives pixel cell to be shown
Show, due to the technical scheme is that, drive circuit and pixel cell be separately positioned on the different surfaces of underlay substrate,
Therefore, it is not necessary to reserve larger region to place drive circuit such that it is able to realize display device at the edge of viewing area
Narrow frame, ultra-narrow frame or even Rimless.
Further, described formation runs through the step of multiple vias of described underlay substrate and includes：
Form the multiple mistakes running through described underlay substrate using UV photoetching, X-ray direct write, laser ablation or patterning processes
Hole.
In one specific embodiment, the described step forming conductive pole in described via includes：
Evaporation binding material and conductive material on the underlay substrate being formed with described via, described binding material and described
Conductive material sticks to described in the hole of crossing and forms described conductive pole.
When forming conductive pole, it is possible to use ion metal plasma sputtering filling runs through the via of underlay substrate,
Can fill, in the way of using coating, the via running through underlay substrate.For plasma sputtering filling it is impossible to realize metal unit
Being filled up completely with for via of element, in not filling completely via, can use for the hollow space not filled up
PDMS (polydimethylsiloxane) Polymer material is filled and to be guaranteed mechanical stability.
The grid conductive layer of described conductive pole and array base palte in preferred implementation, can be formed by patterning processes
Figure, described grid conductive layer figure includes the gate electrode of thin film transistor (TFT) and described grid line, as shown in figure 1, forming described conduction
Post and described grid conductive layer figure comprise the following steps：
A, offer one underlay substrate 1, form via 2, specifically, it is possible to use laser is in hundreds of um on underlay substrate 1
The through hole of a diameter of more than ten um to hundreds of um is got through on thick underlay substrate 1；
B, by the first surface of underlay substrate 1 towards evaporation source, on the first surface of underlay substrate 1 be deposited with binding material
And conductive material, described binding material and described conductive material stick to and form conductive pole 6, binding material and conduction in via 2
Material sticks to first surface and forms tack coat 3 and conductive layer 4, and tack coat 3 and conductive layer 4 form the first conductive layer, wherein viscous
Knot material can adopt chromium, and conductive material can adopt copper；
C, on the first conductive layer coat photoresist 5；
D, using mask plate, photoresist 5 is exposed, forms photoresist reservation region after development and photoresist does not retain
Region, described photoresist reservation region corresponds to grid conductive layer figure；
E, the first conductive layer is performed etching, remove the first conductive layer of the non-reservation region of photoresist, form grid conductive layer
Figure, can peel off remaining photoresist afterwards, and grid conductive layer figure includes grid line 7 and gate electrode 8.
Above-mentioned embodiment forms the first conductive layer while forming conductive pole, and by structure is carried out to the first conductive layer
Figure becomes the figure of grid conductive layer, so can simplify the Making programme of array base palte, reduces the production cost of array base palte.
In another specific embodiment, as shown in Fig. 2 the described step forming conductive pole in described via includes：
Insulating barrier 31, adhesion layer 32, barrier layer 33 and plating seed layer 34 are sequentially formed on the inwall of described via, and
By electroplating technology in described via filler metal 35, formed described conductive pole.
Further, after forming described conductive pole, described manufacture method also includes：
The conduction being connected with described conductive pole in the second surface formation opposite with described first surface of described array base palte
Lead, so when making display device, can be in the drive circuit that second surface adhesion is connected with conductive lead wire so that driving
Circuit is connected with conductive pole by conductive lead wire, and then is connected with grid line and/or data wire, drives pixel cell to be shown.
Further, the step forming described conductive lead wire includes：
Evaporation binding material and conductive material on the underlay substrate being formed with described conductive pole, the of described underlay substrate
Towards evaporation source, described binding material and described conductive material stick to described second surface and form the second conductive layer on two surfaces；
Described second conductive layer coats photoresist, using mask plate, described photoresist is exposed, shape after development
Become photoresist reservation region and the non-reservation region of photoresist, the figure of the corresponding described conductive lead wire of described photoresist reservation region；
Described second conductive layer is performed etching, removes the second conductive layer of the non-reservation region of photoresist；
The photoresist of stripping photoresist reservation region, forms described conductive lead wire.
Embodiment two
The present embodiment additionally provides a kind of array base palte, is made using the manufacture method as described in embodiment one and obtains, institute
State array base palte and include underlay substrate, described underlay substrate includes the multiple vias running through described underlay substrate, in described via
It is formed with conductive pole, the first surface of described underlay substrate forms grid line data line, each data wire and/or grid line are respectively
Electrically connect with a conductive pole.
In the present embodiment, multiple vias running through underlay substrate are formed on underlay substrate, form conductive pole crossing in the hole,
Grid line, data wire and pixel cell are formed on a surface of underlay substrate, grid line and/or data wire are connected with conductive pole,
So drive circuit can be adhered on another surface of underlay substrate, and by conductive lead wire and conductive pole realize drive circuit and
Connection between grid line, data wire, thus realizing drive signal is loaded in pixel cell, drives pixel cell to be shown
Show, due to the technical scheme is that, drive circuit and pixel cell be separately positioned on the different surfaces of underlay substrate,
Therefore, it is not necessary to reserve larger region to place drive circuit such that it is able to realize display device at the edge of viewing area
Narrow frame, ultra-narrow frame or even Rimless.
In preferred embodiment, orthographic projection on described underlay substrate for the described via falls into described grid line in described substrate base
In orthographic projection on plate, described grid line is directly connected to corresponding conductive pole；And/or
Described via falls into just throwing on described underlay substrate for the described data wire in the orthographic projection on described underlay substrate
In shadow, described data wire is directly connected to corresponding conductive pole, so may not necessarily arrange again connection grid line and/or data wire with
The connecting line of conductive pole, can simplify the structure of array base palte.
Further, described array base palte also includes：
It is arranged on the conductive lead wire on the second surface opposite with described first surface of described underlay substrate, described conduction
Lead is connected with described conductive pole, so when making display device, can be connected with conductive lead wire in second surface adhesion
Drive circuit is so that drive circuit is connected with conductive pole by conductive lead wire, and then is connected with grid line and/or data wire, drives
Pixel cell is shown.
Embodiment three
The present embodiment additionally provides a kind of manufacture method of display device, including：
Array base palte as described in embodiment two second surface opposite with described first surface adheres at least one
Drive circuit, the drive circuit on described second surface is connected with described conductive pole by conductive lead wire.
In the present embodiment, wherein one surface of underlay substrate forms grid line, data wire and pixel cell, in another table
Adhere to drive circuit on face, and the connection between drive circuit and grid line, data wire is realized by conductive lead wire and conductive pole, from
And realize drive signal is loaded in pixel cell, drive pixel cell to be shown, due to the technical scheme is that
Drive circuit and pixel cell are separately positioned on the different surfaces of underlay substrate, therefore, it is not necessary to the edge in viewing area
Reserve larger region to place drive circuit such that it is able to realize the narrow frame of display device, ultra-narrow frame or even Rimless.
Further, described drive circuit includes gate driver circuit and source electrode drive circuit, described conductive pole include with
The first conductive pole and the second conductive pole being connected with data wire that grid line connects, described manufacture method includes：
Gate driver circuit is adhered on described second surface, described gate driver circuit passes through conductive lead wire and described the
One conductive pole connects；And/or
Source electrode drive circuit is adhered on described second surface, described source electrode drive circuit passes through conductive lead wire and described the
Two conductive poles connect.
Example IV
The present embodiment additionally provides a kind of display device, is to make using the manufacture method as described in embodiment three to obtain,
The grid line of described display device, data wire, the multiple pixel cells being limited by grid line data line are located at the of underlay substrate
One surface, at least one drive circuit of described display device is located at described underlay substrate second opposite with described first surface
Surface.
In the present embodiment, wherein one surface of underlay substrate forms grid line, data wire and pixel cell, in another table
Adhere to drive circuit on face, and the connection between drive circuit and grid line, data wire is realized by conductive lead wire and conductive pole, from
And realize drive signal is loaded in pixel cell, drive pixel cell to be shown, due to the technical scheme is that
Drive circuit and pixel cell are separately positioned on the different surfaces of underlay substrate, therefore, it is not necessary to the edge in viewing area
Reserve larger region to place drive circuit such that it is able to realize the narrow frame of display device, ultra-narrow frame or even Rimless.
Further, described drive circuit includes gate driver circuit and source electrode drive circuit, described conductive pole include with
The first conductive pole and the second conductive pole being connected with data wire that grid line connects,
It is stained with gate driver circuit, described gate driver circuit passes through to lead on the described second surface of described underlay substrate
Electrical lead is connected with described first conductive pole；And/or
It is stained with source electrode drive circuit, described source electrode drive circuit passes through to lead on the described second surface of described underlay substrate
Electrical lead is connected with described second conductive pole.
Embodiment five
Below in conjunction with the accompanying drawings array base palte of the embodiment of the present invention and preparation method thereof is described in detail：
The manufacture method of the array base palte of the present embodiment specifically includes following steps：
Step 1, offer one underlay substrate 1, this underlay substrate 1 is hard substrate, can be quartz base plate or glass substrate；
Step 2, formation run through multiple vias of underlay substrate 1；
Specifically, can be formed using UV photoetching, X-ray direct write, laser ablation or patterning processes and run through underlay substrate 1
Multiple vias.Wherein, via can correspond to the grid line data line setting of array base palte to be formed, and certainly, via is acceptable
The correspondence source electrode of thin film transistor (TFT) to be formed and gate electrode are arranged, or via can correspond to array base palte to be formed
Grid line and source electrode setting.In the present embodiment, the orthographic projection on underlay substrate 1 of a part of via of formation falls into grid line in lining
In orthographic projection on substrate 1, another part via falls into data wire on underlay substrate 1 in the orthographic projection on underlay substrate 1
Orthographic projection in.
Step 3, cross in the hole formed conductive pole 6；
Specifically, insulating barrier, adhesion layer, barrier layer and plating seed layer can be sequentially formed on the inwall of via, and
By electroplating technology filler metal in the vias, form conductive pole 6.
Because underlay substrate typically adopts quartz base plate or glass substrate, quartz base plate or glass substrate and metal it
Between adhesive force poor, if directly forming the adhesion that conductive pole may result between conductive pole and via in the vias relatively
Difference, therefore, is initially formed insulating barrier on the inwall of via, and the adhesion between this insulating barrier and underlay substrate is preferable, afterwards
Form the preferable adhesion layer of adhesion strength on the insulating layer, then barrier layer is formed on adhesion layer, barrier layer can stop adhesion
Impurity in layer and insulating barrier, forms plating seed layer afterwards over the barrier layer, by electroplating technology filler metal in the vias,
Form conductive pole 6.
Step 4, grid line, data wire and multiple display unit are formed on the first surface through the underlay substrate of step 3；
It is by display unit taking liquid crystal display as a example, need to sequentially form on underlay substrate 1：Grid line, data wire,
The gate electrode 8 of thin film transistor (TFT), gate insulation layer 9, active layer 10, source electrode 11 and drain electrode 12, and pixel electrode 13, its
In, the source electrode 11 of thin film transistor (TFT) and drain electrode 12 are all connected with active layer 10, and drain electrode 12 is connected with pixel electrode 13, leakage
Between electrode 12 and pixel electrode 13 can between be separated with insulating barrier, as shown in figure 3, drain electrode 12 can also be straight with pixel electrode 13
Connect in succession.Grid line 7 is directly connected to corresponding conductive pole 6, and data wire (not shown) is directly connected to corresponding conductive pole 6.
Array base palte as shown in Figure 3 can be formed through above-mentioned steps 1-4.
After forming array base palte as shown in Figure 3, as shown in figure 4, display unit can not formed in array base palte
Another side surface form, by patterning processes, the conductive lead wire 14 and 15 that is connected with conductive pole 6.
When making display device, specifically, as shown in figure 4, do not form a side surface of display unit in array base palte
Attach source electrode drive circuit 16 and gate driver circuit 17, and this side surface in array base palte is formed by patterning processes and grid
Multiple conductive lead wires 15 that the corresponding conductive pole of line 18 connects, grid line 18 is connected with conductive pole by via 19, and and data wire
Multiple conductive lead wires 14 that 20 corresponding conductive poles connect, data wire 20 is connected with conductive pole by via 19, wherein source drive
Circuit 16 is connected with conductive lead wire 14, and gate driver circuit 17 is connected with conductive lead wire 15, and such gate driver circuit 17 exports
Gate drive signal be transferred to grid line 18 on another side surface of array base palte via conductive lead wire 15, conductive pole 6 and then pass
It is handed to gate electrode 7, the data signal of source electrode drive circuit 16 output is transferred to array base palte via conductive lead wire 14, conductive pole 6
The data wire 20 of another side surface and then be transferred to the source electrode 11 of thin film transistor (TFT), thus realize being loaded into drive signal aobvious
Show in unit, drive display unit to be shown.
Further, in addition to source electrode drive circuit and gate driver circuit, display device needs other electricity units using
Device such as printed circuit board (PCB) (PCB), flexible printed circuit board (FPC) etc. can be formed at array base palte and display unit phase
On one side surface of the back of the body.These electricity components and parts can be attached on the surface of array base palte it is also possible to by these electricity unit device
Part is arranged on keyset, after keyset rewiring, amplifying pitch, then keyset is attached on array base palte,
Or form groove on array base palte, keyset is placed in groove.
Because the technical scheme of the present embodiment is the difference that drive circuit and display unit are separately positioned on underlay substrate
On surface, therefore, it is not necessary to reserve larger region to place drive circuit such that it is able to reduce electricity at the edge of viewing area
Components and parts are taken up space, and realize compactization of display module, and narrow frame, the ultra-narrow frame of realizing display device are even boundless
Frame.
In each method embodiment of the present invention, the priority that the sequence number of described each step can not be used for limiting each step is suitable
Sequence, for those of ordinary skill in the art, on the premise of not paying creative work, the priority change to each step
Within protection scope of the present invention.
The above is the preferred embodiment of the present invention it is noted that for those skilled in the art
For, on the premise of without departing from principle of the present invention, some improvements and modifications can also be made, these improvements and modifications
Should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of manufacture method of array base palte is it is characterised in that include：
One underlay substrate is provided；
Form the multiple vias running through described underlay substrate；
Form conductive pole in described via；
Grid line data line is formed on the first surface of underlay substrate, each data wire and/or each grid line are led with one respectively
Electric post electrical connection.
2. the manufacture method of array base palte according to claim 1 is it is characterised in that described formation in described via is led
The step of electric post includes：
Evaporation binding material and conductive material, described binding material and described conduction on the underlay substrate being formed with described via
Material sticks to described in the hole of crossing and forms described conductive pole.
3. the manufacture method of array base palte according to claim 1 is it is characterised in that form institute by patterning processes
State the grid conductive layer figure of conductive pole and array base palte, described grid conductive layer figure includes the gate electrode of thin film transistor (TFT) and described
Grid line, forms described conductive pole and the step of described grid conductive layer figure includes：
Evaporation binding material and conductive material, the first surface of described underlay substrate on the underlay substrate being formed with described via
Towards evaporation source, described binding material and described conductive material stick to described in the hole of crossing and form described conductive pole, described bonding
Material and described conductive material stick to described first surface and form the first conductive layer；
Described first conductive layer coats photoresist, using mask plate, described photoresist is exposed, after development, form light
Photoresist reservation region and the non-reservation region of photoresist, described photoresist reservation region corresponds to described grid conductive layer figure；
Described first conductive layer is performed etching, removes the first conductive layer of the non-reservation region of photoresist；
The photoresist of stripping photoresist reservation region, forms described grid conductive layer figure.
4. the manufacture method of array base palte according to claim 1 is it is characterised in that described formation in described via is led
The step of electric post includes：
Insulating barrier, adhesion layer, barrier layer and plating seed layer are sequentially formed on the inwall of described via, and passes through electroplating technology
Filler metal in described via, forms described conductive pole.
5. after the manufacture method of array base palte according to claim 1 is it is characterised in that form described conductive pole, institute
State manufacture method also to include：
The conductive lead wire being connected with described conductive pole in the second surface formation opposite with described first surface of described array base palte.
6. array base palte according to claim 5 manufacture method it is characterised in that formed described conductive lead wire step
Including：
Evaporation binding material and conductive material, the second table of described underlay substrate on the underlay substrate being formed with described conductive pole
Facing to evaporation source, described binding material and described conductive material stick to described second surface and form the second conductive layer；
Described second conductive layer coats photoresist, using mask plate, described photoresist is exposed, after development, form light
Photoresist reservation region and the non-reservation region of photoresist, the figure of the corresponding described conductive lead wire of described photoresist reservation region；
Described second conductive layer is performed etching, removes the second conductive layer of the non-reservation region of photoresist；
The photoresist of stripping photoresist reservation region, forms described conductive lead wire.
7. a kind of array base palte is it is characterised in that be made to using the manufacture method as any one of claim 1-6
Arrive, described array base palte includes underlay substrate, described underlay substrate includes the multiple vias running through described underlay substrate, described mistake
It is formed with conductive pole in hole, the first surface of described underlay substrate forms grid line data line, each data wire and/or grid line
Electrically connect with a conductive pole respectively.
8. array base palte according to claim 7 is it is characterised in that described array base palte also includes：
It is arranged on the conductive lead wire on the second surface opposite with described first surface of described underlay substrate, described conductive lead wire
It is connected with described conductive pole.
9. a kind of manufacture method of display device is it is characterised in that include：
The array base palte as claimed in claim 7 or 8 second surface opposite with described first surface adheres at least one
Drive circuit, the drive circuit on described second surface is connected with described conductive pole by conductive lead wire.
10. a kind of display device is it is characterised in that being to make using manufacture method as claimed in claim 9 to obtain, described aobvious
The grid line of showing device, data wire, the multiple pixel cells being limited by grid line data line are located at the first surface of underlay substrate,
At least one drive circuit of described display device is located at the described underlay substrate second surface opposite with described first surface.
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| CN201610985205.9A CN106409796A (en) | 2016-10-25 | 2016-10-25 | Array substrate, manufacturing method thereof, display device and manufacturing method thereof |
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| CN201610985205.9A CN106409796A (en) | 2016-10-25 | 2016-10-25 | Array substrate, manufacturing method thereof, display device and manufacturing method thereof |
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