CN106395735A - Method for manufacturing resistive element, method for manufacturing pressure sensor element, pressure sensor element, pressure sensor - Google Patents
Method for manufacturing resistive element, method for manufacturing pressure sensor element, pressure sensor element, pressure sensor Download PDFInfo
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- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/02—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning
- G01L9/06—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning of piezo-resistive devices
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Abstract
本发明提供一种能够将极薄的电阻区域以埋入到极浅的位置的状态形成的电阻元件的制造方法以及压力传感器元件的制造方法,此外,提供一种能够实现小型化以及高精度化的压力传感器元件,并且,提供一种具备所涉及的压力传感器元件的压力传感器、高度计、电子设备以及移动体。本发明的电阻元件的制造方法包括:准备具有n型的硅层(213)的基板(2)的工序;通过向硅层(213)掺杂杂质从而形成电阻区域(51)的工序;通过快速热退火、闪光灯退火以及准分子激光退火中的任意一种退火来对电阻区域(51)进行热处理的工序;通过使硅在电阻区域(51)上外延生长从而形成覆盖层(213a)的工序。
The present invention provides a method of manufacturing a resistance element and a method of manufacturing a pressure sensor element capable of forming an extremely thin resistance region in a state of being buried at an extremely shallow position, and also provides a method capable of achieving miniaturization and high precision. A pressure sensor element, and a pressure sensor, an altimeter, an electronic device, and a mobile body including the pressure sensor element are provided. The manufacturing method of the resistance element of the present invention comprises: the operation of preparing a substrate (2) having an n-type silicon layer (213); the operation of forming a resistance region (51) by doping impurities into the silicon layer (213); A step of heat-treating the resistance region (51) by any one of thermal annealing, flash lamp annealing, and excimer laser annealing; and a step of forming a capping layer (213a) by epitaxially growing silicon on the resistance region (51).
Description
技术领域technical field
本发明涉及电阻元件的制造方法、压力传感器元件的制造方法、压力传感器元件、压力传感器、高度计、电子设备以及移动体。The present invention relates to a method of manufacturing a resistance element, a method of manufacturing a pressure sensor element, a pressure sensor element, a pressure sensor, an altimeter, an electronic device, and a moving body.
背景技术Background technique
在微机电系统(MEMS)(特别是传感器装置)中,广泛采用通过向单晶硅掺杂杂质从而形成电阻元件(压电电阻元件)的方式。In micro-electro-mechanical systems (MEMS) (in particular, sensor devices), a method of doping single crystal silicon with impurities to form resistance elements (piezoelectric resistance elements) is widely used.
作为这种电阻元件的制造方法,例如已知有如专利文献1所公开的那样,通过将硼加速至1MeV的能量并打入到n型硅基板中,从而于在基板表面上残留有n型层的状态下,形成p型的电阻层(电阻区域)的方法。通过利用这种方法而将电阻层埋入所形成的电阻元件,能够降低外部电场的影响。As a method for manufacturing such a resistance element, for example, as disclosed in Patent Document 1, boron is accelerated to an energy of 1 MeV and implanted into an n-type silicon substrate, thereby leaving an n-type layer on the substrate surface. A method of forming a p-type resistive layer (resistive region) in the state. By embedding the resistive layer in the formed resistive element by this method, the influence of an external electric field can be reduced.
然而,由于在专利文献1所记载的方法中,电阻层被形成至比较深的位置,因此存在有如下问题,即,例如在将电阻元件用于极薄的隔膜的挠曲检测的情况下,将电阻层以偏向隔膜的一面的状态埋入,以便能够实施效率的检测是较为困难的。However, in the method described in Patent Document 1, since the resistive layer is formed at a relatively deep position, there is a problem that, for example, when a resistive element is used for deflection detection of an extremely thin diaphragm, It is difficult to bury the resistive layer so that it is biased toward one side of the diaphragm so that the efficiency can be tested.
专利文献1:日本特开平7-131035号公报Patent Document 1: Japanese Patent Application Laid-Open No. 7-131035
发明内容Contents of the invention
本发明的目的在于,提供一种能够将极薄的电阻区域以埋入到极浅的位置的状态而形成的电阻元件的制造方法以及压力传感器元件的制造方法,此外,提供一种能够实现小型化以及高精度化的压力传感器元件,而且提供具备所涉及的压力传感器元件的压力传感器、高度计、电子设备以及移动体。The object of the present invention is to provide a method of manufacturing a resistance element and a method of manufacturing a pressure sensor element in which an extremely thin resistance region can be buried at an extremely shallow position. A pressure sensor element with improved and higher precision, and a pressure sensor, an altimeter, an electronic device, and a mobile body including the pressure sensor element are provided.
此种目的通过下述的本发明来达成。Such objects are achieved by the present invention described below.
应用例1Application example 1
本发明的电阻元件的制造方法的特征在于,包括:准备具有硅层的基板的工序,所述硅层具备n型或者p型的区域;通过向所述区域掺杂杂质从而形成电阻区域的工序;通过快速热退火、闪光灯退火以及准分子激光退火中的任意一种退火来对所述电阻区域进行热处理的工序;通过使硅在所述电阻区域上外延生长从而形成覆盖层的工序。The method for manufacturing a resistance element according to the present invention is characterized in that it includes: a step of preparing a substrate having a silicon layer having an n-type or p-type region; and a step of forming a resistance region by doping the region with an impurity. ; a process of heat-treating the resistance region by any one of rapid thermal annealing, flash lamp annealing, and excimer laser annealing; and a process of forming a capping layer by epitaxially growing silicon on the resistance region.
根据这种电阻元件的制造方法,由于通过快速热退火、闪光灯退火以及准分子激光退火之中的任意一种退火来对电阻区域进行热处理,因此热预算(热过程)较低,从而能够在减少杂质的扩散而将电阻区域留在较浅的位置的同时,使电阻区域活化。此外,由于在所获得的电阻元件中,电阻区域通过覆盖层而被覆盖从而被埋设,因此能够减少噪声向电阻区域的混入。特别是,由于能够将覆盖层通过外延生长而形成,因此能够在将电阻区域的厚度设置得极薄的同时,将电阻区域埋设在极浅的位置处。According to this method of manufacturing a resistance element, since the resistance region is heat-treated by any one of rapid thermal annealing, flash lamp annealing, and excimer laser annealing, the thermal budget (thermal history) is low, enabling reduction in Diffusion of impurities activates the resistive region while leaving it shallow. In addition, in the obtained resistance element, since the resistance region is covered and buried with the cover layer, it is possible to reduce the incorporation of noise into the resistance region. In particular, since the capping layer can be formed by epitaxial growth, it is possible to bury the resistance region at an extremely shallow position while making the thickness of the resistance region extremely thin.
应用例2Application example 2
在本发明的电阻元件的制造方法中,优选为,在形成所述覆盖层的工序中,使用乙硅烷气体来实施所述外延生长。In the method for manufacturing a resistor element according to the present invention, it is preferable that the epitaxial growth is performed using disilane gas in the step of forming the capping layer.
由此,能够在较低的温度下形成覆盖层。因此,能够在形成覆盖层的工序中减少电阻区域扩散的情况。Thus, the covering layer can be formed at a relatively low temperature. Therefore, it is possible to reduce diffusion of the resistive region in the step of forming the cover layer.
应用例3Application example 3
在本发明的电阻元件的制造方法中,优选为,在进行所述热处理的工序中,所述热处理后的所述电阻区域的厚度处于0.1μm以上且2.0μm以下的范围内。In the method for manufacturing a resistor element according to the present invention, preferably, in the step of performing the heat treatment, the thickness of the resistor region after the heat treatment is in a range of 0.1 μm to 2.0 μm.
由此,例如,在将电阻元件作为形变检测元件而设置在通过受压而挠曲变形的隔膜部中的情况下,即使将隔膜部设置得极薄,也能够使电阻区域偏向隔膜部的表面附近,从而能够使电阻元件的检测精度较为优异。Thus, for example, when a resistance element is provided as a strain detection element in a diaphragm portion that is flexed and deformed by pressure, even if the diaphragm portion is made extremely thin, the resistance region can be biased toward the surface of the diaphragm portion. nearby, so that the detection accuracy of the resistance element can be excellent.
应用例4Application example 4
在本发明的电阻元件的制造方法中,优选为,在形成所述覆盖层的工序中,所述覆盖层的厚度处于0.05μm以上且0.4μm以下的范围内。In the method for manufacturing a resistor element according to the present invention, preferably, in the step of forming the covering layer, the thickness of the covering layer is in a range of 0.05 μm to 0.4 μm.
由此,例如,在将电阻元件作为形变检测元件而设置在通过受压而挠曲变形的隔膜部中的情况下,即使将隔膜部设置得极薄,也能够使电阻区域偏向隔膜部的表面附近,从而能够使电阻元件的检测精度较为优异。Thus, for example, when a resistance element is provided as a strain detection element in a diaphragm portion that is flexed and deformed by pressure, even if the diaphragm portion is made extremely thin, the resistance region can be biased toward the surface of the diaphragm portion. nearby, so that the detection accuracy of the resistance element can be excellent.
应用例5Application example 5
本发明的压力传感器元件的制造方法的特征在于,包括:使用本发明的电阻元件的制造方法来形成电阻元件的工序;通过对所述基板的一面侧进行蚀刻从而形成设置有所述电阻元件的隔膜部的工序。The manufacturing method of the pressure sensor element of the present invention is characterized in that it includes: the steps of forming a resistive element using the manufacturing method of the resistive element of the present invention; Diaphragm process.
根据这种压力传感器元件的制造方法,在所获得的压力传感器元件中,即使将隔膜部设置得极薄,也能够使电阻区域偏向隔膜部的表面附近,从而能够使电阻元件的检测精度较为优异。此外,由于在所获得的压力传感器元件中,电阻区域通过覆盖层而被覆盖从而被埋设,因此能够减少噪声向电阻区域的混入。由此,能够实现所获得的压力传感器元件的小型化以及高精度化。According to such a method of manufacturing a pressure sensor element, in the obtained pressure sensor element, even if the diaphragm portion is made extremely thin, the resistance region can be shifted to the vicinity of the surface of the diaphragm portion, and the detection accuracy of the resistance element can be made excellent. . In addition, since the resistive region is buried by being covered with the cover layer in the obtained pressure sensor element, it is possible to reduce the mixing of noise into the resistive region. Thereby, miniaturization and high precision of the obtained pressure sensor element can be achieved.
应用例6Application example 6
本发明的压力传感器元件的特征在于,具有隔膜部,所述隔膜部具备:硅层;电阻元件,其具有在所述硅层内含有载流子的电阻区域,并产生对应于形变的电信号;所述电阻区域上的覆盖层,所述电阻区域的厚度相对于所述隔膜部的厚度处于5%以上且30%以下的范围内,所述隔膜部的所述覆盖层一侧的面和所述电阻区域的载流子浓度的峰值位置之间的距离相对于所述隔膜部的厚度处于2%以上且40%以下的范围内。The pressure sensor element of the present invention is characterized in that it has a diaphragm portion including: a silicon layer; and a resistance element having a resistance region containing carriers in the silicon layer and generating an electrical signal corresponding to deformation. the cover layer on the resistance region, the thickness of the resistance region is in the range of 5% to 30% of the thickness of the diaphragm part, and the surface of the diaphragm part on the side of the cover layer and A distance between peak positions of carrier concentration in the resistance region is within a range of 2% to 40% of the thickness of the diaphragm portion.
根据这种压力传感器元件,即使将隔膜部设置得极薄,也能够使电阻元件偏向隔膜部的表面附近,从而能够使电阻元件的检测精度较为优异。此外,由于电阻区域通过覆盖层而被覆盖从而被埋设,因此能够减少噪声向电阻区域的混入。由此,能够实现压力传感器元件的小型化以及高精度化。According to such a pressure sensor element, even if the diaphragm portion is provided extremely thin, the resistance element can be positioned near the surface of the diaphragm portion, and the detection accuracy of the resistance element can be improved. In addition, since the resistive region is buried by being covered with the cover layer, it is possible to reduce the mixing of noise into the resistive region. Thereby, miniaturization and high precision of the pressure sensor element can be realized.
应用例7Application example 7
在本发明的压力传感器元件中,优选为,具备被设置在所述覆盖层一侧的压力基准室。In the pressure sensor element of the present invention, it is preferable to include a pressure reference chamber provided on the cover layer side.
由此,能够实现以压力基准室的压力为基准来对压力进行检测的压力传感器元件。Accordingly, it is possible to realize a pressure sensor element that detects pressure using the pressure of the pressure reference chamber as a reference.
应用例8Application example 8
在本发明的压力传感器元件中,优选为,所述隔膜部的厚度处于0.5μm以上且15μm以下的范围内。In the pressure sensor element of the present invention, it is preferable that the thickness of the diaphragm part is in the range of 0.5 μm or more and 15 μm or less.
由此,能够实现小型的压力传感器元件。Thus, a small pressure sensor element can be realized.
应用例9Application example 9
在本发明的压力传感器元件中,优选为,所述电阻区域的厚度处于0.1μm以上且2.0μm以下的范围内。In the pressure sensor element of the present invention, preferably, the thickness of the resistance region is in a range of 0.1 μm or more and 2.0 μm or less.
由此,即使将隔膜部设置得极薄,也能够使电阻区域偏向隔膜部的表面附近,从而能够使电阻元件的检测精度较为优异。Thereby, even if the diaphragm part is provided extremely thin, the resistance region can be shifted toward the vicinity of the surface of the diaphragm part, and the detection accuracy of the resistance element can be made excellent.
应用例10Application Example 10
在本发明的压力传感器元件中,优选为,所述隔膜部的所述覆盖层一侧的面和所述电阻区域的载流子浓度的峰值位置之间的距离处于0.05μm以上且0.4μm以下的范围内。In the pressure sensor element according to the present invention, preferably, the distance between the surface of the diaphragm portion on the cover layer side and the peak position of the carrier concentration of the resistance region is 0.05 μm or more and 0.4 μm or less. In the range.
由此,即使将隔膜部设置得极薄,也能够使电阻区域偏向隔膜部的表面附近,从而能够使电阻元件的检测精度较为优异。Thereby, even if the diaphragm part is provided extremely thin, the resistance region can be shifted toward the vicinity of the surface of the diaphragm part, and the detection accuracy of the resistance element can be made excellent.
应用例11Application Example 11
在本发明的压力传感器元件中,优选为,具备基板,所述基板具有所述隔膜部以及电路部。In the pressure sensor element of the present invention, it is preferable to include a substrate having the diaphragm portion and the circuit portion.
由此,能够实现将隔膜部与电路部集成在一个芯片上的压力传感器元件。Accordingly, it is possible to realize a pressure sensor element in which the diaphragm unit and the circuit unit are integrated on one chip.
应用例12Application example 12
本发明的压力传感器的特征在于,具备本发明的压力传感器元件。The pressure sensor of the present invention is characterized by comprising the pressure sensor element of the present invention.
根据这种压力传感器,能够实现压力传感器元件的小型化以及高精度化。According to such a pressure sensor, it is possible to reduce the size and increase the precision of the pressure sensor element.
应用例13Application Example 13
本发明的高度计的特征在于,具备本发明的压力传感器元件。The altimeter of the present invention is characterized by including the pressure sensor element of the present invention.
根据这种高度计,能够实现压力传感器元件的小型化以及高精度化。According to such an altimeter, it is possible to reduce the size and increase the precision of the pressure sensor element.
应用例14Application example 14
本发明的电子设备的特征在于,具备本发明的压力传感器元件。An electronic device of the present invention includes the pressure sensor element of the present invention.
根据这种电子设备,能够实现压力传感器元件的小型化以及高精度化。According to such an electronic device, it is possible to realize miniaturization and high precision of the pressure sensor element.
应用例15Application Example 15
本发明的移动体的特征在于,具备本发明的压力传感器元件。The mobile body of the present invention is characterized by including the pressure sensor element of the present invention.
根据这种移动体,能够实现压力传感器元件的小型化以及高精度化。According to such a moving body, it is possible to reduce the size and increase the precision of the pressure sensor element.
附图说明Description of drawings
图1为表示本发明的第一实施方式所涉及的压力传感器元件的剖视图。FIG. 1 is a cross-sectional view showing a pressure sensor element according to a first embodiment of the present invention.
图2为表示图1所示的压力传感器元件所具备的电阻元件的配置的俯视图。FIG. 2 is a plan view showing an arrangement of resistive elements included in the pressure sensor element shown in FIG. 1 .
图3为表示图2所示的电阻元件的电阻区域的载流子浓度分布的一个示例的曲线图。FIG. 3 is a graph showing an example of a carrier concentration distribution in a resistance region of the resistance element shown in FIG. 2 .
图4为用于对图1所示的压力传感器元件的作用进行说明的图,(a)为表示加压状态的剖视图,(b)为表示加压状态的俯视图。Fig. 4 is a view for explaining the action of the pressure sensor element shown in Fig. 1, (a) is a cross-sectional view showing a pressurized state, and (b) is a plan view showing a pressurized state.
图5为表示图1所示的压力传感器元件的制造工序(电阻元件的形成工序)的图。FIG. 5 is a view showing a manufacturing process (forming a resistive element) of the pressure sensor element shown in FIG. 1 .
图6为表示图5所示的退火后的电阻元件的载流子浓度分布的一个示例的曲线图。FIG. 6 is a graph showing an example of the carrier concentration distribution of the annealed resistance element shown in FIG. 5 .
图7为表示图1所示的压力传感器元件的制造工序(绝缘层、电路部等的形成工序)的图。FIG. 7 is a view showing manufacturing steps (steps of forming an insulating layer, a circuit portion, etc.) of the pressure sensor element shown in FIG. 1 .
图8为表示图1所示的压力传感器元件的制造工序(压力基准室、隔膜部等的形成工序)的图。FIG. 8 is a view showing a manufacturing process of the pressure sensor element shown in FIG. 1 (a forming process of a pressure reference chamber, a diaphragm portion, and the like).
图9为表示本发明的第二实施方式所涉及的压力传感器元件的剖视图。9 is a cross-sectional view showing a pressure sensor element according to a second embodiment of the present invention.
图10为本发明的压力传感器的一个示例的剖视图。Fig. 10 is a sectional view of an example of the pressure sensor of the present invention.
图11为表示本发明的高度计的一个示例的立体图。Fig. 11 is a perspective view showing an example of the altimeter of the present invention.
图12为表示本发明的电子设备的一个示例的主视图。Fig. 12 is a front view showing an example of the electronic device of the present invention.
图13为表示本发明的移动体的一个示例的立体图。Fig. 13 is a perspective view showing an example of the moving body of the present invention.
具体实施方式detailed description
以下,根据附图中所示的各实施方式来对本发明的压力传感器元件、压力传感器、高度计、电子设备以及移动体详细地进行说明。Hereinafter, the pressure sensor element, the pressure sensor, the altimeter, the electronic device, and the mobile body of the present invention will be described in detail based on the respective embodiments shown in the drawings.
1.压力传感器元件1. Pressure sensor element
第一实施方式first embodiment
图1为表示本发明的第一实施方式所涉及的压力传感器元件的剖视图,图2为表示图1所示的压力传感器元件所具备的电阻元件的配置的俯视图。图3为表示图2所示的电阻元件的电阻区域的载流子浓度分布的一个示例的曲线图。图4为用于对图1所示的压力传感器元件的作用进行说明的图,图4(a)为表示加压状态的剖视图,图4(b)为表示加压状态的俯视图。另外,在以下,为了便于进行说明,将图1中的上侧称为“上”,下侧称为“下”。1 is a cross-sectional view showing a pressure sensor element according to a first embodiment of the present invention, and FIG. 2 is a plan view showing an arrangement of resistive elements included in the pressure sensor element shown in FIG. 1 . FIG. 3 is a graph showing an example of a carrier concentration distribution in a resistance region of the resistance element shown in FIG. 2 . 4 is a diagram for explaining the action of the pressure sensor element shown in FIG. 1, FIG. 4(a) is a sectional view showing a pressurized state, and FIG. 4(b) is a plan view showing a pressurized state. In addition, in the following, for convenience of explanation, the upper side in FIG. 1 is called "upper", and the lower side is called "lower".
图1所示的压力传感器元件1具备:具有隔膜部20的基板2;被设置在隔膜部20中的多个压电电阻元件5(电阻元件);与基板2一起形成了空洞部S(压力基准室)的层压结构体6;半导体电路9(电路部)。The pressure sensor element 1 shown in FIG. 1 includes: a substrate 2 having a diaphragm portion 20; a plurality of piezoresistive elements 5 (resistive elements) provided in the diaphragm portion 20; Reference chamber) laminated structure 6; semiconductor circuit 9 (circuit part).
以下,依次对构成压力传感器元件1的各部分进行说明。Hereinafter, each part constituting the pressure sensor element 1 will be described in order.
基板Substrate
基板2具有:半导体基板21;被设置在半导体基板21的一面上的绝缘膜22;被设置在绝缘膜22的与半导体基板21相反的一侧的面上的绝缘膜23。The substrate 2 has a semiconductor substrate 21 , an insulating film 22 provided on one surface of the semiconductor substrate 21 , and an insulating film 23 provided on the surface of the insulating film 22 opposite to the semiconductor substrate 21 .
半导体基板21为,依次层压有由单晶硅构成的硅层211(处理层(handle layer))、由硅氧化膜构成的氧化硅层212(盒层(BOX layer))、由单晶硅构成的硅层213(装置层(device layer))的SOI(Silicon On Insulator:绝缘体上硅)基板。另外,半导体基板21并不限定于SOI基板,例如,也可以为单晶硅基板等其他的半导体基板。The semiconductor substrate 21 is formed by sequentially laminating a silicon layer 211 (handle layer) made of single crystal silicon, a silicon oxide layer 212 (box layer) made of silicon oxide film, and a layer made of single crystal silicon. An SOI (Silicon On Insulator: silicon-on-insulator) substrate comprising a silicon layer 213 (device layer). In addition, the semiconductor substrate 21 is not limited to an SOI substrate, and may be other semiconductor substrates such as a single crystal silicon substrate, for example.
绝缘膜22例如为硅氧化膜,具有绝缘性。此外,绝缘膜23例如为硅氮化膜,具有绝缘性,并且还具有相对于含有氟酸的蚀刻液的耐性。在此,由于绝缘膜22(硅氧化膜)介于半导体基板21(硅层213)与绝缘膜23(硅氮化膜)之间,从而能够通过绝缘膜22来缓和绝缘膜23的成膜时所产生的应力传递至半导体基板21的情况。此外,绝缘膜22能够作为半导体电路9的元件间分离膜来使用。另外,绝缘膜22、23并不限定于前文所述的构成材料,此外,也可以根据需要而省略绝缘膜22、23中的任意一方。The insulating film 22 is, for example, a silicon oxide film and has insulating properties. In addition, the insulating film 23 is, for example, a silicon nitride film, has insulating properties, and also has resistance to an etchant containing hydrofluoric acid. Here, since the insulating film 22 (silicon oxide film) is interposed between the semiconductor substrate 21 (silicon layer 213) and the insulating film 23 (silicon nitride film), the time for forming the insulating film 23 can be eased by the insulating film 22. The generated stress is transmitted to the semiconductor substrate 21 . In addition, the insulating film 22 can be used as an element separation film of the semiconductor circuit 9 . In addition, the insulating films 22 and 23 are not limited to the constituent materials described above, and either one of the insulating films 22 and 23 may be omitted as necessary.
在这种基板2上,设置有与周围的部分相比为薄壁,并通过受压而挠曲变形的隔膜部20。隔膜部20通过在半导体基板21的下表面设置有底的凹部24而形成。该隔膜部20的下表面成为受压面25。在本实施方式中,如图2所示,隔膜部20为正方形(矩形)的俯视形状。On such a substrate 2, there is provided a diaphragm portion 20 which is thinner than the surrounding portion and flexibly deformed by being pressed. The diaphragm portion 20 is formed by providing a bottomed concave portion 24 on the lower surface of the semiconductor substrate 21 . The lower surface of the diaphragm portion 20 serves as a pressure receiving surface 25 . In this embodiment, as shown in FIG. 2 , the diaphragm portion 20 has a square (rectangular) planar shape.
在本实施方式的基板2中,凹部24贯穿硅层211,隔膜部20通过氧化硅层212、硅层213、绝缘膜22以及绝缘膜23这四层而被构成。在此,如后文所述,氧化硅层212能够在压力传感器元件1的制造工序中在通过蚀刻而形成凹部24时,作为蚀刻停止层而被利用,从而能够减少隔膜部20的厚度在每个制品中的偏差。In the substrate 2 of the present embodiment, the concave portion 24 penetrates the silicon layer 211 , and the diaphragm portion 20 is constituted by four layers of the silicon oxide layer 212 , the silicon layer 213 , the insulating film 22 , and the insulating film 23 . Here, as will be described later, the silicon oxide layer 212 can be used as an etching stopper layer when forming the recessed portion 24 by etching in the manufacturing process of the pressure sensor element 1, and the thickness of the diaphragm portion 20 can be reduced every time. Deviations in individual products.
另外,凹部24也可以不贯穿硅层211,从而隔膜部20通过硅层211的薄壁部、氧化硅层212、硅层213、绝缘膜22以及绝缘膜23这五层而构成。In addition, the recess 24 does not need to penetrate the silicon layer 211 , and the diaphragm portion 20 is constituted by five layers of the thin portion of the silicon layer 211 , the silicon oxide layer 212 , the silicon layer 213 , the insulating film 22 , and the insulating film 23 .
压电电阻元件(电阻元件)Piezoelectric resistance element (resistive element)
如图1所示,多个压电电阻元件5分别被形成在隔膜部20的空洞部S侧。在此,压电电阻元件5被形成在半导体基板21的硅层213中。As shown in FIG. 1 , a plurality of piezoresistive elements 5 are respectively formed on the cavity S side of the diaphragm portion 20 . Here, the piezoelectric resistance element 5 is formed in the silicon layer 213 of the semiconductor substrate 21 .
如图2所示,多个压电电阻元件5通过被配置于隔膜部20的外周部的多个压电电阻元件5a、5b、5c、5d而构成。As shown in FIG. 2 , the plurality of piezoresistor elements 5 are constituted by a plurality of piezoresistor elements 5 a , 5 b , 5 c , and 5 d arranged on the outer peripheral portion of the diaphragm portion 20 .
对应于在从基板2的厚度方向俯视观察时(以下,仅称为“俯视观察”)时呈四边形的隔膜部20的四个边,而分别配置有压电电阻元件5a、压电电阻元件5b、压电电阻元件5c、压电电阻元件5d。The piezoresistive element 5 a and the piezoresistive element 5 b are arranged corresponding to the four sides of the quadrilateral diaphragm portion 20 when viewed from above in the thickness direction of the substrate 2 (hereinafter simply referred to as “planar view”). , piezoresistive element 5c, piezoresistive element 5d.
压电电阻元件5a具有沿着与隔膜部20的对应的边垂直的方向而延伸的电阻区域51a。在该电阻区域51a的两端部上电连接有一对配线214a。同样地,压电电阻元件5b具有沿着与隔膜部20的对应的边垂直的方向而延伸的电阻区域51b。在该电阻区域51b的两端部上电连接有一对配线214b。The piezoelectric resistance element 5 a has a resistance region 51 a extending in a direction perpendicular to the corresponding side of the diaphragm portion 20 . A pair of wirings 214a are electrically connected to both ends of the resistance region 51a. Similarly, the piezoelectric resistance element 5 b has a resistance region 51 b extending in a direction perpendicular to the corresponding side of the diaphragm portion 20 . A pair of wirings 214b are electrically connected to both ends of the resistance region 51b.
另一方面,压电电阻元件5c具有沿着与隔膜部20的对应的边平行的方向而延伸的电阻区域51c。在该电阻区域51c的两端部上电连接有一对配线214c。同样地,压电电阻元件5d具有沿着与隔膜部20的对应的边平行的方向而延伸的电阻区域51d。在该电阻区域51d的两端部上电连接有一对配线214d。On the other hand, the piezoelectric resistance element 5 c has a resistance region 51 c extending in a direction parallel to the corresponding side of the diaphragm portion 20 . A pair of wirings 214c are electrically connected to both ends of the resistance region 51c. Similarly, the piezoelectric resistance element 5 d has a resistance region 51 d extending in a direction parallel to the corresponding side of the diaphragm portion 20 . A pair of wirings 214d are electrically connected to both ends of the resistance region 51d.
虽然未图示,但配线214a、214b、214c、214d分别具有在半导体基板21的上表面露出的部分,并且配线214a、214b、214c、214d经由所涉及的部分而与半导体电路9电连接。Although not shown in the figure, the wirings 214a, 214b, 214c, and 214d each have portions exposed on the upper surface of the semiconductor substrate 21, and the wirings 214a, 214b, 214c, and 214d are electrically connected to the semiconductor circuit 9 via the portions. .
另外,在以下,也将电阻区域51a、51b、51c、51d统称为“电阻区域51”,将配线214a、214b、214c、214d统称为“配线214”。In addition, hereinafter, the resistance regions 51a, 51b, 51c, and 51d are also collectively referred to as "resistance region 51", and the wirings 214a, 214b, 214c, and 214d are also collectively referred to as "wiring 214".
这种压电电阻元件5的电阻区域51以及配线214分别通过将例如磷(n型)、硼(p型)等的杂质作为载流子而向硅(单晶硅)掺杂(扩散或者注入)而被构成。在此,配线214中的杂质的掺杂浓度与电阻区域51中的杂质的掺杂浓度相比较高。另外,配线214的至少一部分也可以由金属构成。The resistance region 51 and the wiring 214 of the piezoresistive element 5 are doped (diffused or Injection) is formed. Here, the doping concentration of impurities in the wiring 214 is higher than the doping concentration of impurities in the resistance region 51 . In addition, at least a part of the wiring 214 may be made of metal.
这种含有载流子的电阻区域51以及配线214被埋设在隔膜部20的硅层213中。即,电阻区域51以及配线214的上表面通过覆盖层213a而被覆盖,该覆盖层213a由与电阻区域51以及配线214不同的导电型的单晶硅构成。Such a carrier-containing resistive region 51 and wiring 214 are buried in the silicon layer 213 of the diaphragm portion 20 . That is, the upper surfaces of the resistance region 51 and the wiring 214 are covered with the cover layer 213 a made of single crystal silicon of a conductivity type different from that of the resistance region 51 and the wiring 214 .
在此,电阻区域51以及配线214的导电型为,与硅层213的除电阻区域51以及配线214之外的部分不同的导电型。即,在电阻区域51以及配线214为p型的情况下,硅层213的除电阻区域51以及配线214之外的部分为n型,覆盖层213a也为n型,而在电阻区域51以及配线214为n型的情况下,硅层213的除电阻区域51以及配线214之外的部分为p型,覆盖层213a也为p型。如此,在电阻区域51以及配线214与硅层213的除电阻区域51以及配线214之外的部分之间形成有pn结。由此,能够减少来自电阻区域51以及配线214的漏电流。Here, the conductivity type of the resistance region 51 and the wiring 214 is different from that of the silicon layer 213 except for the resistance region 51 and the wiring 214 . That is, when the resistance region 51 and the wiring 214 are p-type, the part of the silicon layer 213 other than the resistance region 51 and the wiring 214 is n-type, and the cladding layer 213a is also n-type. And when the wiring 214 is n-type, the part of the silicon layer 213 other than the resistance region 51 and the wiring 214 is p-type, and the cladding layer 213a is also p-type. In this way, a pn junction is formed between the resistance region 51 and the wiring 214 and the portion of the silicon layer 213 other than the resistance region 51 and the wiring 214 . Thereby, leakage current from the resistance region 51 and the wiring 214 can be reduced.
虽然电阻区域51以及配线214的导电型为p型、n型中的任意一型均可,但优选为p型。由此,能够使压电电阻元件5的检测灵敏度较为优异。另外,在以下,对电阻区域51以及配线214为p型的情况进行说明。The conductivity type of the resistance region 51 and the wiring 214 may be either p-type or n-type, but is preferably p-type. Accordingly, the detection sensitivity of the piezoresistive element 5 can be made excellent. In addition, below, the case where the resistance region 51 and the wiring 214 are p-type is demonstrated.
此外,如图3所示,电阻区域51的厚度t2为p型区域的厚度,其相对于隔膜部20的厚度t1处于5%以上且30%以下的范围内,隔膜部20的覆盖层213a一侧的面和电阻区域51的载流子浓度的峰值位置之间的距离L相对于隔膜部20的厚度t1处于2%以上且40%以下的范围内。由此,能够在将隔膜部20设置得极薄的同时,使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的检测精度较为优异。此外,由于电阻区域51被埋设,因此能够减少噪声向电阻区域51的混入。由此,能够实现压力传感器元件1的小型化以及高精度化。In addition, as shown in FIG. 3 , the thickness t2 of the resistance region 51 is the thickness of the p-type region, which is in the range of 5% to 30% of the thickness t1 of the diaphragm part 20, and the covering layer of the diaphragm part 20 The distance L between the surface on the 213a side and the peak position of the carrier concentration of the resistance region 51 is within the range of 2% to 40% of the thickness t1 of the diaphragm portion 20 . Accordingly, it is possible to make the diaphragm portion 20 extremely thin, and at the same time displace the resistive region 51 toward the vicinity of the surface of the diaphragm portion 20 , so that the detection accuracy of the piezoresistive element 5 can be made excellent. In addition, since the resistance region 51 is buried, it is possible to reduce the mixing of noise into the resistance region 51 . Accordingly, it is possible to realize downsizing and high precision of the pressure sensor element 1 .
在此,隔膜部20的厚度t1优选为处于0.5μm以上且15μm以下的范围内,更优选为处于0.5μm以上且5μm以下的范围内,进一步优选为处于0.5μm以上且4μm以下的范围内。由此,即使将宽度设为较小也能够使隔膜部20通过受压而挠曲变形,其结果为,能够实现小型的压力传感器元件1。Here, the thickness t1 of the diaphragm portion 20 is preferably in the range of 0.5 μm to 15 μm, more preferably in the range of 0.5 μm to 5 μm, and still more preferably in the range of 0.5 μm to 4 μm. . Thereby, even if the width is made small, the diaphragm portion 20 can be deflected and deformed by receiving pressure, and as a result, a compact pressure sensor element 1 can be realized.
此外,隔膜部20的宽度w优选为处于50μm以上且500μm以下的范围内,更加优选为处于50μm以上且200μm以下的范围内,进一步优选为处于80μm以上且200μm以下的范围内。由此,能够实现小型的压力传感元件1。In addition, the width w of the diaphragm portion 20 is preferably in the range of 50 μm to 500 μm, more preferably in the range of 50 μm to 200 μm, and still more preferably in the range of 80 μm to 200 μm. Thus, a compact pressure sensor element 1 can be realized.
此外,电阻区域51的厚度t2优选为处于0.1μm以上且2.0μm以下的范围内,更加优选为处于0.1μm以上且1.0μm以下的范围内,进一步优选为处于0.1μm以上且0.5μm以下的范围内。由此,能够在将隔膜部20设置得极薄的同时,使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的精度较为优异。In addition, the thickness t2 of the resistance region 51 is preferably in the range of 0.1 μm to 2.0 μm, more preferably in the range of 0.1 μm to 1.0 μm, still more preferably in the range of 0.1 μm to 0.5 μm. within range. Accordingly, it is possible to make the diaphragm portion 20 extremely thin, and at the same time displace the resistive region 51 toward the vicinity of the surface of the diaphragm portion 20 , so that the accuracy of the piezoresistive element 5 can be improved.
此外,隔膜部20的覆盖层213a一侧的面和电阻区域51的载流子浓度的峰值位置之间的距离L优选为处于0.05μm以上且0.4μm以下的范围内,更加优选为处于0.1μm以上且0.4μm以下的范围内,进一步优选为处于0.1μm以上且0.3μm以下的范围内。由此,即使将隔膜部20设置得极薄,也能够使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的检测精度较为优异。In addition, the distance L between the surface of the diaphragm portion 20 on the side of the cover layer 213a and the peak position of the carrier concentration of the resistance region 51 is preferably in the range of 0.05 μm to 0.4 μm, more preferably 0.1 μm. It is within the range of 0.4 μm or more, more preferably within the range of 0.1 μm or more and 0.3 μm or less. Thereby, even if the diaphragm part 20 is provided extremely thin, the resistance region 51 can be deviated to the vicinity of the surface of the diaphragm part 20, and the detection accuracy of the piezoresistive element 5 can be made excellent.
此外,覆盖层213a的厚度优选为处于0.05μm以上且0.4μm以下的范围内,更加优选为处于0.05μm以上且0.20μm以下的范围内,进一步优选为处于0.05μm以上且0.10μm以下的范围内。由此,即使将隔膜部20设置得极薄,也能够使电阻区域51偏向隔膜部20的表面附近,并且能够减少噪声向电阻区域51的混入。In addition, the thickness of the covering layer 213a is preferably in the range of 0.05 μm to 0.4 μm, more preferably in the range of 0.05 μm to 0.20 μm, and still more preferably in the range of 0.05 μm to 0.10 μm. . Accordingly, even if the diaphragm portion 20 is made extremely thin, the resistive region 51 can be shifted toward the vicinity of the surface of the diaphragm portion 20 , and the incorporation of noise into the resistive region 51 can be reduced.
以上所说明的压电电阻元件5经由配线214等而构成了桥接电路(惠斯通桥接电路)。在该桥接电路上连接有供给驱动电压的驱动电路(未图示)。而且,该桥接电路输出与压电电阻元件5的电阻值对应的信号(电压)。如此,压电电阻元件5通过形变而产生电信号。The piezoelectric resistance element 5 described above constitutes a bridge circuit (Wheatstone bridge circuit) via the wiring 214 and the like. A drive circuit (not shown) that supplies a drive voltage is connected to the bridge circuit. Furthermore, the bridge circuit outputs a signal (voltage) corresponding to the resistance value of the piezoelectric resistance element 5 . In this way, the piezoresistive element 5 generates an electrical signal through deformation.
在此,多个压电电阻元件5例如被构成为,自然状态下的电阻值彼此相等。Here, the plurality of piezoresistive elements 5 are configured such that resistance values in a natural state are equal to each other, for example.
层压结构体laminated structure
层压结构体6被形成为,在其与前文所述的基板2之间划分形成空洞部S。在此,层压结构体6被配置在隔膜部20的压电电阻元件5侧,并且与隔膜部20(或者基板2)一起划分形成(构成)空洞部S(内部空间)。The laminated structure 6 is formed so that the cavity S is defined between it and the above-mentioned substrate 2 . Here, the laminated structure 6 is disposed on the piezoresistive element 5 side of the diaphragm portion 20 , and defines (constitutes) a hollow portion S (internal space) together with the diaphragm portion 20 (or substrate 2 ).
该层压结构体6具有:以在俯视观察时包围压电电阻元件5的方式而被形成在基板2上的层间绝缘膜61;被形成在层间绝缘膜61上的配线层62;被形成在配线层62以及层间绝缘膜61上的层间绝缘膜63;被形成在层间绝缘膜63上,并具有具备多个细孔642(开孔)的覆盖层641的配线层64;被形成在配线层64以及层间绝缘膜63上的表面保护膜65;被设置在覆盖层641上的密封层66。This laminated structure 6 has: an interlayer insulating film 61 formed on the substrate 2 so as to surround the piezoelectric resistance element 5 in plan view; a wiring layer 62 formed on the interlayer insulating film 61; The interlayer insulating film 63 formed on the wiring layer 62 and the interlayer insulating film 61 ; layer 64 ; a surface protection film 65 formed on the wiring layer 64 and the interlayer insulating film 63 ; and a sealing layer 66 provided on the cover layer 641 .
层间绝缘膜61、63分别由例如硅氧化膜构成。此外,配线层62、64以及密封层66分别由铝等金属构成。此外,密封层66对覆盖层641所具有的细孔642进行密封。此外,表面保护膜65例如为硅氮化膜。The interlayer insulating films 61 and 63 are each made of, for example, a silicon oxide film. In addition, the wiring layers 62 and 64 and the sealing layer 66 are each made of metal such as aluminum. In addition, the sealing layer 66 seals the pores 642 included in the covering layer 641 . In addition, the surface protection film 65 is, for example, a silicon nitride film.
此外,在半导体基板21上及其上方制造有半导体电路9。该半导体电路9具有:MOS晶体管67等有源元件;其他根据需要而形成的电容器、电感器、电阻、二极管、配线(包括与压电电阻元件5连接的配线214、配线层62、64的一部分)等电路元件。在此,MOS晶体管67具有:通过向半导体基板21的上表面掺杂磷、硼等杂质而形成的源极以及漏极(未图示);在形成于该源极与漏极之间的沟道区域上所形成的栅绝缘膜(未图示);在该栅绝缘膜上所形成的栅电极671。Furthermore, the semiconductor circuit 9 is fabricated on and above the semiconductor substrate 21 . This semiconductor circuit 9 has: active elements such as MOS transistor 67; Other capacitors, inductors, resistors, diodes, and wiring (including wiring 214 connected to piezoresistive element 5, wiring layer 62, 64) and other circuit components. Here, the MOS transistor 67 has: a source and a drain (not shown) formed by doping impurities such as phosphorus and boron on the upper surface of the semiconductor substrate 21; and a trench formed between the source and the drain. a gate insulating film (not shown) formed on the channel region; and a gate electrode 671 formed on the gate insulating film.
这种层压结构体6以及半导体电路9能够使用CMOS工艺之类的半导体制造工艺而形成。Such laminated structure 6 and semiconductor circuit 9 can be formed using a semiconductor manufacturing process such as a CMOS process.
如此,由于基板2具有隔膜部20以及半导体电路9,从而能够实现将隔膜部20与半导体电路9集成在一个芯片上的压力传感器元件1。In this way, since the substrate 2 has the diaphragm portion 20 and the semiconductor circuit 9 , it is possible to realize the pressure sensor element 1 in which the diaphragm portion 20 and the semiconductor circuit 9 are integrated on one chip.
通过基板2与层压结构体6而被划分形成的空洞部S为密闭的空间。该空洞部S被设置在隔膜部20的与受压面25相反的一侧,并作为压力基准室而发挥功能,该压力基准室成为压力传感器元件1进行检测的压力的基准值。在本实施方式中,空洞部S成为真空状态(300Pa以下)。通过将空洞部S设为真空状态,能够将压力传感器元件1作为以真空状态为基准而对压力进行检测的“绝对压力传感器”来使用,从而提高了其便利性。The hollow portion S defined by the substrate 2 and the laminated structure 6 is a closed space. The hollow portion S is provided on the side of the diaphragm portion 20 opposite to the pressure receiving surface 25 , and functions as a pressure reference chamber serving as a reference value of the pressure detected by the pressure sensor element 1 . In this embodiment, the hollow part S is in a vacuum state (300 Pa or less). By setting the hollow portion S in a vacuum state, the pressure sensor element 1 can be used as an "absolute pressure sensor" that detects pressure based on the vacuum state, thereby improving its convenience.
不过,空洞部S也可以不为真空状态,而是为大气压,也可以为与大气压相比气压较低的减压状态,还可以为与大气压相比气压较高的加压状态。此外,也可以在空洞部S中封入氮气、稀有气体等惰性气体。However, the hollow portion S may not be in a vacuum state but may be in an atmospheric pressure state, may be in a decompressed state with an air pressure lower than the atmospheric pressure, or may be in a pressurized state with an air pressure higher than the atmospheric pressure. In addition, an inert gas such as nitrogen gas or a rare gas may be filled in the hollow portion S. As shown in FIG.
以上,对压力传感器元件1的结构简单地进行了说明。在这种结构的压力传感器元件1中,如图4(a)所示,隔膜部20根据隔膜部20的受压面25所承受的压力P而发生变形,由此,如图4(b)所示,压电电阻元件5a、5b、5c、5d发生变形,从而压电电阻元件5a、5b、5c、5d的电阻值发生变化。伴随于此,压电电阻元件5a、5b、5c、5d所构成的桥接电路的输出发生变化,根据该输出,能够求出受压面25所承受的压力的大小。The structure of the pressure sensor element 1 has been briefly described above. In the pressure sensor element 1 having such a structure, as shown in FIG. As shown, the piezoresistive elements 5a, 5b, 5c, and 5d are deformed, and the resistance values of the piezoresistive elements 5a, 5b, 5c, and 5d change. Accompanying this, the output of the bridge circuit composed of the piezoresistive elements 5a, 5b, 5c, and 5d changes, and from this output, the magnitude of the pressure received by the pressure receiving surface 25 can be obtained.
如果更加具体地进行说明则为,在产生前文所述那样的隔膜部20的变形之前的自然状态下,例如在压电电阻元件5a、5b、5c、5d的电阻值彼此相等的情况下,压电电阻元件5a、5b的电阻值的乘积与压电电阻元件5c、5d的电阻值的乘积相等,从而桥接电路的输出(电位差)成为零。More specifically, in the natural state before the above-mentioned deformation of the diaphragm portion 20 occurs, for example, when the resistance values of the piezoresistive elements 5a, 5b, 5c, and 5d are equal to each other, the piezoelectric resistance The product of the resistance values of the resistive elements 5a and 5b is equal to the product of the resistance values of the piezoresistive elements 5c and 5d, so that the output (potential difference) of the bridge circuit becomes zero.
另一方面,当产生如前文所述那样的隔膜部20的变形时,如图4(b)所示,在压电电阻元件5a、5b的电阻区域51a、51b会产生沿着其长度方向的压缩变形以及沿着宽度方向的拉伸变形,并且在压电电阻元件5c、5d的电阻区域51c、51d会产生沿着其长度方向的拉伸变形以及沿着其宽度方向的压缩变形。因此,在产生了如前文所述的那样的隔膜部20的变形时,压电电阻元件5a、5b的电阻值与压电电阻元件5c、5d的电阻值之中的一方的电阻值会增加,而另一方的电阻值会减少。On the other hand, when the diaphragm portion 20 is deformed as described above, as shown in FIG. Compressive deformation and tensile deformation along the width direction, and tensile deformation along the longitudinal direction and compressive deformation along the width direction occur in the resistance regions 51c, 51d of the piezoresistive elements 5c, 5d. Therefore, when the deformation of the diaphragm portion 20 occurs as described above, the resistance value of one of the resistance values of the piezoresistor elements 5a, 5b and the resistance values of the piezoresistor elements 5c, 5d increases, On the other hand, the resistance value will decrease.
通过这样的压电电阻元件5a、5b、5c、5d的形变,将产生压电电阻元件5a、5b的电阻值的乘积与压电电阻元件5c、5d的电阻值的乘积之差,与该差相对应的输出(电位差)将从桥接电路输出。根据该来自桥接电路的输出,能够求出受压面25所承受的压力的大小(绝对压力)。Through the deformation of such piezoresistive elements 5a, 5b, 5c, and 5d, the difference between the product of the resistance values of the piezoresistive elements 5a, 5b and the product of the resistance values of the piezoresistive elements 5c, 5d, and the difference The corresponding output (potential difference) will be output from the bridge circuit. From the output from the bridge circuit, the magnitude of the pressure (absolute pressure) received by the pressure receiving surface 25 can be obtained.
在此,由于在产生了如前文所述的那样的隔膜部20的变形时,压电电阻元件5a、5b的电阻值与压电电阻元件5c、5d的电阻值之中的一方的电阻值会增加,而另一方的电阻值会减小,因此能够增大压电电阻元件5a、5b的电阻值的乘积与压电电阻元件5c、5d的电阻值的乘积之差的变化,伴随于此,能够增大来自桥接电路的输出。其结果为,能够提高压力的检测灵敏度。Here, when the deformation of the diaphragm portion 20 occurs as described above, the resistance value of one of the resistance values of the piezoresistor elements 5a, 5b and the resistance values of the piezoresistor elements 5c, 5d will change. increase, and the resistance value of the other side will decrease, so the change in the difference between the product of the resistance values of the piezoresistive elements 5a, 5b and the product of the resistance values of the piezoresistive elements 5c, 5d can be increased, and with this, The output from the bridge circuit can be increased. As a result, the detection sensitivity of pressure can be improved.
通过以如上所说明的方式而被构成的压力传感器元件1,能够在将隔膜部20设置得极薄的同时,使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的检测精度较为优异。此外,由于电阻区域51通过覆盖层213a而被覆盖从而被埋设,因此能够减少噪声向电阻区域51的混入。由此,能够实现压力传感器元件1的小型化以及高精度化。With the pressure sensor element 1 configured as described above, the diaphragm portion 20 can be made extremely thin, and the resistive region 51 can be shifted toward the vicinity of the surface of the diaphragm portion 20, so that the piezoresistive element 5 can The detection accuracy is excellent. In addition, since the resistive region 51 is covered and buried with the cover layer 213 a, it is possible to reduce the mixing of noise into the resistive region 51 . Accordingly, it is possible to realize downsizing and high precision of the pressure sensor element 1 .
此外,以如上所说明的方式而被构成的压力传感器元件1能够使用以下所说明的制造方法来制造。In addition, the pressure sensor element 1 configured as described above can be manufactured using the manufacturing method described below.
压力传感器元件的制造方法Manufacturing method of pressure sensor element
接下来,以前文所述的压力传感器元件1的制造方法为一个示例来对本发明的压力传感器元件的制造方法进行说明。Next, the method of manufacturing the pressure sensor element of the present invention will be described by taking the method of manufacturing the pressure sensor element 1 described above as an example.
图5为表示图1所示的压力传感器元件的制造工序(电阻元件的形成工序)的图,图6为表示图5所示的退火后的电阻元件的载流子浓度分布的一个示例的曲线图。图7为表示图1所示的压力传感器元件的制造工序(绝缘层、电路部等的形成工序)的图。图8为表示图1所示的压力传感器元件的制造工序(压力基准室、隔膜部等的形成工序)的图。5 is a diagram showing the manufacturing process of the pressure sensor element shown in FIG. 1 (the forming process of the resistive element), and FIG. 6 is a graph showing an example of the carrier concentration distribution of the resistive element shown in FIG. 5 after annealing. picture. FIG. 7 is a view showing manufacturing steps (steps of forming an insulating layer, a circuit portion, etc.) of the pressure sensor element shown in FIG. 1 . FIG. 8 is a view showing a manufacturing process of the pressure sensor element shown in FIG. 1 (a forming process of a pressure reference chamber, a diaphragm portion, and the like).
压力传感器元件1的制造方法包括:[1]形成压电电阻元件5的工序;[2]形成绝缘膜22、23的工序;[3]形成层压结构体6以及半导体电路9的工序;[4]形成隔膜部20的工序。The manufacturing method of the pressure sensor element 1 includes: [1] the process of forming the piezoelectric resistance element 5; [2] the process of forming the insulating films 22 and 23; [3] the process of forming the laminated structure 6 and the semiconductor circuit 9; [ 4] A step of forming the diaphragm portion 20 .
以下,依次对各工序进行说明。Hereinafter, each step will be described in order.
[1]形成压电电阻元件的工序(电阻元件的制造方法)[1] Process of forming a piezoresistive element (manufacturing method of a resistive element)
1-1准备基板的工序1-1 Process of preparing substrate
首先,如图5(a)所示,准备半导体基板21,该半导体基板21为,依次层压有由单晶硅构成的硅层211(处理层(handle layer))、由硅氧化膜构成的氧化硅层212(盒层(BOXlayer))、由单晶硅构成的硅层213(装置层(device layer))的SOI基板。First, as shown in FIG. 5( a ), prepare a semiconductor substrate 21 in which a silicon layer 211 (handle layer) made of single crystal silicon and a silicon oxide film are sequentially laminated. An SOI substrate comprising a silicon oxide layer 212 (box layer) and a silicon layer 213 (device layer) made of single crystal silicon.
在本实施方式中,硅层213具有n型的导电型。In this embodiment, the silicon layer 213 has n-type conductivity.
1-2形成电阻区域的工序1-2 Process of forming resistance region
然后,通过向半导体基板21的硅层213(n型的区域)掺杂(离子注入)硼(p型)等杂质,从而如图5(b)所示那样,形成多个电阻区域51以及配线214。Then, by doping (ion implantation) impurities such as boron (p-type) into the silicon layer 213 (n-type region) of the semiconductor substrate 21, as shown in FIG. line 214.
例如,在以+80keV对硼实施离子注入的情况下,将对于压电电阻元件5的离子注入浓度设为1×1014atoms/cm2左右。此外,将对于配线214的离子注入浓度设为与压电电阻元件5相比较高。例如,在以10keV对硼实施离子注入的情况下,将对于配线214的离子注入浓度设为5×1015atoms/cm2左右。For example, when boron is implanted with ions at +80 keV, the ion implantation concentration into the piezoelectric resistance element 5 is set to about 1×10 14 atoms/cm 2 . In addition, the concentration of ion implantation into the wiring 214 is set higher than that of the piezoresistive element 5 . For example, when boron is ion-implanted at 10 keV, the ion implantation concentration into the wiring 214 is set to about 5×10 15 atoms/cm 2 .
1-3热处理工序1-3 heat treatment process
接下来,如图5(c)所示,通过退火来对电阻区域51以及配线214进行热处理。由此,能够使电阻区域51以及配线214活化,并使电阻区域51以及配线214的电特性较为优异。Next, as shown in FIG. 5( c ), the resistance region 51 and the wiring 214 are heat-treated by annealing. Accordingly, the resistance region 51 and the wiring 214 can be activated, and the electrical characteristics of the resistance region 51 and the wiring 214 can be improved.
特别是,在本工序1-3中所使用的退火为快速热退火(Rapid Thermal Anneal:RTA),闪光灯退火(Flash Lamp Anneal:FLA)以及准分子激光退火(Excimer LaserAnneal:ELA)中的任意一种退火(短时间退火)。这些退火均为热预算(热过程)较低的退火。因此,通过使用其中任意一种退火,从而能够减少杂质的扩散。因此,能够减少热处理后的电阻区域51的厚度变厚的情况或者电阻区域51的载流子浓度的峰值位置向较深的位置移动的情况。由此,例如能够如图6所示那样,在将电阻区域51留在较浅的位置的同时,使电阻区域51活化。In particular, the annealing used in this step 1-3 is any one of rapid thermal annealing (Rapid Thermal Anneal: RTA), flash lamp annealing (Flash Lamp Anneal: FLA) and excimer laser annealing (Excimer Laser Anneal: ELA). Kind of annealing (short time annealing). These anneals are all anneals with a low thermal budget (thermal history). Therefore, by using any one of these annealing, it is possible to reduce the diffusion of impurities. Therefore, it is possible to reduce the increase in the thickness of the resistance region 51 after the heat treatment or the shift of the peak position of the carrier concentration of the resistance region 51 to a deeper position. Thereby, for example, as shown in FIG. 6 , the resistive region 51 can be activated while leaving the resistive region 51 at a shallow position.
与此相对,例如在使用通过炉子而实施的炉内退火来实施热处理的情况下,由于热预算(热过程)较高,因此掺杂物容易扩散。因此,热处理后的电阻区域51的厚度的增加、电阻区域51的载流子浓度的峰值位置向较深的位置的移动较大。因此,即使在前文所述的工序1-2中已将电阻区域51形成在较薄且较浅的位置处,也难以形成处于较薄且较浅的位置处的电阻区域51。由于在隔膜部20的厚度较厚的情况下,即使电阻区域51比较厚或处于较深的位置处,也能够使电阻区域51偏向隔膜部20的表面侧,因此不会成为问题,但在隔膜部20的厚度极薄的情况下,则无法使电阻区域51偏向隔膜部20的表面侧,从而难以通过压电电阻元件5实施效率的检测。On the other hand, for example, when heat treatment is performed using furnace annealing performed in a furnace, dopants tend to diffuse because of a high thermal budget (thermal history). Therefore, the increase in the thickness of the resistance region 51 after the heat treatment and the shift of the peak position of the carrier concentration of the resistance region 51 to a deeper position are large. Therefore, even if the resistive region 51 has been formed at a thinner and shallower position in the aforementioned process 1-2, it is difficult to form the resistive region 51 at a thinner and shallower position. When the thickness of the diaphragm part 20 is thick, even if the resistive region 51 is relatively thick or located at a deep position, the resistive region 51 can be deviated to the surface side of the diaphragm part 20, so there is no problem. When the thickness of the portion 20 is extremely thin, the resistive region 51 cannot be shifted toward the surface side of the diaphragm portion 20 , and it is difficult to detect the efficiency by the piezoresistive element 5 .
此外,在本工序1-3的热处理中,将电阻区域51以及配线214加热至1000℃左右。In addition, in the heat treatment in this step 1-3, the resistance region 51 and the wiring 214 are heated to about 1000° C.
此外,在本工序1-3中,热处理后的电阻区域51的厚度t2优选为处于0.1μm以上且2.0μm以下的范围内,更加优选为处于0.1μm以上且1.0μm以下的范围内,进一步优选为处于0.1μm以上且0.5μm以下的范围内。由此,即使将隔膜部20设置得极薄(例如4μm以下),也能够使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的检测精度较为优异。In addition, in this step 1-3, the thickness t2 of the resistance region 51 after the heat treatment is preferably in the range of 0.1 μm to 2.0 μm, more preferably in the range of 0.1 μm to 1.0 μm, and furthermore Preferably, it exists in the range of 0.1 micrometer or more and 0.5 micrometer or less. Accordingly, even if the diaphragm portion 20 is made extremely thin (for example, 4 μm or less), the resistive region 51 can be shifted to the vicinity of the surface of the diaphragm portion 20 , and the detection accuracy of the piezoresistive element 5 can be improved.
此外,在本工序1-3中,热处理后的电阻区域51的载流子浓度的峰值位置与硅层213的表面之间的距离L1优选为处于0.05μm以上且1.0μm以下的范围内,更加优选为处于0.05μm以上且0.5μm以下的范围内,进一步优选为处于0.05μm以上且0.25μm以下的范围内。由此,即使将隔膜部20设置得极薄(例如4μm以下),也能够使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的检测精度较为优异。In addition, in this step 1-3 , the distance L1 between the peak position of the carrier concentration of the resistance region 51 after heat treatment and the surface of the silicon layer 213 is preferably in the range of 0.05 μm or more and 1.0 μm or less, More preferably, it exists in the range of 0.05 micrometer or more and 0.5 micrometer or less, More preferably, it exists in the range of 0.05 micrometer or more and 0.25 micrometer or less. Accordingly, even if the diaphragm portion 20 is made extremely thin (for example, 4 μm or less), the resistance region 51 can be shifted to the vicinity of the surface of the diaphragm portion 20 , and the detection accuracy of the piezoresistive element 5 can be improved.
1-4形成覆盖层的工序1-4 Process of forming the covering layer
接下来,如图5(d)所示,在电阻区域51以及配线214上形成覆盖层213a。Next, as shown in FIG. 5( d ), a cover layer 213 a is formed on the resistance region 51 and the wiring 214 .
覆盖层213a的形成通过使硅进行外延生长而被实施。由此,能够使电阻区域51以及配线214通过覆盖层213a而被覆盖从而被埋设。因此,能够减少噪声向电阻区域51以及配线214的混入。特别是,由于通过外延生长而形成覆盖层213a,因此与专利文献1中所记载的方法不同,能够在将电阻区域51的厚度设置得极薄的同时,将电阻区域51埋设在极浅的位置处。The formation of the capping layer 213a is carried out by epitaxially growing silicon. Thereby, the resistive region 51 and the wiring 214 can be covered and buried with the cover layer 213a. Therefore, it is possible to reduce the mixing of noise into the resistance region 51 and the wiring 214 . In particular, since the capping layer 213a is formed by epitaxial growth, unlike the method described in Patent Document 1, the thickness of the resistance region 51 can be made extremely thin, and the resistance region 51 can be buried at an extremely shallow position. place.
此外,作为在本工序1-4中实施的外延生长所使用的原料气体,虽然未被特别限定,但可列举出例如乙硅烷(Si2H6)气体、二氯硅烷(SiH2Cl2)气体等,优选为使用乙硅烷气体。通过使用乙硅烷气体来实施外延生长,从而能够在较低的温度(450℃左右)下形成覆盖层213a。因此,能够在形成覆盖层213a的工序1-4中,减少电阻区域51扩散的情况。In addition, although the source gas used for the epitaxial growth in this step 1-4 is not particularly limited, examples thereof include disilane (Si 2 H 6 ) gas, dichlorosilane (SiH 2 Cl 2 ) As the gas, it is preferable to use disilane gas. By performing epitaxial growth using disilane gas, the capping layer 213 a can be formed at a relatively low temperature (about 450° C.). Therefore, it is possible to reduce the diffusion of the resistance region 51 in the step 1-4 of forming the cover layer 213a.
此外,在实施外延生长时,通过将例如磷等成为掺杂物的气体适当地混合到原料气体中,从而能够形成所需的导电型(n型)或导电率的覆盖层213a。另外,在形成p型的覆盖层213a的情况下,例如只需将硼等的气体混合到原料气体中即可。In addition, when epitaxial growth is performed, for example, a dopant gas such as phosphorus is appropriately mixed into the source gas to form the cladding layer 213a of a desired conductivity type (n-type) or conductivity. In addition, in the case of forming the p-type cladding layer 213a, for example, it is only necessary to mix a gas such as boron into the source gas.
此外,在本工序1-4中,覆盖层213a的厚度优选为处于0.05μm以上且0.4μm以下的范围内,更加优选为处于0.05μm以上且0.3μm以下的范围内,进一步优选为处于0.1μm以上且0.2μm以下的范围内。由此,即使将隔膜部20设置得极薄,也能够使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的检测精度较为优异。In addition, in this step 1-4, the thickness of the covering layer 213a is preferably in the range of 0.05 μm to 0.4 μm, more preferably in the range of 0.05 μm to 0.3 μm, still more preferably 0.1 μm In the range of above and below 0.2 μm. Thereby, even if the diaphragm part 20 is provided extremely thin, the resistance region 51 can be deviated to the vicinity of the surface of the diaphragm part 20, and the detection accuracy of the piezoresistive element 5 can be made excellent.
根据以上那样的压电电阻元件5的制造方法,由于通过快速热退火、闪光灯退火以及准分子激光退火中的任意一种退火来对电阻区域51进行热处理,因此热预算(热过程)较低,从而能够在减少杂质的扩散而将电阻区域51留在较浅的位置的同时,使电阻区域51活化。此外,由于在所得到的压电电阻元件5中,电阻区域51通过覆盖层213a而被覆盖从而被埋设,因此能够减少噪声向电阻区域51的混入。特别是,由于通过外延生长而形成覆盖层213a,因此能够在将电阻区域51的厚度设置得极薄的同时,将电阻区域51埋设在极浅的位置处。According to the manufacturing method of the piezoelectric resistance element 5 as above, since the resistance region 51 is heat-treated by any one of rapid thermal annealing, flash lamp annealing, and excimer laser annealing, the thermal budget (thermal history) is low, Accordingly, the resistance region 51 can be activated while reducing the diffusion of impurities and leaving the resistance region 51 at a shallow position. In addition, in the obtained piezoresistive element 5 , since the resistance region 51 is covered and buried with the cover layer 213 a , it is possible to reduce the mixing of noise into the resistance region 51 . In particular, since the capping layer 213a is formed by epitaxial growth, the resistance region 51 can be buried at an extremely shallow position while making the thickness of the resistance region 51 extremely thin.
[2]形成绝缘膜22、23的工序[2] Step of forming insulating films 22 and 23
接下来,如图7(a)所示,在硅层213上依次形成绝缘膜22以及绝缘膜23。Next, as shown in FIG. 7( a ), an insulating film 22 and an insulating film 23 are sequentially formed on the silicon layer 213 .
绝缘膜22、23的形成能够分别通过例如溅射法、CVD(Chemical VaporDeposition:化学气相沉积)法等来实施。The formation of insulating films 22 and 23 can be performed by, for example, sputtering, CVD (Chemical Vapor Deposition: Chemical Vapor Deposition) or the like.
[3]形成层压结构体6以及半导体电路9的工序[3] Step of forming laminated structure 6 and semiconductor circuit 9
3-1MOS晶体管67的形成3-1 Formation of MOS transistor 67
接下来,如图7(b)所示,在硅层213上形成MOS晶体管67。Next, as shown in FIG. 7( b ), a MOS transistor 67 is formed on the silicon layer 213 .
在此,MOS晶体管67的形成能够使用公知的半导体制造工艺来实施。Here, the formation of the MOS transistor 67 can be implemented using a known semiconductor manufacturing process.
3-2层间绝缘膜与配线层形成工序3-2 Interlayer insulating film and wiring layer formation process
接下来,如图7(c)所示,以对绝缘膜23以及MOS晶体管67等进行覆盖的方式而依次形成牺牲层41、配线层62、牺牲层42、配线层64以及表面保护膜65。Next, as shown in FIG. 7(c), a sacrificial layer 41, a wiring layer 62, a sacrificial layer 42, a wiring layer 64, and a surface protection film are sequentially formed to cover the insulating film 23, the MOS transistor 67, and the like. 65.
该牺牲层41、42各自的一部分通过后文叙述的空洞部形成工序而被去除,残留部分成为层间绝缘膜61、63。牺牲层41、42的形成分别通过如下方式而实施,即,利用溅射法、CVD法等形成硅氧化膜,并利用蚀刻而对该硅氧化膜进行图案形成。A part of each of the sacrificial layers 41 and 42 is removed by a cavity forming step described later, and the remaining parts become interlayer insulating films 61 and 63 . The formation of the sacrificial layers 41 and 42 is performed by forming a silicon oxide film by a sputtering method, a CVD method, or the like, and patterning the silicon oxide film by etching.
此外,牺牲层41、42各自的厚度不被特别地限定,例如设为1500nm以上且5000nm以下的程度。In addition, the respective thicknesses of the sacrificial layers 41 and 42 are not particularly limited, and are, for example, about 1500 nm or more and 5000 nm or less.
此外,配线层62、64的形成分别通过如下方式而实施,即,在利用溅射法、CVD法等而形成了例如由铝等构成的层之后,对该层进行图案形成。In addition, the formation of the wiring layers 62 and 64 is carried out by forming a layer made of, for example, aluminum or the like by a sputtering method, a CVD method, or the like, and then patterning the layer.
在此,配线层62、64各自的厚度不被特别地限定,例如设为300nm以上且900nm以下的程度。Here, the respective thicknesses of the wiring layers 62 and 64 are not particularly limited, and are, for example, about 300 nm or more and 900 nm or less.
由这种牺牲层41、42以及配线层62、64构成的层压结构使用通常的CMOS工艺而形成,其层压数根据需要而被适当地设定。即,有时也会根据需要而层压更多的牺牲层或配线层。A laminated structure composed of such sacrificial layers 41, 42 and wiring layers 62, 64 is formed using a normal CMOS process, and the number of laminations is appropriately set as necessary. That is, more sacrificial layers or wiring layers may be laminated as necessary.
此外,表面保护膜65的形成例如能够通过溅射法、CVD法等来实施。由此,在实施后文叙述的工序3-3中的蚀刻时,能够对牺牲层41、42的成为层间绝缘膜61、63的部分进行保护。作为表面保护膜65的构成材料,可列举出例如硅氧化膜、硅氮化膜、聚酰亚胺膜、环氧树脂膜等具有用于从水分、灰尘、损伤等中保护元件的耐性的材料,特别优选为硅氮化膜。虽然未进行图示,但在形成具有前文所述的硅氧化膜以及硅氮化膜的表面保护膜65时,通过如下方式而形成,即,在以相同的方式而依次形成了硅氧化膜以及硅氮化膜之后,对这些层进行图案形成。表面保护膜65的厚度不被特别限定,例如设为500nm以上且2000nm以下的程度。In addition, the formation of the surface protection film 65 can be implemented by a sputtering method, a CVD method, etc., for example. Thereby, when performing the etching in the process 3-3 mentioned later, the part which becomes the interlayer insulating film 61, 63 of the sacrificial layer 41, 42 can be protected. As a constituent material of the surface protection film 65, for example, a silicon oxide film, a silicon nitride film, a polyimide film, an epoxy resin film, etc., have resistance to protect the element from moisture, dust, damage, etc. , particularly preferably a silicon nitride film. Although not shown in the figure, when forming the surface protection film 65 having the aforementioned silicon oxide film and silicon nitride film, it is formed in such a manner that the silicon oxide film and the silicon nitride film are sequentially formed in the same manner. After the silicon nitride film, these layers are patterned. The thickness of the surface protection film 65 is not particularly limited, and is, for example, about 500 nm or more and 2000 nm or less.
3-3空洞部形成工序3-3 Cavity Formation Process
接下来,通过去除牺牲层41、42的一部分,从而如图8(a)所示那样,在绝缘膜23与覆盖层641之间形成空洞部S(空腔)。由此,形成了层间绝缘膜61、63。Next, by removing part of the sacrificial layers 41 and 42 , as shown in FIG. 8( a ), a cavity S (cavity) is formed between the insulating film 23 and the cover layer 641 . Thus, interlayer insulating films 61 and 63 are formed.
空洞部S的形成通过如下的方式而实施,即,利用穿过被形成于覆盖层641上的多个细孔642的蚀刻而将牺牲层41、42的一部分去除。在此,在作为所涉及的蚀刻而使用了湿蚀刻的情况下,从多个细孔642供给氟酸、缓冲氟酸等蚀刻液,而在使用了干蚀刻的情况下,从多个细孔642供给氢氟酸气体等蚀刻气体。在实施这种蚀刻时,绝缘膜23作为蚀刻停止层而发挥功能。此外,由于绝缘膜23具有相对于蚀刻液的耐性,因此还具有从蚀刻液中保护相对于绝缘膜23而靠下侧的结构部(例如绝缘膜22、压电电阻元件5、配线214等)的功能。The formation of the hollow portion S is performed by removing a part of the sacrificial layers 41 , 42 by etching through the plurality of pores 642 formed in the cover layer 641 . Here, when wet etching is used as the etching, an etchant such as hydrofluoric acid or buffered hydrofluoric acid is supplied from the plurality of pores 642, and when dry etching is used, an etching solution such as hydrofluoric acid is supplied from the plurality of pores 642. 642 supplies etching gas such as hydrofluoric acid gas. When performing such etching, the insulating film 23 functions as an etching stopper layer. In addition, since the insulating film 23 has resistance to the etching solution, it also has the function of protecting the structural parts (such as the insulating film 22, the piezoresistive element 5, the wiring 214, etc.) on the lower side with respect to the insulating film 23 from the etching solution. ) function.
3-4密封工序3-4 Sealing process
接下来,如图8(b)所示,在覆盖层641上,通过溅射法、CVD法等而形成由硅氧化膜、硅氮化膜、Al、Cu、W、Ti、TiN等的金属膜等构成的密封层66,从而对各细孔642进行密封。由此,空洞部S通过密封层66而被密封,从而获得了层压结构体6。Next, as shown in FIG. 8(b), on the cover layer 641, a silicon oxide film, a silicon nitride film, a metal layer such as Al, Cu, W, Ti, TiN, etc. are formed by sputtering, CVD, or the like. The sealing layer 66 made of a film or the like is used to seal the pores 642 . As a result, the hollow part S is sealed by the sealing layer 66, and the laminated structure 6 is obtained.
在此,密封层66的厚度不被特别限定,例如设为1000nm以上且5000nm以下的程度。Here, the thickness of the sealing layer 66 is not particularly limited, and is, for example, about 1000 nm to 5000 nm.
[4]形成隔膜部20的工序[4] Step of forming the diaphragm portion 20
接下来,在根据需要而对硅层211的下表面进行了磨削之后,通过蚀刻而去除(加工)硅层211的下表面(一面侧)的一部分,从而如图8(c)所示那样,形成凹部24。由此形成了隔膜部20。Next, after grinding the lower surface of the silicon layer 211 as necessary, a part of the lower surface (one surface side) of the silicon layer 211 is removed (processed) by etching, thereby as shown in FIG. 8( c ). , forming the concave portion 24 . Thus, the diaphragm portion 20 is formed.
在此,在对硅层211的下表面的一部分进行去除时,氧化硅层212作为蚀刻停止层而发挥功能。由此,能够较高精度地规定隔膜部20的厚度。Here, when a part of the lower surface of the silicon layer 211 is removed, the silicon oxide layer 212 functions as an etching stopper layer. Accordingly, the thickness of the diaphragm portion 20 can be specified with high accuracy.
另外,作为对硅层211的下表面的一部分进行去除的方法,既可以为干蚀刻,也可以为湿蚀刻等。In addition, as a method of removing a part of the lower surface of the silicon layer 211 , dry etching or wet etching may be used.
通过以上那样的工序,能够制造出压力传感器元件1。Through the above steps, the pressure sensor element 1 can be manufactured.
根据以上所说明的压力传感器元件1的制造方法,在所获得的压力传感器元件1中,即使将隔膜部20设置得极薄,也能够使电阻区域51偏向隔膜部20的表面附近,从而能够使压电电阻元件5的检测精度较为优异。此外,由于在所获得的压力传感器元件1中,电阻区域51通过覆盖层213a而被覆盖从而被埋设,因此能够减少噪声向电阻区域51的混入。由此,能够实现所获得的压力传感器元件1的小型化以及高精度化。According to the manufacturing method of the pressure sensor element 1 described above, in the obtained pressure sensor element 1, even if the diaphragm portion 20 is provided extremely thin, the resistance region 51 can be deviated to the vicinity of the surface of the diaphragm portion 20, and the The detection accuracy of the piezoelectric resistance element 5 is excellent. In addition, in the obtained pressure sensor element 1 , since the resistance region 51 is covered and buried with the cover layer 213 a, it is possible to reduce the mixing of noise into the resistance region 51 . Thereby, miniaturization and high precision of the obtained pressure sensor element 1 can be achieved.
第二实施方式second embodiment
图9为表示本发明的第二实施方式所涉及的压力传感器元件的剖视图。9 is a cross-sectional view showing a pressure sensor element according to a second embodiment of the present invention.
本实施方式的压力传感器元件除了压力基准室的结构(配置)有所不同之外,均与前文所述的第一实施方式相同。The pressure sensor element of the present embodiment is the same as that of the first embodiment described above except for the difference in the structure (arrangement) of the pressure reference chamber.
另外,在以下的说明中,关于第二实施方式,以与前文所述的实施方式的不同点为中心来进行说明,关于相同的事项则省略其说明。此外,在图9中,对于与前文所述的实施方式相同的结构标注相同的符号。In addition, in the following description, regarding the second embodiment, differences from the above-described embodiment will be mainly described, and descriptions of the same items will be omitted. In addition, in FIG. 9, the same code|symbol is attached|subjected to the structure similar to embodiment mentioned above.
在图9所示的压力传感器元件1A中,代替第一实施方式的层压结构体6而具备与基板2一起形成了空洞部S1(压力基准室)的基板3。在此,基板3将基板2的开口堵塞并被接合在基板2的下表面(硅层211的表面)上。以此方式,通过利用基板3来对凹部24进行气密性的密封而形成作为压力基准室的空洞部S1。此外,作为基板3,只要能够形成作为压力基准室而发挥功能的空洞部S1,则其不会被特别限定,例如能够使用硅基板、玻璃基板、陶瓷基板等。此外,基板3以其隔着空洞部S1而与隔膜部20对置的部分不会由于差压而变形的方式,相对于隔膜部20而成为足够厚。In a pressure sensor element 1A shown in FIG. 9 , a substrate 3 in which a cavity S1 (pressure reference chamber) is formed together with a substrate 2 is provided instead of the laminated structure 6 of the first embodiment. Here, the substrate 3 closes the opening of the substrate 2 and is bonded to the lower surface of the substrate 2 (the surface of the silicon layer 211 ). In this way, the hollow portion S1 serving as the pressure reference chamber is formed by hermetically sealing the concave portion 24 with the substrate 3 . In addition, the substrate 3 is not particularly limited as long as the cavity S1 functioning as a pressure reference chamber can be formed, and for example, a silicon substrate, a glass substrate, a ceramic substrate, or the like can be used. In addition, the substrate 3 is sufficiently thick with respect to the diaphragm portion 20 so that the portion of the substrate 3 facing the diaphragm portion 20 across the hollow portion S1 is not deformed by the differential pressure.
在此,由于在本实施方式中,如前文所述,在基板2的硅层211侧设置有作为压力基准室而发挥功能的空洞部S1,因此隔膜部20的与空洞部S1相反的一侧的面成为受压面25A。Here, in the present embodiment, as described above, the hollow portion S1 functioning as the pressure reference chamber is provided on the side of the silicon layer 211 of the substrate 2, so the side of the diaphragm portion 20 opposite to the hollow portion S1 is The surface becomes the pressure receiving surface 25A.
另外,在图9中,虽然省略了电路部的图示,但也可以设置与前文所述的第一实施方式的半导体电路9相同的电路部,也可以在压力传感器元件1A的外部设置电路部。In addition, in FIG. 9, although the illustration of the circuit part is omitted, the same circuit part as the semiconductor circuit 9 of the first embodiment described above may be provided, and the circuit part may be provided outside the pressure sensor element 1A. .
通过以上所说明的第二实施方式,也与第一实施方式同样地能够在将隔膜部20设置得极薄的同时,使电阻区域51偏向隔膜部20的表面附近,并能够使压电电阻元件5的检测精度较为优异。此外,由于电阻区域51通过覆盖层213a而被覆盖从而被埋设,因此能够减少噪音向电阻区域51的混入。由此,能够实现压力传感器元件1A的小型化以及高精度化。According to the second embodiment described above, as in the first embodiment, the diaphragm portion 20 can be provided extremely thin, and the resistance region 51 can be shifted toward the vicinity of the surface of the diaphragm portion 20, and the piezoresistive element can be made The detection accuracy of 5 is relatively excellent. In addition, since the resistive region 51 is buried by being covered with the cover layer 213 a, it is possible to reduce the mixing of noise into the resistive region 51 . Accordingly, it is possible to achieve downsizing and high precision of the pressure sensor element 1A.
2.压力传感器2. Pressure sensor
接下来,对具备本发明的压力传感器元件的压力传感器(本发明的压力传感器)进行说明。图10为表示本发明的压力传感器的一个示例的剖视图。Next, a pressure sensor including the pressure sensor element of the present invention (pressure sensor of the present invention) will be described. Fig. 10 is a cross-sectional view showing an example of the pressure sensor of the present invention.
如图10所示,本发明的压力传感器100具备:压力传感器元件1;对压力传感元件1进行收纳的框体101;将从压力传感器元件1所获得的信号运算为压力数据的运算部102。压力传感器元件1经由配线103而与运算部102电连接。As shown in FIG. 10 , the pressure sensor 100 of the present invention includes: a pressure sensor element 1; a housing 101 for accommodating the pressure sensor element 1; and a calculation unit 102 for calculating a signal obtained from the pressure sensor element 1 into pressure data . The pressure sensor element 1 is electrically connected to the computing unit 102 via wiring 103 .
压力传感器元件1通过未图示的固定单元而被固定在框体101的内侧。此外,在框体101中,具有用于使压力传感器元件1的隔膜部20与例如大气(框体101的外侧)连通的贯穿孔104。The pressure sensor element 1 is fixed inside the housing 101 by a fixing unit not shown. In addition, the housing 101 has a through hole 104 for communicating the diaphragm portion 20 of the pressure sensor element 1 with, for example, the atmosphere (outside of the housing 101 ).
根据这种压力传感器100,隔膜部20经由贯穿孔104而承受压力。将由于该受压而从压力传感器元件1输出的信号经由配线103而向运算部102发送,并对压力数据进行运算。该被运算出的压力数据能够经由未图示的显示部(例如,个人计算机的显示器等)而被显示。According to such a pressure sensor 100 , the diaphragm portion 20 receives pressure through the through hole 104 . The signal output from the pressure sensor element 1 due to this pressure is sent to the calculation unit 102 via the wiring 103, and the pressure data is calculated. The calculated pressure data can be displayed via an unillustrated display unit (for example, a display of a personal computer, etc.).
3.高度计3. Altimeter
接下来,对具备本发明的压力传感器元件的高度计(本发明的高度计)的一个示例进行说明。图11为表示本发明的高度计的一个示例的立体图。Next, an example of an altimeter including the pressure sensor element of the present invention (altimeter of the present invention) will be described. Fig. 11 is a perspective view showing an example of the altimeter of the present invention.
高度计200能够像手表那样佩戴在手腕上。此外,在高度计200的内部搭载有压力传感器元件1(压力传感器100),在显示部201上能够显示所在地的海拔高度或所在地的气压等。The altimeter 200 can be worn on the wrist like a watch. In addition, the pressure sensor element 1 (pressure sensor 100 ) is mounted inside the altimeter 200 , and the altitude of the location or the atmospheric pressure of the location can be displayed on the display unit 201 .
另外,在该显示部201上能够显示当前时刻、使用者的心搏数、天气等各种信息。In addition, various information such as the current time, the user's heart rate, and weather can be displayed on the display unit 201 .
4.电子设备4. Electronic equipment
接下来,对应用了具备本发明的压力传感器元件的电子设备的导航系统进行说明。图12为表示本发明的电子设备的一个示例的主视图。Next, a navigation system to which an electronic device including the pressure sensor element of the present invention is applied will be described. Fig. 12 is a front view showing an example of the electronic device of the present invention.
在导航系统300中具备:未图示的地图信息;从GPS(全球定位系统:GlobalPositioning System)取得位置信息的位置信息取得单元;基于陀螺传感器、加速度传感器与车速数据的自主导航单元;压力传感器元件1;对预定的位置信息或行进道路信息进行显示的显示部301。The navigation system 300 includes: map information not shown in the figure; a position information acquisition unit that acquires position information from GPS (Global Positioning System: Global Positioning System); an autonomous navigation unit based on gyro sensor, acceleration sensor, and vehicle speed data; and a pressure sensor element. 1. A display unit 301 that displays predetermined position information or travel route information.
根据该导航系统,不仅能够取得位置信息,还能够取得高度信息。例如,当行驶于与一般道路在位置信息上表示大致相同的位置的高架道路时,如果不具备高度信息,则无法通过导航系统而判断出是行驶在一般道路上还是行驶在高架道路上,从而将一般道路的信息作为优先信息而提供给使用者。因此,在本实施方式所涉及的导航系统300中,能够通过压力传感器元件1而取得高度信息,从而能够对由于从一般道路进入高架道路而产生的高度变化进行检测,并将高架道路的行驶状态下的导航信息提供给使用者。According to this navigation system, not only positional information but also altitude information can be acquired. For example, when driving on an elevated road whose location information indicates approximately the same position as a general road, if there is no altitude information, it is impossible to determine whether to drive on a general road or an elevated road through the navigation system, thereby The general road information is provided to the user as priority information. Therefore, in the navigation system 300 according to the present embodiment, height information can be obtained through the pressure sensor element 1, thereby detecting a change in height due to entering an elevated road from a general road, and estimating the driving state of the elevated road. The following navigation information is provided to the user.
另外,显示部301成为例如液晶面板显示器、有机EL(Organic Electro-Luminescence:有机电致发光)显示器等能够实现小型且薄型化的结构。In addition, the display unit 301 has a structure capable of reducing the size and thickness, such as a liquid crystal panel display or an organic EL (Organic Electro-Luminescence: organic electroluminescence) display.
另外,具备本发明的压力传感器元件的电子设备并不限定于上述的设备,例如能够应用于个人计算机、移动电话、医疗设备(例如电子体温计、血压计、血糖计、心电图计测装置、超声波诊断装置、电子内窥镜)、各种测量设备、计量仪器类(例如车辆、飞机、船舶的计量仪器类)、飞行模拟器等中。In addition, electronic equipment equipped with the pressure sensor element of the present invention is not limited to the above-mentioned equipment, for example, it can be applied to personal computers, mobile phones, medical equipment (such as electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring equipment, ultrasonic diagnostic equipment, etc.) Devices, electronic endoscopes), various measuring equipment, measuring instruments (such as measuring instruments for vehicles, aircraft, and ships), flight simulators, etc.
5.移动体5. Moving body
接下来,对应用了本发明的压力传感器元件的移动体(本发明的移动体)进行说明。图13为表示本发明的移动体的一个示例的立体图。Next, a moving body to which the pressure sensor element of the present invention is applied (moving body of the present invention) will be described. Fig. 13 is a perspective view showing an example of the moving body of the present invention.
如图13所示,移动体400具有车身401和四个车轮402,并被构成为通过被设置于车身401中的未图示的动力源(发动机)而使车轮402进行旋转。在这种移动体400中内置有导航系统300(压力传感器元件1)。As shown in FIG. 13 , the mobile body 400 has a vehicle body 401 and four wheels 402 , and is configured to rotate the wheels 402 by a power source (engine) not shown provided in the vehicle body 401 . A navigation system 300 (pressure sensor element 1 ) is built in such a mobile body 400 .
以上,虽然根据图示的各实施方式而对本发明的压力传感器元件、压力传感器、高度计、电子设备以及移动体进行了说明,但本发明并不限定于此,各部分的结构能够置换为具有相同的功能的任意的结构。此外,也可以附加其他任意的结构物。As mentioned above, although the pressure sensor element, the pressure sensor, the altimeter, the electronic device, and the moving body of the present invention have been described based on the illustrated embodiments, the present invention is not limited thereto, and the structures of the respective parts can be replaced with those having the same structure. Arbitrary structure of functions. In addition, other arbitrary structures may be added.
此外,对于设置在一个隔膜部中的压电电阻元件(功能元件)的数目,虽然在前文所述的实施方式中以四个的情况为例而进行了说明,但并不限定于此,例如,也可以为一个以上且三个以下,或者为五个以上。此外,压电电阻元件的配置与形状等也不限定于前文所述的实施方式,例如也可以在前文所述的实施方式中,将压电电阻元件配置在隔膜部的中央部处。In addition, although the number of piezoresistive elements (functional elements) provided in one diaphragm portion was described as an example of four in the above-mentioned embodiment, it is not limited thereto. For example, , may be more than one and less than three, or may be more than five. In addition, the arrangement and shape of the piezoresistive elements are not limited to the above-mentioned embodiments, and for example, the piezoresistor elements may be arranged at the center of the diaphragm in the above-mentioned embodiments.
符号说明Symbol Description
1:压力传感器元件;1A:压力传感器元件;2:基板;3:基板;5:压电电阻元件;5a:压电电阻元件;5b:压电电阻元件;5c:压电电阻元件;5d:压电电阻元件;6:层压结构体;9:半导体电路;20:隔膜部;21:半导体基板;22:绝缘膜;23:绝缘膜;24:凹部;25:受压面;25A:受压面;41:牺牲层;42:牺牲层;51:电阻区域;51a:电阻区域;51b:电阻区域;51c:电阻区域;51d:电阻区域;61:层间绝缘膜;62:配线层;63:层间绝缘膜;64:配线层;65:表面保护膜;66:密封层;67:MOS晶体管;100:压力传感器;101:框体;102:运算部;103:配线;104:贯穿孔;200:高度计;201:显示部;211:硅层;212:氧化硅层;213:硅层;213a:覆盖层;214:配线;214a:配线;214b:配线;214c:配线;214d:配线;300:导航系统;301:显示部;400:移动体;401:车身;402:车轮;641:覆盖层;642:细孔;671:栅电极;L:距离;L1:距离;P:压力;t1:厚度;t2:厚度;S:空洞部;S1:空洞部;w:宽度。1: pressure sensor element; 1A: pressure sensor element; 2: substrate; 3: substrate; 5: piezoresistive element; 5a: piezoresistive element; 5b: piezoresistive element; 5c: piezoresistive element; Piezoelectric resistance element; 6: laminated structure; 9: semiconductor circuit; 20: diaphragm part; 21: semiconductor substrate; 22: insulating film; 23: insulating film; 24: concave part; 25: pressure receiving surface; 25A: receiving Pressure surface; 41: sacrificial layer; 42: sacrificial layer; 51: resistance area; 51a: resistance area; 51b: resistance area; 51c: resistance area; 51d: resistance area; 61: interlayer insulating film; 62: wiring layer ;63: interlayer insulation film; 64: wiring layer; 65: surface protection film; 66: sealing layer; 67: MOS transistor; 100: pressure sensor; 101: frame; 102: computing unit; 103: wiring; 104: through hole; 200: altimeter; 201: display part; 211: silicon layer; 212: silicon oxide layer; 213: silicon layer; 213a: cover layer; 214: wiring; 214a: wiring; 214b: wiring; 214c: wiring; 214d: wiring; 300: navigation system; 301: display unit; 400: moving body; 401: vehicle body; 402: wheel; 641: covering layer; 642: pores; 671: grid electrode; L: distance; L 1 : distance; P: pressure; t 1 : thickness; t 2 : thickness; S: cavity; S1: cavity; w: width.
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