CN106356330B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN106356330B CN106356330B CN201510423235.6A CN201510423235A CN106356330B CN 106356330 B CN106356330 B CN 106356330B CN 201510423235 A CN201510423235 A CN 201510423235A CN 106356330 B CN106356330 B CN 106356330B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of forming method of semiconductor structure, comprising: provide substrate, the substrate surface is formed with dielectric layer；The dielectric layer that removal first thickness is etched using the first etching technics forms pre- opening in the dielectric layer；Using depositing operation, in the pre- open bottom and sidewall surfaces deposited silicon layer；Using the second etching technics, etching removal is located at the silicon layer on the pre- open bottom surface, and etches the dielectric layer that removal is located at the second thickness of pre- opening lower section；Depositing operation described in repetitive cycling, the second etching technics, until forming the opening for running through the dielectric layer, the open bottom exposes substrate surface；Form the conductive layer for filling the full opening.The present invention improves the opening sidewalls pattern to be formed, to improve the breakdown voltage for the semiconductor structure to be formed, improves time correlation dielectric breakdown problem.
Description
Technical field
The present invention relates to semiconductor fabrication techniques field, in particular to a kind of forming method of semiconductor structure.
Background technique
With being constantly progressive for super large-scale integration technology, the characteristic size of semiconductor devices constantly reduces,
Chip area persistently increases, and the delay time of interconnection structure can be compared with the device gate delay time.People are faced with
Rapidly growth and bring RC (R refers to that resistance, C refer to capacitor) due to connection length is how overcome to postpone the problem of dramatically increasing.
Especially because the influence of hardware cloth line capacitance is got worse, device performance sharp fall is caused, semiconductor is had become
The key restriction factors that industry further develops.In order to reduce RC retardation ratio caused by interconnection, many kinds of measures has been used.
Parasitic capacitance and interconnection resistance between interconnection structure cause the transmission delay of signal.Since copper is with lower
Resistivity, superior electromigration resistance properties and high reliability can reduce the interconnection resistance of metal, and then reduce total interconnection
Postpone effect, low-resistance copper-connection is changed by conventional aluminium interconnection.The capacitor reduced between interconnection simultaneously equally may be used
To reduce delay, and parasitic capacitance C is proportional to the relative dielectric constant k of circuit layer dielectric, thus use low-k materials as
The dielectric of different circuit layers replaces traditional SiO2Medium has become the needs for meeting the development of high-speed chip.
However, the electric property for the semiconductor structure that the prior art is formed is still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, improves the opening sidewalls shape of formation
Looks, to improve the breakdown voltage of semiconductor structure, improve semiconductor structure with time correlation dielectric breakdown problem.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
Substrate surface is formed with dielectric layer；The dielectric layer that removal first thickness is etched using the first etching technics, in the dielectric layer
Form pre- opening；Using depositing operation, in the pre- open bottom and sidewall surfaces deposited silicon layer；Using the second etching technics,
Etching removal is located at the silicon layer on the pre- open bottom surface, exposes the pre- open bottom；Continue using the second etching work
Skill, etching removal are located at the dielectric layer of the second thickness below the pre- open bottom exposed；It is deposited described in repetitive cycling
Technique, the second etching technics, until forming the opening for running through the dielectric layer, the open bottom exposes substrate surface；Shape
At the conductive layer for filling the full opening.
Optionally, second etching technics is greater than to pre- open side the etch rate of the silicon layer on pre- open bottom surface
The etch rate of the silicon layer of wall surface.
Optionally, the method for forming the silicon layer includes: to be placed on place by the substrate and with the medium being open in advance
It manages in chamber, and processing chamber housing inner-wall material includes silicon；Plasma, work of the plasma in DC offset voltage are provided
With lower bombardment processing chamber inner wall, the silicon atom of processing chamber housing inner wall is made to fall off, the silicon atom to fall off is attached to pre- opening
Bottom surface and sidewall surfaces, form the silicon layer.
Optionally, the etch chamber of the etching cavity of the processing chamber housing and first etching technics, the second etching technics
Room is the same chamber.
Optionally, the technological parameter of the silicon layer is formed are as follows: N2Flow is 50sccm to 500sccm, and Ar flow is
50sccm to 500sccm, processing chamber housing pressure are 5 millitorrs to 200 millitorrs, and plasma rf power is 50 watts to 1000 watts,
Biasing radio-frequency power is 0 watt to 200 watts, and DC offset voltage is -100V to -1000V.
Optionally, the silicon layer with a thickness of 5 angstroms to 50 angstroms.
Optionally, the opening includes the through-hole and groove being intertwined, wherein the through-hole is located at groove and substrate
Between, and the width dimensions of the through-hole are less than the width dimensions of groove.
Optionally, the processing step for forming the pre- opening includes: to form the first mask layer, institute in the dielectric layer surface
It states and is formed with the first groove for exposing certain media layer surface in the first mask layer；Then it is formed and is covered in the first mask layer table
It is recessed to be formed with second in second mask layer for second mask layer of the certain media layer surface that face and the first groove expose
Slot, and the width dimensions of second groove are less than the width dimensions of the first groove；Using second mask layer as exposure mask, etching
The dielectric layer of first thickness is removed, the pre- opening is formed.
Optionally, the first thickness is more than or equal to the 75% of thickness of dielectric layers and is less than or equal to thickness of dielectric layers
90%.
Optionally, using first mask layer as exposure mask, second etching technics is carried out, second etching technics is also
Etch the dielectric layer that the first mask layer exposes.
Optionally, the dielectric layer top surface that the silicon layer is also located at the first exposure mask layer surface, the first mask layer exposes；
Second etching technics also etches at the top of the dielectric layer that removal is located at the first exposure mask layer surface and the first mask layer exposes
The silicon layer on surface.
Optionally, before the silicon layer on the pre- opening sidewalls surface is removed by complete etching, stop second etching
Technique.
Optionally, when the silicon layer on the pre- opening sidewalls surface is by complete etching removal, stop the second etching work
Skill.
Optionally, the technological parameter of second etching technics are as follows: CH4Flow is 50sccm to 500sccm, CHF3Flow
For 50sccm to 500sccm, N2Flow is 50sccm to 500sccm, C4F6Flow is 0sccm to 200sccm, etch chamber chamber pressure
It is by force 5 millitorrs to 200 millitorrs, RF source power is 50 watts to 1000 watts, and bias power is 0V to 5000V.
Optionally, the first mask layer is formed in the dielectric layer surface, is formed with the portion of exposing in first mask layer
Divide the first groove of dielectric layer surface；Using first mask layer as exposure mask, first etching technics is carried out；With described first
Mask layer is exposure mask, carries out second etching technics.
Optionally, the material of first mask layer is SiN, SiC, SiCN, Ta, Ti, Tu, TaN, TiN, TuN or WN.
Optionally, the dielectric layer be laminated construction, the dielectric layer include etching stop layer and be located at etching stopping
The main dielectric layer of layer surface.
Optionally, the dielectric layer is single layer structure, and the dielectric layer includes main dielectric layer.
Optionally, the material of the main dielectric layer is silica, low k dielectric materials or ultra-low k dielectric material.
Optionally, the conductive layer includes: diffusion barrier layer positioned at open bottom and sidewall surfaces and is located at diffusion
Barrier layer surface and the conductor layer for filling full gate mouth.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the forming method of semiconductor structure provided by the invention, is etched and removed using the first etching technics
The dielectric layer of first thickness forms pre- opening in the dielectric layer；Then using depositing operation in the pre- open bottom and side wall
Surface deposited silicon layer；Then the second etching technics is used, etching removal is located at the silicon layer on the pre- open bottom surface, and etches
Removal is located at the dielectric layer of the second thickness of pre- opening lower section；Depositing operation described in repetitive cycling, the second etching technics, until shape
At the opening for running through the dielectric layer, the open bottom exposes substrate surface；Form the conductive layer for filling the full opening.
Since in the second etching process, the silicon layer positioned at pre- opening sidewalls surface plays protection to pre- opening sidewalls surface and makees
With so that the opening formed on the basis of pre- opening has good sidewall profile, to improve the conduction formed in opening
The quality of layer improves the interface performance between dielectric layer and conductive layer, avoids conductive layer to dielectric layer sunken inside, and then improves half
The breakdown voltage of conductor structure improves and time correlation dielectric breakdown problem.
Further, the etching of the processing chamber housing of silicon layer and the etching cavity of the first etching technics, the second etching technics is formed
Chamber is the same chamber, to reduce the required time of semiconductor structure disengaging chamber, and is avoided to semiconductor structure
Secondary pollution is caused, the electric property of the semiconductor structure formed is further improved.
Further, first thickness is more than or equal to the 75% of thickness of dielectric layers and is less than or equal to medium thickness in the present invention
Degree 90% so that formed pre- opening depth it is moderate, avoid it is pre- be open shallowly cause groove formed after and via bottoms
Substrate surface is not exposed, and avoids the too deep etching for causing intrabasement bottom metal layer to be exposed to the second etching technics that is open
Overlong time in environment.
Detailed description of the invention
Fig. 1 is the schematic diagram of the section structure for the semiconductor structure that the prior art is formed；
Fig. 2 to Figure 11 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process；
Figure 12 to Figure 16 be another embodiment of the present invention provides semiconductor structure formed process the schematic diagram of the section structure.
Specific embodiment
It can be seen from background technology that the electric property for the semiconductor structure that the prior art is formed is to be improved, for example, semiconductor
The breakdown voltage (VBD:Breakdown Voltage) of structure is low, and there are time associated medias to puncture (TDDB:Time
Dependent Dielectric Breakdown) problem.
With reference to Fig. 1, the formation of semiconductor structure is formed with the following steps are included: provide substrate 100 in the substrate 100
Bottom metal layer 101；Dielectric layer 102 is formed on 100 surface of substrate；The dielectric layer 102 is etched to be formed through being given an account of
The opening 103 of 102 thickness of matter layer；Form the conductive layer of the full opening 103 of filling, the conductive layer and bottom metal layer 101
Electrical connection.
It has been investigated that leading to the reason that the breakdown potential of semiconductor structure is forced down, time correlation dielectric breakdown problem is significant
Be: the performance for the conductive layer filled in opening 103 is poor；Conductive layer side wall and 102 side wall of dielectric layer contact defective tightness,
Interface performance between conductive layer and dielectric layer 102 is poor；Also, it is closer between adjacent conductive layer, between adjacent conductive layer
It is easy to happen electrical breakdown.
Further study show that etching technics is inevitably to opening 103 during etch media layer 102 forms opening 103
Side wall causes to etch, and etching technics is difficult to control the etch rate of 103 side walls of opening, 103 side of opening resulted in
Wall surface is no longer the surface of smooth transition, and defect area 104, the presence of the defect area 104 occur in 103 side-walls of opening
It will lead to that the conductive layer to be formed is second-rate, and the interface performance between conductive layer and dielectric layer 102 is poor, the metal in conductive layer
Ion easily spreads along the interface of the performance difference and electromigration occurs.When defect area 104 is bowl-shape defect (bowl
Profile defect) when, since bowl-shape defect is to 102 sunken inside of dielectric layer, so that the conductive layer in bowl-shape defect is also to Jie
102 sunken inside of matter layer in turn results in the shortening of the distance between adjacent conductive layer, therefore electrical breakdown easily occurs in semiconductor structure,
And time correlation dielectric breakdown problem is serious.
For this purpose, the present invention provides a kind of forming method of semiconductor structure, using the first etching technics etching removal first
The dielectric layer of thickness forms pre- opening in the dielectric layer；Then using depositing operation in the pre- open bottom and sidewall surfaces
Deposited silicon layer；Then the second etching technics is used, etching removal is located at the silicon layer on the pre- open bottom surface and is located at pre-
The dielectric layer of second thickness below being open；Depositing operation described in repetitive cycling, the second etching technics, until being formed through described
The opening of dielectric layer, the open bottom expose substrate surface；Form the conductive layer for filling the full opening.The present invention improves
The pattern of the opening formed in dielectric layer improves dielectric layer and conduction to improve the quality of the conductive layer formed in being open
Interface performance between layer avoids conductive layer to dielectric layer sunken inside, and then improves the breakdown voltage of semiconductor structure, improve with
Time correlation dielectric breakdown problem.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 11 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process.
With reference to Fig. 2, substrate 200 and the dielectric layer positioned at 200 surface of substrate are provided, are formed with bottom in the substrate 200
Layer metal layer 201.
The material of the substrate 200 is silicon, germanium, SiGe, silicon carbide or GaAs；The material of the substrate 200 may be used also
Think the silicon on monocrystalline silicon, polysilicon, amorphous silicon or insulator.
200 surface of substrate can also be formed with several boundary layers or epitaxial layer to improve the electrical property of semiconductor structure
Energy.Can also be formed with semiconductor devices in the substrate 200, the semiconductor devices be PMOS transistor, NMOS transistor,
CMOS transistor, capacitor, resistor or inductor.
In the present embodiment, the substrate 200 is silicon base.
The bottom metal layer 201 with conductive layer to be formed for being connected, it can also be used to the conductive layer being subsequently formed
It is electrically connected with external or other metal layers.The material of the bottom metal layer 201 is the conductive materials such as Cu, Al or W.
The dielectric layer is single layer structure or laminated construction.In the present embodiment, the dielectric layer is laminated construction, is given an account of
Matter layer includes etching barrier layer 202 and the main dielectric layer 203 positioned at 202 surface of etching barrier layer.In other embodiments, it is situated between
Matter layer may be the single layer structure of main dielectric layer.
The etching barrier layer 202 plays the role of etch stopper, the etching technics of the main dielectric layer 203 of subsequent etching subsequent
It is smaller to the etch rate of etching barrier layer 202, to play the role of etching stopping, prevent to substrate 200 or bottom metal layer
201 cause over etching.The material of the etching barrier layer 202 is different from the material of main dielectric layer 203.
The material of the etching barrier layer 202 is silicon nitride, silicon oxynitride or carbonitride of silicium.In the present embodiment, the quarter
The material for losing barrier layer 202 is carbonitride of silicium.
The material of the main dielectric layer 203 is silica, (low k dielectric materials refer to relative dielectric constant to low k dielectric materials
More than or equal to the 2.6, dielectric material less than 3.9) or ultra-low k dielectric material (ultra-low k dielectric material refers to that relative dielectric constant is less than
2.6 dielectric material).
When the material of the main dielectric layer 203 is low k dielectric materials or ultra-low k dielectric material, the material of main dielectric layer 203
For SiOH, SiCOH, FSG (silica of fluorine doped), BSG (silica of boron-doping), PSG (silica of p-doped), BPSG
(silica of boron-doping phosphorus), hydrogenation silsesquioxane (HSQ, (HSiO1.5)n) or methyl silsesquioxane (MSQ,
(CH3SiO1.5)n)。
In the present embodiment, the material of the main dielectric layer 203 is ultra-low k dielectric material, and the ultra-low k dielectric material is
SiCOH。
In the present embodiment, further comprises the steps of: and form passivation layer (not shown) on main 203 surface of dielectric layer, the passivation layer
Play the role of the main dielectric layer 203 of protection, the lattice constant phase of the lattice constant of main dielectric layer 203 and the mask layer being subsequently formed
Difference is larger, and the lattice constant of passivation layer is positioned there between, therefore passivation layer also functions to transitional function, avoids since lattice is normal
Numerical mutation and stress is applied to main dielectric layer 203, main dielectric layer 203 is caused to deform.The material of passivation layer is silica or carbon containing oxygen
SiClx.
Subsequent etching dielectric layer forms the opening for running through dielectric layer, and the opening is single Damascus opening or double damascenes
Leather opening.In the present embodiment, the opening being subsequently formed includes the through-hole and groove being intertwined, wherein the through-hole is located at
Between groove and substrate 200, and the width dimensions of the through-hole are less than the width dimensions of groove；It can be using after being initially formed through-hole
Form groove (via first trench last), be initially formed after groove formed through-hole (trench first via last) or
The method for being formed simultaneously through-hole and groove (via and trench all-in one etch) forms dual damascene openings.This
Embodiment is used as using the method for being formed simultaneously through-hole and groove and is shown using the opening being subsequently formed as dual damascene openings
Example.
With reference to Fig. 3, the first mask layer 205 is formed in the dielectric layer surface, is formed in first mask layer 205 sudden and violent
First groove 206 of exposed portion dielectric layer surface.
First groove 206 defines the positions and dimensions for the groove being subsequently formed.First mask layer 205 is single
Layer structure or laminated construction, first mask layer 205 can be the single layer of the single layer structure of medium mask layer, metal mask layer
The laminated construction of structure or medium mask layer and the metal mask layer positioned at medium exposure mask layer surface, wherein medium exposure mask
The material of layer is SiN, SiC, SiCN, and the material of metal mask layer is Ta, Ti, Tu, TaN, TiN, TuN or WN.
In the present embodiment, first mask layer 205 is single layer structure, and the material of the first mask layer 205 is TiN.
With reference to Fig. 4, is formed and be covered in 205 surface of the first mask layer and portion that the first groove 205 exposes (with reference to Fig. 3)
Divide the second mask layer of dielectric layer surface, is formed with the second groove 207 in second mask layer.
Second groove 207 defines the positions and dimensions for the through-hole being subsequently formed, and second groove 207 and
The figure that one groove 206 is projected on 200 surface of substrate has the part being overlapped.In the present embodiment, second groove 207 is located at
First groove, 206 top, the width dimensions of the second groove 207 are less than the width dimensions of the first groove 206, i.e. the second groove 207
The figure for being projected on 200 surface of substrate is located at the first groove 206 and is projected in the figure on 200 surface of substrate.
In the present embodiment, second mask layer includes organic distribution layer 208, positioned at the bottom on organic 208 surface of distribution layer
Portion's anti-reflection coating 209 and photoresist layer 210 positioned at 209 surface of bottom antireflective coating, wherein second groove
207 run through the photoresist layer 210 and expose 209 surface of bottom antireflective coating.
In other embodiments, second mask layer can be the single layer structure or bottom anti-reflective of photoresist layer
The laminated construction of coating and photoresist layer or laminated construction for photoresist layer and reflection coating provided.
With reference to Fig. 5, using second mask layer as exposure mask, the first etching technics is used along the second groove 207 (referring to Fig. 4)
The dielectric layer of etching removal first thickness, forms pre- opening 211 in the dielectric layer.In the present embodiment, the first etching technics
The main dielectric layer 203 of etching removal segment thickness, forms pre- opening 211 in the main dielectric layer 203.Part is removed in etching
Before the main dielectric layer 203 of thickness, further comprises the steps of: and be sequentially etched (the reference of bottom antireflective coating 209 along the second groove 207
Fig. 4) and organic distribution layer 208 (refer to Fig. 4), until main 203 top surface of dielectric layer is exposed.
The main dielectric layer 203 is etched using dry etch process.In a specific embodiment, the dry etching work
The etching gas of skill includes CH2F2、C4F6、CF4Or CHF3, in order to reduce dry etch process to quarter caused by main dielectric layer 203
Deteriorate wound, the etching gas of the dry etch process can also include O2。
In the present embodiment, joined using the technique that lock-out pulse etching technics etches the main dielectric layer 203 of removal segment thickness
Number are as follows: N2Flow is 50sccm to 200sccm, C4F6Flow is 50sccm to 200sccm, and Ar flow is 0sccm to 200sccm,
CF4Flow is 0sccm to 100sccm, CH2F2Flow is 0sccm to 100sccm, and etching cavity pressure is 10 millitorrs to 200 millis
Support, providing plasma rf power is 100 watts to 500 watts, and providing biasing radio-frequency power is 0 watt to 200 watts, and plasma is penetrated
The duty ratio of frequency power is 10% to 80%, and the duty ratio for biasing radio-frequency power is 10% to 80%.
The present embodiment is during dry etch process, photoresist layer 210 (referring to Fig. 4) and bottom antireflective coating
209 (referring to Fig. 4) are consumed, therefore after the dielectric layer 203 of etching removal segment thickness, it is only necessary to organic point of etching removal
Layer of cloth 208 (refers to Fig. 4).In other embodiments, if after the dielectric layer of etching removal segment thickness, on dielectric layer
Still there is the photoresist layer of segment thickness in side, then needs to etch removal photoresist layer, bottom antireflective coating and organic distribution layer.
The depth of the pre- opening 211 should not be excessively shallow, and the depth of pre- opening 211 is identical as first thickness, otherwise subsequent shape
At through-hole depth dimensions it is too small；If the depth of the pre- opening 211 is too deep, through-hole can compare during subsequent etching processes
Groove is initially formed, so that being exposed in etching environment for 201 longer period of bottom metal layer, is easy to bottom metal layer 201
Cause etching injury.
For this purpose, in the present embodiment, the depth of the pre- opening 211 is more than or equal to the 75% of thickness of dielectric layers and is less than etc.
In the 90% of thickness of dielectric layers, that is, first thickness is more than or equal to the 75% of thickness of dielectric layers and is less than or equal to thickness of dielectric layers
90%.Since compared with the thickness of main dielectric layer 203, the thickness of etching stop layer 202 be can be ignored, and etching technics
There is biggish etching selection ratio with to main dielectric layer 203 to etching stop layer 202, accordingly, it is believed that the first thickness
75% more than or equal to main 203 thickness of dielectric layer and 90% less than or equal to main 203 thickness of dielectric layer.The pre- opening 211
Section pattern is inverted trapezoidal, and the sidewall surfaces of the pre- opening 211 can also be perpendicular to 200 surface of substrate.
With reference to Fig. 6, using depositing operation, in 211 bottom and side wall surface deposited silicon layers 212 of the pre- opening.
In the present embodiment, the silicon layer 212 is not only located at 211 bottom and side wall surfaces of pre- opening, is also located at the first exposure mask
205 surface of layer, and the silicon layer 212 is also located at 203 top surface of main dielectric layer that the first mask layer 205 exposes.It is subsequent
In etching process, it is located at 211 bottom surfaces of 205 surface of the first mask layer, 203 top surface of main dielectric layer and pre- opening
Silicon layer 212 can be etched removal.
Effect positioned at the silicon layer 212 on 211 bottom and side wall surfaces of pre- opening is: in subsequent etching processes, etching work
Skill is greater than the quarter of the silicon layer 212 to 211 sidewall surfaces of pre- opening to the etch rate of the silicon layer 212 of 211 bottom surfaces of pre- opening
Rate is lost, so that pre- 211 sidewall surfaces that are open are by silicon layer 212 during etching the certain media layer below pre- opening 211
Covering avoids 211 sidewall surfaces of pre- opening from being exposed in etching environment, subsequent to form opening on the basis of pre- opening 211, makes
The opening sidewalls surface topography that must be formed is good, and the opening sidewalls avoided the formation of are by etching injury.
The method for forming the silicon layer 212 includes: to be placed on the substrate 200 and medium with pre- opening 211
In processing chamber housing, and processing chamber housing inner-wall material includes silicon；Plasma is provided, the plasma is in DC offset voltage
Lower bombardment processing chamber inner wall is acted on, so that the silicon atom of processing chamber housing inner wall is fallen off, the silicon atom to fall off is attached to pre- open
The bottom surface and sidewall surfaces of mouth 211, the silicon atom to fall off are also attached to 205 surface of the first mask layer and medium
Layer top surface, forms the silicon layer 212.
Specifically, in one embodiment, Ar gaseous plasmaization is formed Ar plasma, in DC offset voltage
Under the action of, Ar plasma bombardment processing chamber housing inner wall.In another embodiment, by N2Gaseous plasmaization forms N etc.
Gas ions, under the action of DC offset voltage, N plasma bombardment processing chamber housing inner wall.
It should be noted that in deposition process, target that plasma bombards under DC offset voltage effect
For processing chamber housing inner wall, it is therefore desirable to according to the positive negativity of plasma-charge, determine the positive negativity of DC offset voltage, thus
Bombard plasma to processing chamber housing inner wall, without bombarding dielectric layer.
In the present embodiment, the technological parameter of the silicon layer 212 is formed are as follows: N2Flow is 50sccm to 500sccm, Ar flow
For 50sccm to 500sccm, processing chamber housing pressure is 5 millitorrs to 200 millitorrs, and plasma rf power is 50 watts to 1000
Watt, biasing radio-frequency power is 0 watt to 200 watts, and DC offset voltage is -100V to -1000V.
Wherein, DC offset voltage is that the meaning of -100V to -1000V is: under DC offset voltage effect, N
Plasma, Ar plasma bombardment are located at the processing chamber housing inner wall right above dielectric layer, under the action of DC offset voltage
Plasma obtains the kinetic energy that can bombard the processing chamber housing inner wall right above dielectric layer.
In other embodiments, if the material of processing chamber housing inner wall does not include silicon atom, the method for forming silicon layer are as follows: mention
For silicon target, using plasma bombards silicon target under the action of direct current biasing power, and silicon atom is made to fall off from silicon target
It is attached to the bottom and side wall surface of opening, to form silicon layer.
In the present embodiment, the thickness of the silicon layer 212 of formation is unsuitable blocked up, otherwise 211 bottoms of the pre- opening of subsequent etching removal
Silicon layer 212 needed for etch period it is too long, be unfavorable for shorten semiconductor structure production cycle；The thickness of the silicon layer 212 of formation
Degree is also unsuitable excessively thin, and it is excessively weak to be otherwise located at the protective effect that the silicon layers 212 of 211 sidewall surfaces of pre- opening plays, and is located at pre- opening
The silicon layer 212 of 211 sidewall surfaces is easily removed in subsequent etching technics, and 211 side walls of pre- opening is caused to be exposed to etching
In environment, it is easy to cause the opening sidewalls pattern to be formed poor.
For this purpose, in the present embodiment, the silicon layer 212 with a thickness of 5 angstroms to 50 angstroms so that subsequent etching processes etch
Etch period needed for removal is located at the silicon layer 212 of 211 bottom surfaces of pre- opening is shorter, reduces etching technics to main dielectric layer
Adverse effect caused by 203, and the silicon layer 212 for being located at 211 sidewall surfaces of pre- opening have to 211 side walls of pre- opening it is enough
Protective effect.
In the present embodiment, the etching cavity of the first etching technics, the processing chamber housing and subsequent second for forming silicon layer 212
The etching cavity of etching technics is the same chamber, can not only improve production efficiency, additionally it is possible to avoid external environment to opening in advance
Mouth 211 causes secondary pollution.
With reference to Fig. 7, using the second etching technics, etching removal is located at the silicon layer 212 of 211 bottom surfaces of the pre- opening
(referring to Fig. 6), exposes 211 bottom surfaces of pre- opening；Continue using the second etching technics, etching removal is located at described expose
211 bottom part down of pre- opening second thickness dielectric layer.
In the present embodiment, second etching technics with the first mask layer 205 (referring to Fig. 3) for exposure mask, along the first groove
206 (referring to Fig. 3) etchings are located at the silicon layer 212 of 211 bottom surfaces of pre- opening, the certain media layer positioned at pre- 211 lower section of opening；
Second etching technics also etches the silicon layer 212 that removal is located at 205 surface of the first mask layer, table at the top of etching removal dielectric layer
The dielectric layer that face silicon layer 212, also etching removal are not covered by the first mask layer 205.
Second etching technics, which is greater than the etch rate for the silicon layer 212 for being located at 211 bottoms of pre- opening, to be opened in advance to being located at
The etch rate of the silicon layer 212 of 211 sidewall surfaces of mouth, and the second etching technics is to the silicon layer 212 for being located at 205 surface of mask layer
Etch rate be greater than the etch rate to the silicon layer 212 for being located at 211 sidewall surfaces of pre- opening.As the second etching technics carries out
The certain media layer of the passage of time, the silicon layer 212 of 211 bottom surfaces of the pre- opening and pre- opening lower section is etched
It removes, therefore, basad 200 surface direction of bottom position of pre- opening 211 moves down.And since the second etching technics is also covered to first
The dielectric layer that film layer 205 exposes performs etching, therefore, with 211 top width of pre- opening before the second etching technics of progress
Size is compared, and the top width of the pre- opening 211 after the second etching technics becomes large-sized.It is pre- after second etching technics
The top width size of opening 211 is consistent with the width dimensions of the first groove 206.
In one embodiment, before the silicon layer 212 of 211 sidewall surfaces of the pre- opening is by complete etching removal, stop
Only second etching technics.In another embodiment, it is etched completely in the silicon layer 212 of 211 sidewall surfaces of the pre- opening
When removal, stop second etching technics.In the second etching process, pre- 211 sidewall surfaces that are open are by 212 institute of silicon layer
Protection, 211 sidewall surfaces of pre- opening protected by silicon layer 212 prevent from occurring in 211 sidewall surfaces of opening in advance from etching injury
Defect area, so that the opening sidewalls surface formed on the basis of pre- opening 211 be avoided defect area occur.
The second thickness and the silicon layer of formation 212 and the second etching technics are to positioned at 211 sidewall surfaces of pre- opening
The etch rate of silicon layer 212 is related.The present embodiment is to be located at the silicon layer 212 of 211 sidewall surfaces of pre- opening by complete etching removal
When stop the second etching technics as example.In other embodiments, in order to further protect 211 sidewall surfaces of pre- opening,
It can also stop the second etching technics before the silicon layer 212 for being located at 211 sidewall surfaces of pre- opening is by complete etching removal.
In the present embodiment, the technological parameter of second etching technics are as follows: CH4Flow is 50sccm to 500sccm, CHF3
Flow is 50sccm to 500sccm, N2Flow is 50sccm to 500sccm, C4F6Flow is 0sccm to 200sccm, etch chamber
Chamber pressure is 5 millitorrs to 200 millitorrs, and RF source power is 50 watts to 1000 watts, and bias power is 0V to 5000V.
Above-mentioned second etching technics is small to the etch rate for the silicon layer 212 for being located at 211 sidewall surfaces of pre- opening, pre- to being located at
The etch rate of the silicon layer 212 for 211 bottom surfaces that are open is big, and the etch rate to the dielectric layer for being located at 211 bottoms of pre- opening
Greatly, thus it is very fast in the rate for moving down pre- opening basad 200 surface direction of 211 bottom positions, to avoid premature incite somebody to action
The silicon layer 212 of 211 sidewall surfaces of pre- opening etches removal, so that the silicon layer 212 of 211 sidewall surfaces of opening is to pre- opening 211 in advance
Sidewall surfaces play enough protective effects.
With reference to Fig. 8, continue using depositing operation, in 211 bottom and side wall surface deposited silicon layers 212 of the pre- opening.
In the present embodiment, the silicon layer 212 is also located at 205 surface of the first mask layer, the first mask layer 205 exposes Jie
Matter layer top surface.Effect and forming method in relation to silicon layer 212 can refer to the description that silicon layer 212 is formed in earlier figures 6,
This is repeated no more.
With reference to Fig. 9, continue using the second etching technics, etching removal is located at the silicon layer of 211 bottom surfaces of the pre- opening
212 (referring to Fig. 8), the dielectric layer of the second thickness of pre- 211 lower section of opening of etching removal.
It is exposure mask with first mask layer 205 in the present embodiment, is located at 211 bottoms of pre- opening along the first groove 206 etching
The silicon layer 212 on portion surface and the certain media layer below pre- opening 211；Second etching technics also etch not by
The dielectric layer of first mask layer 205 covering.
The present embodiment is to stop the second etching when being located at the silicon layer 212 of 211 sidewall surfaces of pre- opening by complete etching removal
It, in other embodiments, can also be in the silicon layer 212 for being located at 211 sidewall surfaces of pre- opening by complete etching removal for technique
Stop the second etching technics before.
Thickness, the second etching technics of the silicon layer 212 deposited before the second thickness and the second etching technics are open to pre-
The etch rate of the silicon layer 212 of 211 sidewall surfaces is related, therefore it is fixed value that the second thickness in the processing step, which is not,
Second thickness in the processing step and the second thickness in the second etching technics shown in Fig. 7 can be identical or not
Together.
With reference to Figure 10, repetitive cycling progress depositing operation above-mentioned, the second etching technics run through the medium until being formed
The opening of layer, the open bottom expose 200 surface of substrate.
In the present embodiment, the opening includes the through-hole 222 and groove 221 being intertwined, wherein the through-hole 222
Between groove 221 and substrate 200, and the width dimensions of the through-hole 222 are less than the width dimensions of groove 221.
The number of the number, the second etching technics that repeat depositing operation above-mentioned can be deep according to opening to be formed
The thickness of the depth for the pre- opening 211 that degree, first time etching technics are formed, each time dielectric layer of the second etching technics etching removal
Degree is to determine.Due to being formed with silicon layer 212, the silicon on pre- open bottom surface and sidewall surfaces before the second etching technics
Layer 212 plays the role of protection 211 side walls of pre- opening in the second etching process, prevents the second etching technics to pre- opening
211 sidewall surfaces cause etching injury, therefore as the second etching technics carries out the passage of time, on the basis of pre- opening 211
The opening sidewalls of formation have good pattern, avoid forming defect area on opening sidewalls surface.In the present embodiment, through-hole
222 side walls and 221 side wall of groove all have good pattern.
It is heavy in repetitive cycling since main dielectric layer 203 is different from the material of etching stop layer 202 in the present embodiment
Product technique and the second etching technics etch main dielectric layer 203 to after exposing etching stop layer 202, can be carved using third
Etching technique directly performs etching etching stop layer 202, the third etching technics to the etch rate of main dielectric layer 203 very
It is small, therefore adverse effect will not be caused to the opening sidewalls pattern of formation.
With reference to Figure 11, the conductive layer 224 for filling the full opening is formed.
In the present embodiment, the completely described through-hole 222 (referring to Figure 10) of the filling of conductive layer 224 and groove 221 are (with reference to figure
10)。
In a specific embodiment, the processing step for forming the conductive layer 224 includes: to form the full opening of filling
Conductive film, the conductive film also covers the first mask layer 205 (with reference to Figure 10) surface；Removal is higher than dielectric layer top surface
Conductive film forms the conductive layer 221 of filling full gate mouth, and 221 top surface of the conductive layer is flushed with dielectric layer top surface.
In the present embodiment, using surface with chemical polishing technology, removal is covered higher than the conductive film of dielectric layer top surface and first
Film layer 205.
The conductive layer 224 is single layer structure or laminated construction, the material of the conductive layer 224 is TiN, Ti, Ta, TaN,
WN, Cu, Al or W.
For the present embodiment by taking conductive layer 224 is single layer structure as an example, the material of conductive layer 224 is W.
In other embodiments, conductive layer include: diffusion barrier layer positioned at the open bottom and sidewall surfaces and
Positioned at the conductor layer of diffusion barrier layer surface and the full opening of filling.Wherein, the material of the electrically conductive barrier be TiN,
Ti, Ta, TaN or WN；The material of the conductor layer is Cu, Al or W.
Since opening sidewalls have good pattern, avoid generating defect area, therefore this implementation on opening sidewalls surface
The conductive layer 224 filled in opening in example has good quality, tight between 224 side wall of conductive layer and dielectric layer side wall
Contiguity touching prevents the metal ion in conductive layer 224 logical so that the interface performance that conductive layer 224 is in contact with dielectric layer is good
Cross the interface that conductive layer 224 contacts with dielectric layer the distance between electromigration occurs, and avoids adjacent conductive layer 224 it is excessively close.
Therefore, the breakdown voltage for the semiconductor structure that the present embodiment is formed is larger, improves the breakdown characteristics of semiconductor structure, improves
Semiconductor structure with time correlation dielectric breakdown problem, optimize the electric property for the semiconductor structure to be formed.
Another embodiment of the present invention also provides a kind of forming method of semiconductor structure, and Figure 12 to Figure 16 is that the present invention is another
The semiconductor structure that embodiment provides forms the schematic diagram of the section structure of process.
With reference to Figure 12, substrate 300 is provided, 300 surface of substrate is formed with dielectric layer；It is formed in the dielectric layer surface
First mask layer 305 is formed with the first groove 306 for exposing certain media layer surface in first mask layer 305.
In the present embodiment, the dielectric layer includes etching stop layer 302 and main Jie positioned at 302 surface of etching stop layer
Matter layer 303.
It is exposure mask with first mask layer 305 with reference to Figure 13, is etched using the first etching technics along the first groove 305
The dielectric layer of portion's first thickness forms pre- opening 311 in the dielectric layer.
The first thickness is more than or equal to the 75% of thickness of dielectric layers and is less than or equal to the 90% of thickness of dielectric layers.This reality
It applies in example, first thickness is more than or equal to the 75% of main 203 thickness of dielectric layer and is less than or equal to the 90% of main 203 thickness of dielectric layer.
With reference to Figure 14, using depositing operation, in 311 bottom and side wall surface deposited silicon layers 312 of the pre- opening.
In the present embodiment, the silicon layer 312 is also located at 304 surface of the first mask layer.Effect and formation in relation to silicon layer 312
Method can refer to the explanation of previous embodiment, and details are not described herein.
With reference to Figure 15, using the second etching technics, etching removal is located at the (reference of silicon layer 312 of 311 bottom surfaces of pre- opening
Figure 14), and the dielectric layer for being located at the second thickness of pre- 311 lower section of opening is etched.
The time passage carried out with the second etching technics, it is pre- to be open under 311 basad 300 surface direction of bottom position
It moves, compared with before the second etching technics, the depth of the pre- opening 311 after the second etching technics is deepened.
In the present embodiment, also etching removes the silicon layer 312 for being located at 305 surface of the first mask layer.Second etching technics is to pre-
The etch rate of the silicon layer 312 for 311 bottom surfaces that are open is greater than the etch rate of the silicon layer 312 to 311 sidewall surfaces of pre- opening,
The removal so that silicon layer 312 for 311 bottom surfaces that ought be open in advance is etched continues the dielectric layer that etching is located at pre- 311 lower section of opening
During, pre- 311 sidewall surfaces that are open are covered by silicon layer 312, so that 311 sidewall surfaces of pre- opening be prevented to be exposed to etched rings
In border, avoid causing 311 sidewall surfaces of pre- opening etching injury, therefore the subsequent opening formed on the basis of pre- opening 311
Side wall has good pattern.
In one embodiment, stopped positioned at the silicon layer 312 of 311 sidewall surfaces of pre- opening by before complete etching removal
Second etching technics.In another embodiment, positioned at the silicon layer 312 of 311 sidewall surfaces of pre- opening by complete etching removal
When, stop second etching technics.
Technological parameter in relation to the second etching technics can refer to the explanation of previous embodiment, and details are not described herein.
With reference to Figure 16, repetitive cycling depositing operation above-mentioned, the second etching technics, until being formed through the dielectric layer
Opening 310,310 bottom-exposeds of the opening go out 200 surface of substrate.
Due to being formed with silicon layer on pre- opening 311 (referring to Figure 15) bottom and side wall surface before the second etching technics
312, the silicon layer 312 plays the role of protection 311 side walls of pre- opening in the second etching process, prevents the second etching work
Skill causes etching injury to 311 sidewall surfaces of pre- opening, therefore as the second etching technics carries out the passage of time, is being open in advance
310 side wall of opening formed on the basis of 311 has good pattern, avoids forming defect area in 310 sidewall surfaces that are open.
Subsequent processing step includes: the conductive layer to form the full opening 310 of filling, the conductive layer top and medium
Layer top flushes；Remove first mask layer 305.
There is good pattern by 310 side wall of opening formed in this present embodiment, avoid producing in 310 sidewall surfaces that are open
Raw defect area, therefore the conductive layer filled in opening 310 has good quality, the conductive layer side wall and dielectric layer side
It is in close contact between wall, so that the interface performance that conductive layer is in contact with dielectric layer is good, prevents the metal ion in conductive layer
Electromigration occurs for the interface contacted with dielectric layer by conductive layer, and it is excessively close the distance between to avoid adjacent conductive layer.Therefore, originally
The breakdown voltage for the semiconductor structure that embodiment is formed is larger, to improve the breakdown characteristics of semiconductor structure, and improves half
Conductor structure with time correlation dielectric breakdown problem so that the electric property of semiconductor structure formed is improved.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate surface is formed with dielectric layer；
The dielectric layer that removal first thickness is etched using the first etching technics forms pre- opening in the dielectric layer；
Using depositing operation, in the pre- open bottom and sidewall surfaces deposited silicon layer；
Using the second etching technics, etching removal is located at the silicon layer on the pre- open bottom surface, exposes the pre- open bottom
Portion；
Continue using the second etching technics, etching removal is located at Jie of the second thickness below the pre- open bottom exposed
Matter layer；
Depositing operation described in repetitive cycling, the second etching technics, until forming the opening for running through the dielectric layer, the open bottom
Portion exposes substrate surface；
Form the conductive layer for filling the full opening.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that second etching technics is to pre-
The etch rate of the silicon layer on open bottom surface is greater than the etch rate to the silicon layer on pre- opening sidewalls surface.
3. the forming method of semiconductor structure according to claim 1, which is characterized in that form the method packet of the silicon layer
It includes: being placed in processing chamber housing by the substrate and with the medium being open in advance, and processing chamber housing inner-wall material includes silicon；It mentions
For plasma, plasma bombardment processing chamber inner wall under the action of DC offset voltage makes processing chamber housing inner wall
Silicon atom fall off, the silicon atom to fall off is attached to the bottom surface and sidewall surfaces of pre- opening, forms the silicon layer.
4. the forming method of semiconductor structure according to claim 3, which is characterized in that the processing chamber housing and described the
The etching cavity of one etching technics, the second etching technics etching cavity be the same chamber.
5. the forming method of semiconductor structure according to claim 3, which is characterized in that form the technique ginseng of the silicon layer
Number are as follows: N2Flow is 50sccm to 500sccm, and Ar flow is 50sccm to 500sccm, and processing chamber housing pressure is 5 millitorrs to 200
Millitorr, plasma rf power be 50 watts to 1000 watts, biasing radio-frequency power be 0 watt to 200 watts, DC offset voltage be-
100V to -1000V.
6. the forming method of semiconductor structure according to claim 1, which is characterized in that the silicon layer with a thickness of 5 angstroms
To 50 angstroms.
7. the forming method of semiconductor structure according to claim 1, which is characterized in that the opening includes being intertwined
Through-hole and groove, wherein the through-hole is between groove and substrate, and the width dimensions of the through-hole are less than groove
Width dimensions.
8. the forming method of semiconductor structure according to claim 7, which is characterized in that the technique for forming the pre- opening
Step includes: to form the first mask layer in the dielectric layer surface, is formed in first mask layer and exposes certain media
First groove of layer surface；Then the certain media layer table that formation is covered in the first exposure mask layer surface and the first groove exposes
Second mask layer in face is formed with the second groove in second mask layer, and the width dimensions of second groove are less than
The width dimensions of one groove；Using second mask layer as exposure mask, the dielectric layer of etching removal first thickness forms described pre- open
Mouthful.
9. the forming method of semiconductor structure according to claim 1 or 8, which is characterized in that the first thickness is greater than
75% equal to thickness of dielectric layers and 90% less than or equal to thickness of dielectric layers.
10. the forming method of semiconductor structure according to claim 8, which is characterized in that be with first mask layer
Exposure mask, carries out second etching technics, and second etching technics also etches the dielectric layer that the first mask layer exposes.
11. the forming method of semiconductor structure according to claim 8, which is characterized in that the silicon layer is also located at first
The dielectric layer top surface that exposure mask layer surface, the first mask layer expose；Second etching technics also etches removal and is located at the
The silicon layer for the dielectric layer top surface that one exposure mask layer surface and the first mask layer expose.
12. the forming method of semiconductor structure according to claim 1, which is characterized in that in the pre- opening sidewalls table
The silicon layer in face stops second etching technics by before complete etching removal.
13. the forming method of semiconductor structure according to claim 1, which is characterized in that in the pre- opening sidewalls table
When the silicon layer in face is by complete etching removal, stop second etching technics.
14. the forming method of semiconductor structure according to claim 1, which is characterized in that second etching technics
Technological parameter are as follows: CH4Flow is 50sccm to 500sccm, CHF3Flow is 50sccm to 500sccm, N2Flow be 50sccm extremely
500sccm, C4F6Flow is 0sccm to 200sccm, and etching cavity pressure is 5 millitorrs to 200 millitorrs, and RF source power is 50 watts
To 1000 watts, bias power is 0V to 5000V.
15. the forming method of semiconductor structure according to claim 1, which is characterized in that in the dielectric layer surface shape
At the first mask layer, the first groove for exposing certain media layer surface is formed in first mask layer；With described first
Mask layer is exposure mask, carries out first etching technics；Using first mask layer as exposure mask, the second etching work is carried out
Skill.
16. the forming method of the semiconductor structure according to claim 8 or 15, which is characterized in that first mask layer
Material be SiN, SiC, SiCN, Ta, Ti, Tu, TaN, TiN, TuN or WN.
17. the forming method of semiconductor structure according to claim 1, which is characterized in that the dielectric layer is lamination knot
Structure, the dielectric layer include etching stop layer and the main dielectric layer positioned at etching stopping layer surface.
18. the forming method of semiconductor structure according to claim 1, which is characterized in that the dielectric layer is single layer knot
Structure, the dielectric layer include main dielectric layer.
19. the forming method of semiconductor structure described in 7 or 18 according to claim 1, which is characterized in that the main dielectric layer
Material is silica, low k dielectric materials or ultra-low k dielectric material.
20. the forming method of semiconductor structure according to claim 1, which is characterized in that the conductive layer includes: to be located at
The diffusion barrier layer of open bottom and sidewall surfaces and positioned at diffusion barrier layer surface and fill the conductor layer of full gate mouth.
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| CN1647263A (en) * | 2002-04-02 | 2005-07-27 | 陶氏环球技术公司 | Tri-layer masking architecture for patterning dual damascene interconnects |
| JP2013206991A (en) * | 2012-03-27 | 2013-10-07 | Kyushu Institute Of Technology | Semiconductor device manufacturing method |
| CN103390581A (en) * | 2013-07-26 | 2013-11-13 | 中微半导体设备(上海)有限公司 | Through-silicon-via etching method |
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| CN1647263A (en) * | 2002-04-02 | 2005-07-27 | 陶氏环球技术公司 | Tri-layer masking architecture for patterning dual damascene interconnects |
| JP2013206991A (en) * | 2012-03-27 | 2013-10-07 | Kyushu Institute Of Technology | Semiconductor device manufacturing method |
| CN103390581A (en) * | 2013-07-26 | 2013-11-13 | 中微半导体设备(上海)有限公司 | Through-silicon-via etching method |
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