CN113113349B - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN113113349B CN113113349B CN202010026387.3A CN202010026387A CN113113349B CN 113113349 B CN113113349 B CN 113113349B CN 202010026387 A CN202010026387 A CN 202010026387A CN 113113349 B CN113113349 B CN 113113349B
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- 238000000034 method Methods 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 239000010410 layer Substances 0.000 claims abstract description 562
- 239000000463 material Substances 0.000 claims abstract description 223
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000005530 etching Methods 0.000 claims abstract description 52
- 239000011241 protective layer Substances 0.000 claims abstract description 50
- 238000002955 isolation Methods 0.000 claims description 50
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 239000011368 organic material Substances 0.000 claims description 12
- 238000004380 ashing Methods 0.000 claims description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000006117 anti-reflective coating Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000012159 carrier gas Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
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- 238000005457 optimization Methods 0.000 abstract 1
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- 238000000231 atomic layer deposition Methods 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for forming a semiconductor structure includes: providing a substrate; forming a pattern material layer on a substrate; carrying out a plurality of groove forming steps on the pattern material layer, forming grooves at a plurality of positions of the pattern material layer in sequence, wherein the remaining pattern material layer is used as the pattern layer, and the groove forming step comprises the following steps: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer is positioned on the top surface of the graphic material layer and is used as a protective layer; removing the second mask layer; after forming the pattern layer, the protective layer is removed. According to the embodiment of the invention, after the pattern layer is formed, the protective layer is removed, so that the material of the junction area between the top surface of the pattern layer and all the side walls of the grooves is damaged only once, and therefore, the chamfer angle at the top of the side walls of the grooves is smaller, and the optimization of the electrical performance of the semiconductor structure is facilitated.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
As semiconductor fabrication technology has become more sophisticated, significant changes have also been made to integrated circuits, and the number of components integrated on the same chip has increased from the first tens, hundreds, to millions today. In order to meet the requirement of circuit density, the fabrication process of semiconductor integrated circuit chips forms various types of complex devices on a substrate by using a batch process technology and connects them to each other to have a complete electronic function, and at present, an ultra-low k interlayer dielectric layer is mostly used between wires as a dielectric material for isolating each metal interconnect, and an interconnection structure is used for providing wiring between devices on the IC chip and the entire package. In this technique, devices such as Field Effect Transistors (FETs) are first formed on a semiconductor substrate surface, and then interconnect structures are formed in a Back End of Line (BEOL) process of integrated circuit fabrication.
As predicted by moore's law, the ever shrinking dimensions of semiconductor substrates and the use of interconnect structures to connect transistors is a necessary option in order to increase the performance of devices where more transistors are formed on the semiconductor substrate. However, compared with the miniaturization and integration of components, the number of conductor wires in a circuit is continuously increased, the formation quality of an interconnection structure greatly affects the reliability of circuit connection, and the normal operation of a semiconductor device can be affected in severe cases.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure and improving the electrical performance of a device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a pattern material layer on the substrate; and carrying out a plurality of groove forming steps on the graph material layer, forming grooves at a plurality of positions of the graph material layer in sequence, wherein the rest graph material layer is used as the graph layer, and the groove forming step comprises the following steps: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer is positioned on the top surface of the graphic material layer and is used as a protective layer; removing the second mask layer; and removing the protective layer after the pattern layer is formed.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the method for forming a semiconductor structure provided by the embodiment of the invention, in the step of forming the groove, a mask layer is formed on the pattern material layer, the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, the second mask layer is provided with an opening, the pattern material layer is etched by taking the second mask layer as a mask, a groove is formed in the pattern material layer, the first mask layer positioned on the top surface of the pattern material layer is used as a protective layer, so that the top surface of the pattern material layer covered by the protective layer is not exposed in the process of forming the groove, and the material of the junction area of the corresponding top surface of the pattern material layer and the side wall of the groove is not easily damaged; after the pattern layer is formed, the protective layer is removed, so that materials of the junction areas of the top surface of the pattern layer and all groove side walls are damaged only once, the chamfer at the top of the groove side walls is smaller, gaps are not easy to exist at the top of a top mask layer formed in the groove later, the pattern layer is removed, the top mask layer is used as a mask etching substrate, a residual substrate and an isolation layer positioned on the residual substrate are formed, gaps are not easy to exist at the top of the isolation layer, a conducting layer is formed on the residual substrate between the isolation layers, and conducting materials forming the conducting layer are not easy to deposit at the top of the isolation layer, so that the probability of leakage current of the conducting layer is reduced, and the electric performance of a semiconductor structure is optimized.
Drawings
Fig. 1 to 10 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 11 to 21 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Fig. 1 to 10 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
As shown in fig. 1 and 2, fig. 2 is a cross-sectional view of fig. 1 in the AA direction, providing a base comprising a substrate 1 and a layer of graphic material 2 on said substrate 1.
As shown in fig. 3, a first mask layer 3 is formed to cover the pattern material layer 2 and the substrate 1, the first mask layer 3 including a first organic material layer 31, a first anti-reflection coating layer 32 on the first organic material layer 31, and a first photoresist layer 33 on the first anti-reflection coating layer 32, the first photoresist layer having an opening 4 therein.
As shown in fig. 4, the first mask layer 3 is used as a mask to etch the pattern material layer 2, and a first groove 5 is formed in the pattern material layer 2; after the first groove 5 is formed, the first mask layer 3 is removed.
As shown in fig. 5, after the first mask layer 3 is removed, a second mask layer 6 is formed to cover the pattern material layer 2 and the substrate 1, and the second mask layer 6 includes a second organic material layer 61, a second anti-reflection coating layer 62 disposed on the second organic material layer 61, and a second photoresist layer 63 disposed on the second anti-reflection coating layer 62, where the second photoresist layer 63 has an opening 7 therein.
As shown in fig. 6 and 7, fig. 7 is a view in the direction B of fig. 6, the second mask layer 6 is used as a mask to etch the pattern material layer 2, and a second groove 8 is formed in the pattern material layer 2; after the second recess 8 is formed, the second mask layer 6 is removed.
As shown in fig. 8 and 9, a mask material layer 11 is conformally covered on the pattern material layer 2 and the substrate 1 between the pattern material layers 2; removing the mask material layer 11 higher than the pattern material layer 2, wherein the rest mask material layer 11 is used as a mask layer 9; after the mask layer 9 is formed, the pattern material layer 2 is removed.
As shown in fig. 10, the substrate 1 is etched with the mask layer 9 as a mask, a remaining substrate 12 and a spacer layer 13 on the remaining substrate 12 are formed, a conductive material layer (not shown in the figure) is formed on the remaining substrate 12 where the spacer layer 13 is exposed, the conductive material layer higher than the spacer layer 13 is removed, and the remaining conductive material layer serves as the conductive layer 10.
As the integration level of integrated circuits is continuously improved, the size of the semiconductor structure is also smaller and smaller, and the distance between the first groove 105 and the second groove 108 in the pattern material layer 102 is correspondingly smaller and smaller, because the resolution capability of the current lithography machine is insufficient, a mask layer for forming the first groove 105 and the second groove 108 cannot be generated through one exposure, and in the method for forming the semiconductor structure, the first groove 105 and the second groove 108 need to be formed through the cooperation of the first mask layer 3 and the second mask layer 6. After the first groove 5 is formed, in the step of removing the first mask layer 3, the region where the top of the sidewall of the first groove 5 meets the pattern material layer 2 is damaged; after the second recess 8 is formed, in the step of removing the second mask layer 6, the region where the top of the sidewall of the first recess 5 meets the pattern material layer 2 is damaged again, and the region where the top of the sidewall of the second recess 8 meets the pattern material layer 2 is damaged only once, so that the chamfer angle of the top of the first recess 5 is larger than that of the top of the second recess 8. In the process of forming the mask material layer 11, the top of the first groove 5 is not easy to be filled, a gap (sea) a (as shown in fig. 8) is easy to exist, and accordingly, in the process of forming the separation layer 13 by taking the mask layer 9 as a mask, the gap is transferred to the separation layer 13, in the process of forming the conductive layer 10, a conductive material layer is easy to exist in the gap of the separation layer 13, and in the process of working the semiconductor structure, the conductive layer 10 is easy to generate electric leakage, so that the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a pattern material layer on the substrate; and carrying out a plurality of groove forming steps on the graph material layer, forming grooves at a plurality of positions of the graph material layer in sequence, wherein the rest graph material layer is used as the graph layer, and the groove forming step comprises the following steps: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer is positioned on the top surface of the graphic material layer and is used as a protective layer; removing the second mask layer; and removing the protective layer after the pattern layer is formed.
In the method for forming a semiconductor structure provided by the embodiment of the invention, in the step of forming the groove, a mask layer is formed on the pattern material layer, the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, the second mask layer is provided with an opening, the pattern material layer is etched by taking the second mask layer as a mask, a groove is formed in the pattern material layer, the first mask layer positioned on the top surface of the pattern material layer is used as a protective layer, so that the top surface of the pattern material layer covered by the protective layer is not exposed in the process of forming the groove, and the material of the junction area of the corresponding top surface of the pattern material layer and the side wall of the groove is not easily damaged; after the pattern layer is formed, the protective layer is removed, so that materials of the junction areas of the top surface of the pattern layer and all groove side walls are damaged only once, the chamfer at the top of the groove side walls is smaller, gaps are not easy to exist at the top of a top mask layer formed in the groove later, the pattern layer is removed, the top mask layer is used as a mask etching substrate, a residual substrate and an isolation layer positioned on the residual substrate are formed, gaps are not easy to exist at the top of the isolation layer, a conducting layer is formed on the residual substrate between the isolation layers, and conducting materials forming the conducting layer are not easy to deposit at the top of the isolation layer, so that the probability of leakage current of the conducting layer is reduced, and the electric performance of a semiconductor structure is optimized.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 11 to 21 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 11, a substrate is provided.
The substrate provides a process basis for the subsequent formation of the conductive layer.
In this embodiment, the material of the substrate includes a dielectric layer 100, a first buffer material layer 101 on the dielectric layer 100, a hard mask layer 102 on the first buffer material layer 101, and a second buffer material layer 103 on the hard mask layer 102.
The dielectric layer 100 is etched later to form a remaining substrate and an isolation layer on the remaining substrate, a conductive layer is formed on the remaining substrate between the isolation layers, and the dielectric layer 100 is used to electrically isolate the conductive layer.
In this embodiment, the material of the dielectric layer 100 is a low-k dielectric material, which is beneficial to reduce parasitic capacitance between conductive layers, and thus is beneficial to reduce the RC delay of the back-end.
Specifically, the material of the dielectric layer 100 includes SiCOH.
The first buffer material layer 101 is configured to reduce stress between the hard mask layer 102 and the dielectric layer 100, so as to avoid excessive stress between the hard mask layer 102 and the dielectric layer 100, so that the hard mask layer 102 is not easy to crack or fall off.
In this embodiment, the material of the first buffer material layer 101 includes SiOC. In other embodiments, the material of the first buffer material layer may further include silicon oxide.
The hard mask layer 102 is used to prepare for a subsequent etch of the dielectric layer 100. The hard mask layer 102 has a higher etching resistance, and the materials of the dielectric layer 100 and the hard mask layer 102 have a larger etching selectivity in the subsequent etching process of the dielectric layer 100.
Specifically, the material of the hard mask layer 102 includes one or more of TiN, tiO 2、HfN、ZrO2, and Al 2O3. In this embodiment, the material of the hard mask layer 102 includes TiN.
The pattern material layer 104 is subsequently formed on the hard mask layer 102, and the second buffer material layer 103 is used for reducing stress between the hard mask layer 102 and the pattern material layer 104, so that the excessive stress caused by direct contact between the pattern material layer 104 and the hard mask layer 102 is avoided, and the pattern material layer 104 is not easy to crack or fall off.
In this embodiment, the material of the second buffer material layer 103 includes TEOS (tetraethyl orthosilicate, also called ethyl silicate). In other embodiments, the material of the second buffer material layer may further include silicon oxide.
It should be noted that the substrate further includes a gate structure, and source and drain doped regions located at two sides of the gate structure, and a contact plug (not shown) contacting with the source and drain doped regions is further formed in the substrate.
Referring to fig. 12 in combination with fig. 11, fig. 12 is a view of fig. 11 in the direction C, on which a layer of pattern material 104 is formed.
The layer of graphics material 104 provides for the subsequent formation of a graphics layer.
In this embodiment, the materials of the graphic material layer 104 include: silicon. In other embodiments, the material of the graphic material layer may further include: silicon oxide, silicon nitride or silicon oxynitride.
In this embodiment, the forming step of the graphic material layer 104 includes: forming a pattern material film (not shown in the drawings) on the substrate; forming a mask layer (not shown) on the pattern material film; and etching the pattern material film by taking the mask layer as a mask, wherein the remaining pattern material film is taken as a pattern material layer 104.
In other embodiments, the layer of graphics material may also be formed using self-aligned double patterning (SELF ALIGNED Double Patterning, SADP) or self-aligned quad patterning (SELF ALIGNED quadruple patterning, SAQP).
Referring to fig. 13 to 18, the pattern material layer 104 is subjected to a plurality of recess forming steps, in which recesses 105 are sequentially formed at a plurality of positions of the pattern material layer 104, and the remaining pattern material layer 104 serves as a pattern layer 112, the recess forming steps including: forming a mask layer 106 on the pattern material layer 104, wherein the mask layer 106 comprises a first mask layer 108 and a second mask layer 109 positioned on the first mask layer 108, and the second mask layer 109 is provided with an opening 107; etching the pattern material layer 104 by taking the second mask layer 109 as a mask, forming a groove 105 in the pattern material layer 104, and taking the first mask layer 108 remaining on the top surface of the pattern material layer 104 as a protection layer 111; the second mask layer 109 is removed.
In the step of forming the grooves, a mask layer 106 is formed on the pattern material layer 104, the mask layer 106 includes a first mask layer 108 and a second mask layer 109 located on the first mask layer 108, the second mask layer 109 has an opening 107, the pattern material layer 104 is etched by taking the second mask layer 109 as a mask, the grooves 105 are formed in the pattern material layer 104, the first mask layer 108 located on the top surface of the pattern material layer 104 is used as a protective layer 111, so that the top surface of the pattern material layer 104 covered by the protective layer 111 is not exposed in the process of forming the grooves 105, and the material of the interface area between the top surface of the pattern material layer 104 and the side walls of the grooves 105 is not easily damaged; after the pattern layer 112 is formed, the protective layer 111 is removed, so that the material of the junction area between the top surface of the pattern layer 112 and all the side walls of the groove 105 is damaged only once, and therefore, the chamfer angle at the top of the side walls of the groove 105 is smaller, gaps are not easy to exist at the top of a top mask layer formed in the groove 105 later, the pattern layer 112 is removed, the top mask layer is used as a mask etching substrate, a residual substrate and an isolation layer positioned on the residual substrate are formed, gaps are not easy to exist at the top of the isolation layer, a conductive layer is formed on the residual substrate between the isolation layers, and the conductive material forming the conductive layer is not easy to deposit at the top of the isolation layer, so that the probability of leakage current of the conductive layer is reduced, and the electrical performance of the semiconductor structure is optimized.
Specifically, the groove forming step includes:
As shown in fig. 13, a mask layer 106 is formed on the pattern material layer 104, the mask layer 106 includes a first mask layer 108 and a second mask layer 109 on the first mask layer 108, and the second mask layer 109 has an opening 107.
In the subsequent process, the patterned material layer 102 is etched by using the mask layer 106 as a mask, so as to form a patterned layer.
In this embodiment, the first mask layer 108 is in contact with the pattern material layer 102 in the mask layer 106, and the material of the first mask layer 108 includes an organic material layer.
The material of the first mask layer 108 includes an organic material layer. And after the pattern layer is formed later, the damage to the pattern layer is less in the process of removing the mask layer 106 on the pattern layer.
Specifically, the organic material layer includes: SOC (spin on carbon) or SOH (spin on hard mask) materials. In other embodiments, the organic material layer may further include one or more of ODL (organic DIELECTRIC LAYER ) material, DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide layer) material, and APF (ADVANCED PATTERNING FILM ) material.
In other embodiments, the first mask layer may be made of other materials that can function as a mask and are easy to remove, so that damage to the pattern material layer is reduced when the mask layer is subsequently removed, for example: one or more of silicon oxycarbide, ethyl orthosilicate, polysilicon, and oxygen doped silicon carbide.
In this embodiment, the first mask layer 108 is formed by a spin-coating process. The surface flatness of the first mask layer 108 is high.
In this embodiment, the second mask layer 109 includes a bottom anti-reflective coating 1091 (BARC) and a photoresist layer 1092 on the bottom anti-reflective coating 1091.
Specifically, the opening 107 is located in the photoresist layer 1092.
The step of forming the opening 107 includes: forming a photoresist material layer (not shown) on the bottom anti-reflection coating 1091; the photoresist material layer is subjected to exposure treatment, an opening 107 is formed in the photoresist material layer, and the remaining photoresist material layer serves as a photoresist layer 1092.
As shown in fig. 14 to 16, the second mask layer 109 is used as a mask to etch the pattern material layer 104, a groove 105 is formed in the pattern material layer 104, and the first mask layer 108 located on the top surface of the pattern material layer 104 is used as a protection layer 111.
In this embodiment, the pattern material layer 104 is etched by a dry etching process, and a groove 105 is formed in the pattern material layer 104. The dry etching process has anisotropic etching characteristics and good etching profile control, is favorable for enabling the shape of the groove 105 to meet the process requirements, and can etch the bottom anti-reflection coating 1091 and the pattern material layer 104 in the same etching equipment by changing etching gas, so that the process steps are simplified. In addition, in the etching process, the top of the substrate can be used as an etching stop position, so that damage to other film structures is reduced.
Specifically, the mask layer 106 is used as a mask, the pattern material layer 104 is etched by using an anisotropic reactive ion etching process (Reactive Ion Etching, RIE), and the grooves 105 are formed in the pattern material layer 104. In the anisotropic reactive ion etching process, a large amount of chemically active gas ions exist in plasma generated by gas discharge, and the ions interact with the surface of the material to cause chemical reaction of surface atoms, so that an etching effect is achieved. The reactive ion etching process is advantageous in reducing damage to the top of the substrate during etching to form the recess 105.
In this embodiment, in the step of etching the pattern material layer 104 to form the recess 105 in the pattern material layer 104, the second mask layer 109 is removed.
As shown in fig. 15 and 16, fig. 16 is a cross-sectional view of fig. 15 along the DD direction, and in this embodiment, the step of forming the protective layer 111 further includes: after the grooves 105 are formed, the first mask layer 108 with a partial thickness of the top surface of the pattern material layer 104 is etched, and the remaining first mask layer 108 located on the top surface of the pattern material layer 104 is used as a protection layer 111. In other embodiments, after the grooves are formed, the thickness of the first mask layer on the top surface of the pattern material layer is smaller, and the first mask layer on the top surface of the pattern material layer may not be etched.
After the grooves 105 are formed, the first mask layer 108 with a partial thickness on the top surface of the pattern material layer 104 is etched, so that the first mask layer 108 on the top surface of the pattern material layer 104 is not too thick, that is, the protective layer 111 on the top surface of the pattern material layer 104 is not too thick, and in the subsequent groove forming step, the film structure on the pattern material layer 104 is not too thick, so that the pattern material layer 104 is not easy to deform or bend.
In this embodiment, the material of the first mask layer 108 includes an organic material layer. Accordingly, the first mask layer 108 with a partial thickness is etched by an ashing process, so as to form the protective layer 111.
The process parameters of etching a portion of the thickness of the first mask layer 108 using an ashing process include: the reactive gas includes O 2 and N 2, and the carrier gas includes one or both of Ar and He.
In the step of forming the protective layer 111 by etching a portion of the thickness of the first mask layer 108 by an ashing process, the flow rate of the reaction gas should not be too large or too small. If the flow of the reaction gas is too large, the pressure in the reaction chamber is easily caused to be too large, the etching rate of the first mask layer 108 on the top surface of the pattern material layer 104 is too fast, the process control performance and the uniformity of the reaction rate of etching are reduced, damage is easily caused to the top surface of the pattern material layer 104, so that the junction area between the top surface of the pattern material layer 104 and the side wall of the groove 105 is easily damaged, the chamfer of the junction area between the top surface of the pattern material layer 104 and the side wall of the groove 105 is easily increased, gaps are easily formed at the top of the top mask layer formed in the groove 105, the pattern layer is removed, the top mask layer is used as a mask to etch the substrate, the residual substrate and the isolation layer positioned on the residual substrate are formed, gaps are easily formed at the top of the isolation layer, the conductive material forming the conductive layer is easily deposited at the top of the isolation layer on the residual substrate between the isolation layer, and the probability of leakage current of the conductive layer is not easily reduced. The too small flow of the reaction gas may easily cause too small pressure in the reaction chamber, and the etching rate of the first mask layer 108 etching the top surface of the patterned material layer 104 is too slow, which is not beneficial to improving the forming rate of the protective layer 111. In this embodiment, in the step of forming the protective layer 111 by etching a portion of the first mask layer 108 with a thickness using an ashing process, the flow rate of the reaction gas is 50sccm to 300sccm.
In the step of forming the protective layer 111 by etching a portion of the thickness of the first mask layer 108 using an ashing process, the chamber pressure should not be too high or too low. If the pressure of the chamber is too high, the decomposition rate of the by-product generated by the first mask layer 108 on the top surface of the patterned material layer 104 is too low, and correspondingly, the rate of the by-product discharged from the chamber is too low, and the pressure of the chamber is too high, which also easily causes the carrier 200 exposed by the second mask layer 205 to be etched by etching gas, so that the top surface of the patterned material layer 104 is easily damaged, and therefore, the junction area between the top surface of the patterned material layer 104 and the sidewall of the groove 105 is easily damaged, the chamfer of the junction area between the top surface of the patterned material layer 104 and the sidewall of the groove 105 is easily enlarged, gaps are easily formed at the top of the top mask layer formed in the groove 105, the patterned layer is removed, the top mask layer is used as a mask etching substrate, a residual substrate and an isolation layer positioned on the residual substrate are easily formed, gaps are easily formed at the top of the isolation layer, a conductive layer is formed on the residual substrate between the isolation layer, and the conductive material forming the conductive layer is easily deposited at the top of the isolation layer, so that the probability of easily reducing the leakage current of the conductive layer is not facilitated. If the chamber pressure is too low, the low density of the plasma of the etching gas in the chamber tends to result in a low etching rate of the first mask layer 108 on the top surface of the patterned material layer 104, which is not beneficial to improving the formation rate of the protective layer 111. In this embodiment, in the step of forming the protective layer 111 by etching a portion of the first mask layer 108 with a thickness using an ashing process, the chamber pressure is 5mTorr to 30mTorr.
In other embodiments, in the step of forming the recess in the pattern material layer by an etching process, the second mask layer may further have residues. Correspondingly, in the step of etching the first mask layer with the partial thickness of the top surface of the graph material layer, the second mask layer is removed.
In other embodiments, when the material of the first mask layer includes one or more of silicon oxycarbide, tetraethyl orthosilicate, polysilicon, and oxygen-doped silicon carbide, a dry etching process is used to etch the first mask layer with a thickness of a top portion of the pattern material layer, so as to form the protection layer.
As shown in fig. 17 and 18, fig. 18 is a cross-sectional view of fig. 17 in the EE direction, the pattern material layer 102 is subjected to a plurality of groove forming steps, and grooves 105 are sequentially formed at a plurality of positions of the pattern material layer 102, and the remaining pattern material layer 104 is used as a pattern layer 112.
The recesses 105 provide for the subsequent formation of a top mask layer over the substrate between the pattern layers 112.
In the step of forming the recess, the protective layer 111 on the top surface of the pattern material layer 104 is preferably not too thick or too thin. In the next groove forming step, a mask layer is formed on the pattern material layer 104, if the protective layer 111 on the top surface of the pattern material layer 104 is too thick, after the mask layer is formed on the protective layer 111, the film layer on the top surface of the pattern material layer 104 is too thick, and the pattern material layer 104 is easy to bend or incline, so that the formation quality of the groove 105 is poor, the appearance quality of the top mask layer correspondingly filled in the groove 105 is poor, and after the pattern layer 104 is removed, the quality of an isolation layer formed by etching the substrate by taking the top mask layer as a mask is poor, and the isolation layer cannot well play a role in electrically isolating the conductive layer. If the protective layer 111 on the top surface of the patterned material layer 104 is too thin, in the process of etching the first mask layer 108 with a partial thickness to form the protective layer 111, the top of the patterned material layer 104 is easily damaged, so that the quality of the formation of the recess 105 is poor, and after the patterned layer 104 is subsequently removed, the quality of the isolation layer formed by etching the substrate with the top mask layer as a mask is poor, and the isolation layer cannot well play a role in electrically isolating the conductive layer. In this embodiment, in the recess forming step, the thickness of the protective layer 111 on the top surface of the patterned material layer 104 isTo the point of
Referring to fig. 19, after the pattern layer 112 is formed, the protective layer 111 is removed.
After the pattern layer 112 is formed, the protective layer 111 is removed, so that the material of the junction area between the top surface of the pattern layer 112 and all the side walls of the groove 105 is damaged only once, and therefore, the chamfer angle at the top of the side walls of the groove 105 is smaller, gaps are not easy to exist at the top of a top mask layer formed in the groove 105 later, the pattern layer 112 is removed, the top mask layer is used as a mask etching substrate, a residual substrate and an isolation layer positioned on the residual substrate are formed, gaps are not easy to exist at the top of the isolation layer, a conductive layer is formed on the residual substrate between the isolation layers, and the conductive material forming the conductive layer is not easy to deposit at the top of the isolation layer, so that the probability of leakage current of the conductive layer is reduced, and the electrical performance of the semiconductor structure is optimized.
The protective layer 111 is removed to provide room for a subsequent formation of a top mask layer on the substrate between the patterned layers 112.
In this embodiment, the material of the protective layer 111 includes an organic material layer, and an ashing process is used to remove the protective layer 111. In other embodiments, a dry etching process may also be used to remove the protective layer.
In the step of removing the protective layer 111 by an ashing process, the damage to the pattern layer 112 is less.
Referring to fig. 20, the method for forming the semiconductor structure further includes: after removing the protective layer 111, a top mask layer 113 is formed in the recess 105.
The top mask layer 113 serves as an etch mask for subsequent etching of the substrate.
In this embodiment, the material of the top mask layer 113 includes silicon nitride. Silicon nitride has higher process compatibility and is a material with common process and lower cost.
The step of forming a top mask layer 113 in the recess 105 includes: conformally covering the graphics layer 112 and a top mask material layer (not shown) on the substrate between the graphics layers 112; the top mask material layer above the pattern layer 112 is removed and the remaining top mask material layer in the recess 105 serves as a top mask layer 113.
In this embodiment, the top mask material layer is formed using an atomic layer deposition process (Atomic layer deposition, ALD). The atomic layer deposition process comprises multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the top mask material layer, so that the thickness of the top mask material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, the probability of occurrence of voids in the top mask material layer is reduced, and the formation quality of the top mask layer 113 is correspondingly improved. In other embodiments, the top mask material layer may also be formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
In this embodiment, a chemical mechanical polishing (CHEMICAL MECHANICAL planarization, CMP) process is used to remove the top mask material layer above the pattern layer 112. The cmp process is a global surface planarization technique that accurately and uniformly removes the top mask material layer above the patterned layer 112.
The chamfer at the top of the sidewall of the recess 105 is smaller, so that a gap (sea) is not easily formed at the top of the top mask layer 113.
Referring to fig. 21, the method for forming the semiconductor structure further includes: removing the pattern layer 112, and etching the substrate by taking the top mask layer 113 as a mask to form a residual substrate 115 and an isolation layer 116 positioned on the residual substrate 115; a conductive layer 114 is formed in the remaining substrate 115 between the isolation layers 116.
The top of the top mask layer 113 is not easy to have a gap, so that in the process of etching the substrate by using the top mask layer 113 as a mask, the top of the formed isolation layer 116 is not easy to have a gap, and correspondingly, in the process of forming the conductive layer 114, the top of the isolation layer 116 is not easy to form a conductive material, thereby being beneficial to reducing the probability of leakage current of the conductive layer 114 and improving the electrical performance of the semiconductor structure.
Specifically, the remaining substrate 115 and isolation layer 116 are formed by etching the dielectric layer 100.
The dielectric layer 100 is a low-K dielectric material, and correspondingly, the isolation layer 116 is also a low-K dielectric material.
The isolation layer 116 serves to electrically isolate the conductive layers 114 and can reduce the capacitive coupling effect between the conductive layers 114.
The conductive layer 114 is used as an interconnect structure.
In this embodiment, the material of the conductive layer 114 is Cu. In other embodiments, the material of the conductive layer may be a conductive material such as TaN, tiN, or Co.
The step of forming the conductive layer 114 includes: forming a conductive material layer on the isolation layer 116 and the remaining substrate 115 between the isolation layers 116; the layer of conductive material above the isolation layer 116 is removed, with the remaining layer of conductive material acting as the conductive layer 114.
In this embodiment, the conductive material layer is formed by an electrochemical plating process. The electrochemical plating process has the advantages of simple operation, high deposition speed, low cost and the like.
In this embodiment, a wet etching process is used to remove the pattern layer 112, so as to form a trench surrounded by the top mask layer 113 and the substrate. The wet etching process has higher etching rate, simple operation and low process cost.
The material of the pattern layer 112 comprises silicon and the material of the second buffer material layer 103 on top of the substrate comprises TEOS. Accordingly, the etching solution used in the wet etching process includes a tetramethylammonium hydroxide (TMAH) solution. The etching rate of the tetramethyl ammonium hydroxide solution to Si is larger than that to TEOS material.
It should be noted that, the method for forming the semiconductor structure further includes: after forming the remaining substrate 115 and isolation layer 116, the remaining first buffer material layer 101, hard mask layer 102 and second mask layer 103 are removed before forming the conductive material layer.
Correspondingly, with continued reference to fig. 21, the embodiment of the present invention further provides a transistor formed by using the foregoing forming method.
The transistor includes: a remaining substrate 115; an isolation layer 116, which is separated from the remaining substrate 115; a conductive layer 114 on the remaining substrate 115 between the isolation layers 116.
In the transistor, a gap is not easy to exist at the top of the isolation layer 116, and in the corresponding process of forming the conductive layer 114, the conductive material is not easy to form at the top of the isolation layer 116, so that the probability of leakage current of the conductive layer 114 is reduced, and the electrical performance of the transistor is improved.
The isolation layer 116 serves to electrically isolate the conductive layer 114.
In this embodiment, the material of the isolation layer 116 is a low-k dielectric material, which is beneficial to reduce parasitic capacitance between the conductive layers 114, and thus beneficial to reduce the RC delay of the back-end.
Specifically, the material of the isolation layer 116 includes SiCOH.
It should be noted that the bottom of the remaining substrate further includes a gate structure, and source-drain doped regions located at two sides of the gate structure, and a contact plug (not shown) contacting with the source-drain doped regions is further formed in the substrate.
The conductive layer 114 is used as an interconnect structure.
In this embodiment, the material of the conductive layer 114 is Cu. In other embodiments, the material of the conductive layer may be a conductive material such as TaN, tiN, or Co.
The semiconductor structure of this embodiment may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
Forming a pattern material layer on the substrate;
And carrying out a plurality of groove forming steps on the graph material layer, forming grooves at a plurality of positions of the graph material layer in sequence, wherein the rest graph material layer is used as the graph layer, and the groove forming step comprises the following steps: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer is positioned on the top surface of the graphic material layer and is used as a protective layer; removing the second mask layer;
And removing the protective layer after the pattern layer is formed.
2. The method of forming a semiconductor structure according to claim 1, wherein in the recess forming step, a thickness of the protective layer on the top surface of the pattern material layer isTo the point of
3. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the recess, the second mask layer is removed;
the step of forming the protective layer further includes: and after the grooves are formed, etching the first mask layer with partial thickness on the top surface of the pattern material layer, wherein the first mask layer remaining on the top surface of the pattern material layer is used as a protective layer.
4. The method of forming a semiconductor structure of claim 1, wherein the step of forming the protective layer further comprises: after the grooves are formed, etching the first mask layer with partial thickness on the top surface of the graph material layer, wherein the residual first mask layer on the top surface of the graph material layer is used as a protective layer; and in the step of etching the first mask layer with the partial thickness of the top surface of the graph material layer, removing the second mask layer.
5. The method of forming a semiconductor structure as claimed in claim 3 or 4, wherein the first mask layer is etched by ashing to a thickness of a top portion of the pattern material layer, thereby forming the protective layer.
6. The method of claim 5, wherein etching a portion of the thickness of the first mask layer using an ashing process comprises: the reactive gas comprises O 2 and N 2, the carrier gas comprises one or two of Ar and He, the flow rate of the reactive gas is 50sccm to 300sccm, and the chamber pressure is 5mTorr to 30mTorr.
7. The method of forming a semiconductor structure of claim 3 or 4, wherein the material of the protective layer comprises an organic material layer.
8. The method of forming a semiconductor structure of claim 7, wherein the material of the organic material layer comprises: one or more of an SOC material, SOH material, ODL material, DUO material, and APF material.
9. The method of forming a semiconductor structure of claim 3 or 4, wherein the material of the first mask layer comprises one or more of silicon oxycarbide, ethyl orthosilicate, polysilicon, and oxygen doped silicon carbide.
10. The method of claim 9, wherein the first mask layer is etched to a thickness of a top portion of the patterned material layer using a dry etching process to form the protective layer.
11. The method of forming a semiconductor structure of claim 1, wherein the second mask layer comprises a bottom anti-reflective coating and a photoresist layer on the bottom anti-reflective coating.
12. The method of forming a semiconductor structure of claim 11, wherein the opening is in the photoresist layer.
13. The method of claim 1, wherein the patterning material layer is etched using an anisotropic reactive ion etching process with the mask layer as a mask, and the recess is formed in the patterning material layer.
14. The method of forming a semiconductor structure of claim 1, further comprising: after removing the protective layer, forming a top mask layer in the groove;
Removing the pattern layer, and etching the substrate by taking the top mask layer as a mask to form a residual substrate and an isolation layer positioned on the residual substrate;
and forming a conductive layer on the rest substrate between the isolation layers.
15. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises a dielectric layer.
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| CN109585279A (en) * | 2018-11-30 | 2019-04-05 | 上海华力微电子有限公司 | A kind of forming method of autoregistration bilayer figure |
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| CN109755175B (en) * | 2017-11-03 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Interconnect structure and method of forming the same |
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| CN109585279A (en) * | 2018-11-30 | 2019-04-05 | 上海华力微电子有限公司 | A kind of forming method of autoregistration bilayer figure |
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