CN106299108A - Resistance-variable storing device and preparation method thereof - Google Patents

Abstract

The invention discloses a resistive variable memory, which includes a first electrode, a resistive material layer, and a second electrode stacked on a substrate in sequence, and also includes an interval formed at the interface between the first electrode and the resistive material layer or/ and a conductive bump array at the interface between the second electrode and the resistive material layer. In the resistive variable memory, uniformly distributed and controllable conductive bump arrays are prepared at the interface between the first electrode or/and the second electrode and the resistive switch material layer, so that the electric field is concentrated on the conductive bump array, increasing the conductive bump array. The probability of forming a conductive channel at the array is improved, thereby improving the stability of the resistive memory and improving the uniformity of the resistive memory. The present invention also discloses a method for preparing the above-mentioned resistive variable memory, including: A, the step of preparing a first electrode, a resistive material layer, and a second electrode on a substrate; B, at the interface between the first electrode and the resistive material layer Or/and a step of preparing a conductive protrusion array at the interface between the second electrode and the resistive material layer.

Description

Resistive memory and its preparation method

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a resistive variable memory capable of improving the uniformity of the resistive variable memory and a preparation method thereof.

Background technique

Resistive RAM (RRAM) has the advantages of simple structure, fast read and write speed, low operating power consumption, high storage density, compatibility with existing CMOS (complementary metal oxide semiconductor) process technology, great potential for further scaling down, and multi- Value storage and other features, so it is a strong competitor for the next generation of general-purpose memory.

The traditional resistive memory is a typical sandwich structure: a layer of resistive material is added between the upper and lower electrodes. Its working principle is to apply voltages of different sizes or polarities to both ends of the resistive material layer to control The resistance value of the layer is switched between high and low resistance states to realize the writing and erasing of data. The widely accepted conductive filament theory believes that during the resistive switching process, oxygen vacancies or metal ions in the resistive material layer migrate to form conductive filaments. When the conductive filaments are connected to the upper and lower electrodes, the resistive variable memory enters the low Resistance state; when an appropriate voltage is applied again, the conductive filament breaks and enters a high-resistance state, so the change in resistance is due to the fracture and formation of the conductive filament. Since this kind of fracture and formation is random, the morphology and distribution of conductive filaments are different during multiple resistance switching processes, so the electrical parameters of the resistance switching material layer (set voltage, reset voltage, high and low resistance state resistance, etc.) ) has great volatility, which seriously reduces the stability and reliability of the RRAM operation. Therefore, how to effectively control the formation and fracture of conductive filaments has become a key core issue to improve the performance of memory devices.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a resistive variable resistor and a preparation method thereof. The resistive variable resistor effectively improves the uniformity of the resistive variable memory by preparing a conductive bump array.

In order to achieve the above-mentioned purpose of the invention, the present invention has adopted following technical scheme:

A resistive variable memory, comprising a substrate, a first electrode, a resistive material layer, and a second electrode stacked in sequence, and further comprising: an interval formed at the interface between the first electrode and the resistive material layer or/and the The conductive protrusion array at the interface between the second electrode and the resistive material layer.

Further, the material of the conductive bump array is selected from any one of Pt, Cu, Al, Ti, Ni and Au.

Further, the height of the array of conductive bumps is 1nm-5nm;

Further, the pitch of the array of conductive protrusions is 50 nm˜50 μm.

Further, the thickness of the resistive material layer is 5nm-200nm.

Further, the material of the resistive material layer is selected from at least one of hafnium oxide, titanium oxide, zirconium oxide, zinc oxide, tungsten oxide, and tantalum oxide; the material of the substrate is selected from a silicon substrate, a glass substrate bottom, flexible substrate; the material of the lower electrode is selected from any one of Pt, Cu, Al, Ti, Ni, TiN; the material of the upper electrode is selected from Pt, Cu, Al, Any one of Ti, Ni, TiN.

Another object of the present invention is to provide a method for preparing a resistive variable memory as described above, including: A, the steps of preparing a first electrode, a resistive material layer, and a second electrode on a substrate; The step of preparing a conductive protrusion array at the interface between the first electrode and the resistive material layer or/and at the interface between the second electrode and the resistive material layer.

Further, the step of preparing the conductive bump array specifically includes: coating the nanosphere array at the interface between the first electrode and the resistive material layer or/and at the interface between the second electrode and the resistive material layer by using a spin coating method ; Using self-assembly technology to self-assemble the nanosphere array to form a nanosphere layer; using the nanosphere layer as a mask, depositing a metal film on the nanosphere layer; wherein, the deposition method is selected from chemical vapor phase Any one of deposition, physical vapor deposition, electron beam evaporation, sputtering, atomic layer deposition, and thermal evaporation; removing the nanosphere layer by etching to form the array of conductive protrusions.

Further, the number of layers of the nanosphere layer is 1-2 layers.

Further, the material of the nanosphere layer is selected from any one of polystyrene and silicon dioxide.

The present invention prepares a uniformly distributed and controllable conductive bump array at the interface of the first electrode or/and the second electrode and the resistive material layer by using nanosphere photolithography technology, so that the electric field is concentrated on the conductive bump array, increasing the The probability of forming a conductive channel at the conductive bump array is improved, thereby improving the working stability of the resistive variable memory and improving the uniformity of the resistive variable memory.

Description of drawings

The above and other aspects, features and advantages of embodiments of the present invention will become more apparent through the following description in conjunction with the accompanying drawings, in which:

1 is a schematic structural diagram of a resistive variable memory according to Embodiment 1 of the present invention;

2 is a flow chart of the steps of the method for preparing a resistive memory according to Embodiment 1 of the present invention;

Fig. 3 is the structural representation of the nanosphere layer according to embodiment 1 of the present invention;

4 is a schematic structural view of a conductive bump array according to Embodiment 1 of the present invention;

5 is a schematic structural diagram of a resistive memory according to Embodiment 2 of the present invention;

6 is a flow chart of the steps of the method for manufacturing a resistive variable memory according to Embodiment 2 of the present invention;

Figure 7 is a schematic structural view of a nanosphere layer according to Embodiment 2 of the present invention;

FIG. 8 is a schematic structural diagram of a conductive bump array according to Embodiment 2 of the present invention.

detailed description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, the embodiments are provided to explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to particular intended uses. In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.

Example 1

FIG. 1 is a schematic structural diagram of a resistive variable memory according to Embodiment 1 of the present invention.

Referring to FIG. 1, the resistive variable memory according to Embodiment 1 of the present invention includes a substrate 10; a first electrode 20, a resistive material layer 30, and a second electrode 40 sequentially stacked on the substrate 10; The conductive protrusion array 50 formed on the surface of the first electrode 20 is spaced between the first electrode 20 and the resistive material layer 30 .

In this embodiment, the material of the above-mentioned conductive bump array 50 is Pt, and the height of the conductive bump array is about 5nm, and the pitch is 50nm; but the present invention is not limited thereto, the material of the conductive bump array can also be selected Any one of Cu, Al, Ti, Ni, Au, and the height of the conductive bump array is limited to 1nm-5nm, and the spacing is controlled to be 50nm-50μm.

The conductive bump array 50 formed at the interface between the first electrode 20 and the resistive material layer 30 can concentrate the electric field on the conductive bump array 50, increasing the probability of forming a conductive channel at the conductive bump array 50, thereby improving the The working stability of the resistive variable memory improves the uniformity of the resistive variable memory.

Preferably, in this embodiment, the substrate 10 is a silicon substrate; the material of the first electrode 20 formed on the silicon substrate is Pt; the material of the resistive material layer 30 formed on the first electrode 20 is oxide Zirconium, and its thickness is 60nm; The material of the second electrode 40 formed on the resistive material layer 30 is Pt; But the present invention is not limited thereto, as the material of substrate 10 can also be glass substrate or flexible substrate etc., the material of the first electrode 20 and the second electrode 40 can also be selected from any one of Cu, Al, Ti, Ni, TiN, and the material of the resistive material layer 30 can also be selected from titanium oxide, hafnium oxide, Any one of zinc oxide, tungsten oxide, tantalum oxide or a mixture thereof, and the thickness of the resistive material layer 30 is not limited to 60nm, it only needs to be controlled within the range of 5nm-200nm.

The method for manufacturing the above-mentioned resistive memory will be described in detail below with reference to the flow chart of the steps of the method for manufacturing the resistive memory shown in FIG. 2 .

Referring to FIG. 2 , the flow chart of the steps of the manufacturing method of the resistive variable memory according to Embodiment 1 of the present invention includes the following steps:

In step 110 , metal Pt is deposited on the substrate 10 to form the first electrode 20 . Specifically, the substrate 10 is a silicon substrate.

In step 120 , nanospheres are formed on the first electrode 20 , and a nanosphere array is formed by using self-assembly technology to form a nanosphere layer 61 . Specifically, a spin-coating method is used to form the nanospheres, and the material of the nanospheres is polystyrene.

In this embodiment, the number of layers of the nanosphere layer 61 is one layer, and the top view of the nanosphere layer 61 is shown in Figure 3. In Figure 3, a gap 62 is formed between the polystyrene nanospheres arranged in an array. and b-gap 63 two kinds of gaps.

In step 130 , metal Pt is deposited on the nanosphere layer 61 , and a metal thin film is formed on the surface of the nanosphere layer 61 , a void 62 and b void 63 . Specifically, metal Pt is deposited on the nanosphere layer 61 by electron beam evaporation.

It should be noted that the metal thin film deposited on the nanosphere layer 61 may be any one of chemical vapor deposition, physical vapor deposition, sputtering, atomic layer deposition, and thermal evaporation.

In step 140 , the nanosphere layer 61 is removed by etching, and the conductive protrusion array 50 is formed on the first electrode 20 . That is to say, in this embodiment, the conductive bump array 50 is essentially metal Pt deposited at the a-gap 62 and the b-gap 63 with the nanosphere layer 61 as a mask. The structure schematic diagram of the conductive bump array 50 As shown in Figure 4.

The conductive bump array 50 prepared through steps 120-140 has a height of 5 nm and a pitch of 50 nm. It is worth noting that the height of the conductive bump array 50 can be controlled in the range of 1 nm to 5 nm, and the pitch can be controlled in the range of 50 nm to 50 μm, and the height and pitch of the conductive bump array 50 can be adjusted by controlling the polystyrene The particle size of the ethylene nanospheres is sufficient, so the array of conductive protrusions 50 is a uniform and controllable array.

The material of the conductive bump array 50 is not limited to metal Pt, and other metals such as Cu, Al, Ti, Ni, Au, etc. are also acceptable.

In step 150 , a resistive material layer 30 is formed on the first electrode 20 and the conductive bump array 50 . Specifically, the formation method of the resistive material layer 30 is a sputtering method.

Specifically, the resistive material layer 30 is a zirconia layer with a thickness of 60 nm.

In step 160 , the second electrode 40 is formed on the resistive material layer 30 .

Specifically, the material of the second electrode 40 is metal Pt, and the formation method of the second electrode 40 is a photolithography method and a lift-off method.

In this embodiment, the process of forming the first electrode 20 , the resistive material layer 30 and the second electrode 40 layer by layer on the substrate 10 is a common method used by those skilled in the art, and the process will not be repeated here.

In the resistive variable memory prepared through the above steps 110-160, the conductive bump array 50 is prepared at the interface between the first electrode 20 and the resistive switch material layer 30, so that the electric field can be concentrated on the conductive bump array 50, and the conductive bump array 50 can be increased. The probability of forming a conductive channel at the array 50 is improved, thereby improving the stability of the RRAM and improving the uniformity of the RRAM.

Example 2

In the description of Embodiment 2, the similarities with Embodiment 1 will not be repeated here, and only the differences with Embodiment 1 will be described. The difference between Embodiment 2 and Embodiment 1 is that, referring to FIG. 5 , the resistive variable memory according to Embodiment 2 of the present invention includes a substrate 10; The material layer 30 , the second electrode 40 ; and the array of conductive protrusions 50 arranged between the second electrode 40 and the resistive material layer 30 and formed on the surface of the resistive material layer 30 at intervals.

Referring to FIG. 6 is a flow chart of the steps of the manufacturing method of the RRAM according to Embodiment 2 of the present invention.

In step 210 , metal Pt is deposited on the substrate 10 to form the first electrode 20 , and the resistive material layer 30 is formed on the first electrode 20 . Specifically, the substrate 10 is a glass substrate, and the resistive material layer 30 is formed by atomic layer deposition.

In this embodiment, the resistive switch material layer 30 is a mixed layer of aluminum oxide and hafnium oxide with a thickness of 5 nm.

In step 220 , nanospheres are formed on the resistive material layer 30 , and a nanosphere array is formed by using self-assembly technology to form the nanosphere layer 61 . Specifically, a spin coating method is used to form the nanospheres, and the material of the nanospheres is silicon dioxide.

In the present embodiment, the number of layers of the nanosphere layer 61 is two layers. The top view of the nanosphere layer 61 is shown in FIG. 6. In FIG. A kind of void.

In step 230 , metal Pt is deposited on the nanosphere layer 61 , and a metal thin film is formed on the surface of the nanosphere layer 61 and the c-space 64 . Specifically, metal Pt is deposited on the nanosphere layer 61 by electron beam evaporation.

In step 240 , the nanosphere layer 61 is removed by etching, and the conductive protrusion array 50 is formed on the resistive material layer 30 . That is to say, in this embodiment, the conductive bump array 50 is essentially metal Pt deposited at the c-gap 64 with the nanosphere layer 61 as a mask. The schematic structural diagram of the conductive bump array 50 is shown in FIG. 8 Show.

The conductive bump array 50 prepared through steps 220-240 has a height of 1 nm and a pitch of 50 μm.

In step 250 , the second electrode 40 is formed on the resistive material layer 30 and the conductive bump array 50 .

Specifically, the material of the second electrode 40 is metal Pt, and the formation method of the second electrode 40 is a photolithography method and a lift-off method.

In this embodiment, the process of forming the first electrode 20 , the resistive material layer 30 and the second electrode 40 layer by layer on the substrate 10 is a common method used by those skilled in the art, and the process will not be repeated here.

In the resistive variable memory prepared through the above steps 210-250, the conductive bump array 50 is prepared at the interface between the second electrode 40 and the resistive switch material layer 30, so that the electric field can be concentrated on the conductive bump array 50, and the conductive bump array 50 can be increased. The probability of forming a conductive channel at the array 50 is improved, thereby improving the stability of the RRAM and improving the uniformity of the RRAM.

It is worth noting that the preparation of the conductive bump array 50 at the interface between the first electrode 20 or the second electrode 40 and the resistive material layer 30 is to concentrate the electric field on the conductive bump array 50, which increases the number of conductive bump arrays. The probability of forming a conductive channel at 50, thereby improving the stability of the resistive memory and improving the uniformity of the resistive memory; therefore, if at the interface between the first electrode 20 and the resistive material layer 30, and the second electrode 4 and Conductive bump arrays 50 are prepared at the interface of the resistive variable material layer 30, which can also achieve the purpose of improving the uniformity of the resistive variable memory according to the present invention, and still belong to the protection scope of the present invention.

While the invention has been shown and described with reference to particular embodiments, it will be understood by those skilled in the art that changes may be made in the form and scope thereof without departing from the spirit and scope of the invention as defined by the claims and their equivalents. Various changes in details.

Claims (10)

1. a resistance-variable storing device, including lamination successively arrange substrate, the first electrode, resistance change material layer, Second electrode, it is characterised in that also include: be formed at described first electrode and resistive material bed boundary or/ With the conductive bumps array at described second electrode and resistive material bed boundary.

Resistance-variable storing device the most according to claim 1, it is characterised in that described conductive bumps array Material is selected from any one in Pt, Cu, Al, Ti, Ni, Au.

Resistance-variable storing device the most according to claim 1 and 2, it is characterised in that described conductive bumps battle array The height of row is 1nm～5nm.

Resistance-variable storing device the most according to claim 1 and 2, it is characterised in that described conductive bumps battle array The spacing of row is 50nm～50 μm.

Resistance-variable storing device the most according to claim 1, it is characterised in that the thickness of described resistance change material layer Degree is 5nm～200nm.

Resistance-variable storing device the most according to claim 1, it is characterised in that the material of described resistance change material layer At least one in hafnium oxide, titanium oxide, zirconium oxide, zinc oxide, tungsten oxide, tantalum oxide of material；Institute State any one in silicon substrate, glass substrate, flexible substrate of the material of substrate；Described bottom electrode Material is selected from any one in Pt, Cu, Al, Ti, Ni, TiN；The material of described upper electrode selected from Pt, Any one in Cu, Al, Ti, Ni, TiN.

7. the preparation method of the resistance-variable storing device as described in claim 1-6 is arbitrary, it is characterised in that Including:

A, prepare on substrate the first electrode, resistance change material layer, the step of the second electrode；

B, at described first electrode and resistive material bed boundary or/and described second electrode and resistance change material layer The step of conductive bumps array is prepared in interface.

Preparation method the most according to claim 7, it is characterised in that prepare the step of conductive bumps array Suddenly specifically include:

Use spin-coating method at described first electrode and resistive material bed boundary or/and described second electrode and resistive Nanosphere array it is coated with at material bed boundary；

Use self-assembling technique that described nanosphere array is self-assembly of nanometer layers of balls；

With described nanometer layers of balls as mask, use formation of deposits metallic film in described nanometer layers of balls；Wherein, Described deposition process is selected from chemical gaseous phase deposition, physical vapour deposition (PVD), electron beam evaporation, sputtering, atomic layer Deposition, any one in thermal evaporation；

Nanometer layers of balls described in erosion removal, forms described conductive bumps array.

Preparation method the most according to claim 8, it is characterised in that the number of plies of described nanometer layers of balls is 1～2 layer.

Preparation method the most according to claim 8 or claim 9, it is characterised in that described nanometer layers of balls Material is selected from any one in polystyrene, silicon dioxide.