CN106298714A - Semiconductor structure - Google Patents

Abstract

The invention provides a semiconductor structure, which comprises a substrate, a plurality of welding pads, a plurality of welding flux layers and an electronic element. The substrate comprises a core layer, a metal layer and a dielectric layer, wherein the metal layer is arranged on the dielectric layer, and the dielectric layer is arranged on the core layer and comprises at least one groove. The bonding pad is disposed on the dielectric layer and electrically connected to the metal layer. The groove is arranged between any two adjacent welding pads. The solder layers are respectively arranged on the solder pads. The electronic element is arranged on the welding pad through the welding flux layer, thereby avoiding the problems of bridging phenomenon and short circuit of the welding flux convex block in the process of reflow soldering and further improving the production yield.

Description

semiconductor structure

technical field

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure avoiding solder bridging.

Background technique

In recent years, with the rapid development of electronic technology and the emergence of high-tech electronic industries, more humanized and better functional electronic products are constantly being introduced, and are moving towards the trend of lightness, thinness, shortness and smallness. Under this trend, because the circuit board has the advantages of fine wiring, compact assembly and good performance, the circuit board has become one of the main media for carrying multiple electronic components (such as chips) and electrically connecting these electronic components to each other. .

Flip chip packaging is a way of packaging chips and circuit boards. The circuit board has a plurality of welding pads, and the circuit board can be electrically connected to the chip through reflow soldering arranged on the welding pads. In recent years, due to the increasing number of signals that need to be transmitted between electronic components (such as chips), the number of pads required for circuit boards is also increasing. However, the space on the circuit board is limited, so the distance between the pads Towards fine pitch (fine pitch) development.

However, when solder bumps are placed on these solder pads and bonded to the chip by reflow, these solder bumps will be in a molten state due to the heat of reflow, because these pads are arranged on the surface of the substrate with a fine pitch , so it is easy to cause bridging and short circuit problems in the molten solder bumps during the reflow process, and it is impossible to provide a fine-pitch electrical connection structure. Generally speaking, although the usage of the solder bumps has been strictly calculated, there are still many variables that will cause the solder bumps to overflow after being heated, such as heating temperature, heating time, Subtle factors such as the material itself may cause overflow, especially on substrates with limited space, the impact may be greater.

Contents of the invention

The invention provides a semiconductor structure, which avoids bridging phenomenon and short circuit of solder bumps during reflow process, thereby improving production yield.

The semiconductor structure of the present invention includes a substrate, a plurality of bonding pads, a plurality of solder layers, and electronic components. The substrate includes a core layer, a metal layer and a dielectric layer. The metal layer is disposed on the dielectric layer. The dielectric layer is disposed on the core layer and includes at least one groove. The welding pad is disposed on the dielectric layer and electrically connected with the metal layer. The trench is disposed between any two adjacent pads. The solder layers are respectively disposed on the pads. The electronic components are disposed on the pads through the solder layer.

In an embodiment of the present invention, opposite sidewalls of the aforementioned trench are parallel to each other.

In an embodiment of the present invention, the surfaces of the opposite sidewalls of the aforementioned trench are rough surfaces.

In an embodiment of the present invention, the distance between the opposite sidewalls of the trench decreases gradually toward the core layer.

In an embodiment of the present invention, there are multiple at least one trench, and two of the trenches are disposed between any two adjacent pads.

In an embodiment of the present invention, the depth of each of the aforementioned grooves is between 10 microns and 50 microns.

In an embodiment of the present invention, each of the aforementioned trenches exposes the core layer.

In an embodiment of the present invention, the bottom surface of the groove is a rough surface.

In an embodiment of the present invention, the above-mentioned semiconductor structure further includes a solder resist layer disposed on the dielectric layer and exposing the solder pad.

In an embodiment of the present invention, the aforementioned substrate is a printed circuit board.

Based on the above, the semiconductor structure of the present invention is provided with at least one groove between any two adjacent pads on its substrate, so that the solder on the pad can be extended by using the groove between any two adjacent pads. The flow path of the layer in the molten state allows the solder layers on any two adjacent pads to be separated from each other by corresponding grooves, thus greatly reducing the solder on any two adjacent pads due to their close spacing. Therefore, the semiconductor structure of the present invention can have a higher production yield.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1E are schematic cross-sectional views of a fabrication process of a semiconductor structure according to an embodiment of the present invention;

2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

Explanation of reference signs:

100, 100a～100d: semiconductor structure;

110: substrate;

112: core layer;

112a: core circuit layer;

114: metal layer;

116: dielectric layer;

116a: groove;

116b: rough surface;

120: welding pad;

130: solder block;

132: solder layer;

140: electronic components;

150: Solder mask.

detailed description

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed descriptions of the embodiments with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Accordingly, the directional terms used are illustrative, not limiting, of the invention. Also, in the following embodiments, the same or similar components will be given the same or similar symbols.

1A to 1E are schematic cross-sectional views of a fabrication process of a semiconductor structure according to an embodiment of the present invention. The manufacturing method of the semiconductor structure of this embodiment includes the following steps: first, please refer to FIG. layer 116 , and the dielectric layer 116 is disposed on the core layer 112 . In this embodiment, the metal layer 114 can be fabricated by, for example, pressing a metal foil on the dielectric layer 116 and patterning the metal foil to form the metal layer 114 as shown in FIG. 1A . Of course, the present invention is not limited thereto. In an embodiment of the present invention, the substrate 110 may include a plurality of dielectric layers 116 and a plurality of metal layers 114, the dielectric layer 116 may be disposed on at least two opposite surfaces of the core layer 112, and the metal layer 114 may be disposed on On each dielectric layer 116 and the core layer 112 , they are electrically connected to each other through conductive elements such as via holes. Specifically, the substrate 110 may be a printed circuit board (printed circuit board, PCB). Of course, the present invention does not limit the type, number of layers and manufacturing method of the substrate 110. In fact, the substrate 110 can also be a glass fiber substrate, BT (Bismaleimide Triacine) resin substrate, glass fiber epoxy resin copper foil (FR4) substrate or Substrates of other similar materials.

Next, referring to FIG. 1B , at least one trench 116 a is formed on the dielectric layer 116 . In this embodiment, the method for forming the trench 116a on the dielectric layer 116 may include laser cutting, and the trench 116a may or may not expose the underlying core layer 112 as shown in FIG. 1C , In other words, the trench 116 a may or may not penetrate the dielectric layer 116 . Specifically, the depth of each groove 116 a is approximately between 10 micrometers (μm) and 50 micrometers. In addition, opposite sidewalls of the trench 116a may be parallel to each other as shown in FIG. 1C. Of course, this embodiment is only used for illustration, and the present invention does not limit the depth, shape and form of the groove.

Please continue referring to FIG. 1C , forming a plurality of pads 120 on the dielectric layer 116 . In detail, the pads 120 are electrically connected to the metal layer 114 , and the trench 116 a is located between any two adjacent pads 120 . Next, a solder resist layer 150 as shown in FIG. 1C is formed on the dielectric layer 116 , and the solder resist layer 150 exposes the solder pad 120 and the groove 116 a. In this embodiment, the solder resist layer 150 may have a plurality of openings, which respectively expose the solder pads 120 and the groove 116 a between any two adjacent solder pads 120 .

Next, referring to FIG. 1D , a plurality of solder bumps 130 are formed on the pads 120 . In this embodiment, the method of forming the solder bump 130 on the pad 120 may include ball planting or printing, and of course, the present invention is not limited thereto. Next, an electronic component 140 is disposed on the pad 120 as shown in FIG. 1D . In this embodiment, the electronic component 140 may include passive or active components such as resistors, capacitors, inductors, diodes, transistors, or integrated circuits (ICs).

Next, referring to FIG. 1E , a reflow process is performed to melt the solder mass 130 to form a plurality of solder layers 132, wherein the above-mentioned solder layers 132 cover the solder pads 120 respectively. At this time, the solder layers 132 on any two adjacent pads 120 are adapted to respectively extend to opposite side walls of the corresponding trenches 116a as shown in FIG. 1E , and are separated from each other by the corresponding trenches 116a. That is to say, in this embodiment, the groove 116a located between any two adjacent welding pads 120 is used to extend the flow path of the solder layer 132 flowing downward from the welding pad 120 , so that any two adjacent welding pads 120 The solder layers 132 of the solder pads 132 can be separated from each other by corresponding grooves 116a, thereby greatly reducing the situation that the solder layers 132 on any two adjacent solder pads 120 are prone to bridging after reflow due to the close spacing. Generally speaking, the usage amount of the solder layer 132 is calculated according to engineering. Even if overflow occurs, the amount of overflow will not be so large that it will exceed the extended flow path. Thus, the semiconductor structure 100 of this embodiment Fabrication is substantially completed, and preventive designs are formed on the substrate 110 .

The semiconductor structure 100 manufactured according to the above manufacturing method may include a substrate 110 , a plurality of pads 120 , a plurality of solder layers 132 and electronic components 140 as shown in FIG. 1E . In this embodiment, the substrate 110 can be a printed circuit board, which can include a core layer 112, a metal layer 114, and a dielectric layer 116, wherein the metal layer 114 is disposed on the dielectric layer 116, and the dielectric layer 116 is disposed on the core layer 112, and the dielectric layer 116 includes at least one trench 116a. The pad 120 is disposed on the dielectric layer 116 and electrically connected to the metal layer 114 . The trench 116 a is disposed between any two adjacent pads 120 , and, in this embodiment, opposite side walls of the trench 116 a may be parallel to each other, for example. The solder layers 132 are respectively disposed on the pads 120 . The electronic component 140 is disposed on the pad 120 through the solder layer 132 and electrically connected thereto. In detail, the solder layers 132 on any two adjacent pads 120 are adapted to respectively extend to opposite sidewalls of the corresponding trenches 116a, and are separated from each other by the corresponding trenches 116a.

So configured, the semiconductor structure 100 of this embodiment uses the groove 116a between any two adjacent pads 120 to extend the flow path of the solder layer 132 in the molten state, so that any two adjacent pads 120 The solder layers 132 can be separated from each other corresponding to the trenches 116 a, thus greatly reducing the bridging of the solder layers 132 on any two adjacent pads 120 after reflow, thereby improving the production yield of the semiconductor structure 100 .

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. It must be noted here that the semiconductor structure 100a of this embodiment is similar to the semiconductor structure 100 of FIG. components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and this embodiment will not be repeated. The differences between the semiconductor structure 100 a of this embodiment and the semiconductor structure 100 of FIG. 1E will be described below.

Please refer to FIG. 2 , in this embodiment, opposite side walls of the trench 116 a are also parallel to each other, but the surfaces of the two side walls are rough. This configuration can further increase the contact area between the solder layer 132 and the opposite side walls of the groove 116a, thus further prolonging the flow path and time for the solder layer 132 to flow along the two side walls in the molten state, so that the solder layer 132 can be melted by melting. In this state, there is enough time to form a solid state, which can further reduce the probability of bridging of the solder layer 132 on any two adjacent pads 120 after reflow, and further improve the production yield of the semiconductor structure 100a.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. It must be noted here that the semiconductor structure 100b of this embodiment is similar to the semiconductor structure 100 of FIG. components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and this embodiment will not be repeated. The differences between the semiconductor structure 100b of this embodiment and the semiconductor structure 100 of FIG. 1E will be described below.

Referring to FIG. 3 , in this embodiment, the distance between the opposite sidewalls of the trench 116 a gradually decreases toward the core layer 112 as shown in FIG. 3 instead of being parallel to each other as shown in FIG. 1E . Such configuration, compared with the semiconductor structure 100 shown in FIG. 1E , the semiconductor structure 100b of this embodiment increases the length of the opposite side walls of the trench 116a and the rough surface 116b on the wall surface, so that the solder layer 132 can be further extended. In the molten state, the flow path flowing down the two side walls and the rough surface 116b on the wall delay the flow speed of the solder layer 132, which can further reduce the solder layer 132 on any two adjacent solder pads 120 after reflow. The probability of bridging is improved to improve the production yield of the semiconductor structure 100b.

FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. It must be noted here that the semiconductor structure 100c of this embodiment is similar to the semiconductor structure 100 shown in FIG. components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and this embodiment will not be repeated. The differences between the semiconductor structure 100c of this embodiment and the semiconductor structure 100 of FIG. 1E will be described below.

Referring to FIG. 4 , in this embodiment, the number of trenches 116 a in the dielectric layer 116 is multiple, wherein two of the trenches 116 a are disposed between any two adjacent pads 120 . That is to say, two grooves 116 a are disposed between any two adjacent pads 120 , and the two grooves 116 a between any two adjacent pads 120 are not connected to each other. In this way, the solder layer 132 on any two adjacent solder pads 120 can respectively flow into the two corresponding grooves 116a during the reflow process, and be separated from each other by the barrier of the side walls of the two grooves 116a, Therefore, the possibility of bridging of the solder layer 132 on any two adjacent pads 120 after reflow can be avoided, thereby greatly improving the production yield of the semiconductor structure 100c.

FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. It must be noted here that the semiconductor structure 100d of this embodiment is similar to the semiconductor structure 100 of FIG. components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and this embodiment will not be repeated. The differences between the semiconductor structure 100d of this embodiment and the semiconductor structure 100 of FIG. 1E will be described below.

Referring to FIG. 5, in this embodiment, the trench 116a of the semiconductor structure 100d does not expose the core layer 112, that is, the trench 116a does not penetrate the dielectric layer 116, and the bottom surface of the trench 116a is shown in FIG. Rough surface 116b is shown. With such configuration, since the trench 116a does not expose the core layer 112, the core layer 112 under the trench 116a can still retain the original circuit design, that is, the upper surface of the core layer 112 can have the core circuit layer 112a. Moreover, the bottom surface of the groove 116a is a rough surface, which can increase the contact area between the solder layer 132 and the groove 116a, thereby prolonging the flow path of the solder layer 132 in the reflow process to compensate for the fact that the core layer 112 is not exposed by the groove 116a. As a result, the flow path of the solder layer 132 is shortened. Moreover, in an embodiment of the present invention, the opposite side walls and the bottom surface of the groove 116a can be rough surfaces 116b, so as to further increase the contact area between the solder layer 132 and the groove 116a, and extend the solder layer 132 during reflow. flow path in the process. Therefore, the semiconductor structure 100d of this embodiment can greatly reduce the probability of bridging of the solder layer 132 on any two adjacent pads 120 after reflow, and improve the production yield of the semiconductor structure 100d.

In summary, the semiconductor structure of the present invention is provided with at least one groove between any two adjacent pads on its substrate, so as to use the groove between any two adjacent pads to extend the length of the pad. The flow path of the solder layer in the molten state, so that the solder layers on any two adjacent pads can be separated from each other by corresponding grooves, thus greatly reducing the gap between any two adjacent pads due to their close spacing. The solder layer is bridged after reflow. Therefore, the semiconductor structure of the present invention can have a higher production yield due to the preventive structural design.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (10)

1. a semiconductor structure, it is characterised in that including:

Substrate, including core layer, metal level and dielectric layer, described metal level is arranged at described dielectric layer On, described dielectric layer is arranged in described core layer and includes at least one groove；

Multiple weld pads, are arranged on described dielectric layer and electrically connect with described metal level, and described groove is arranged Between wantonly two adjacent weld pads；

Multiple solder layers, are respectively arranged on those weld pads；And

Electronic component, is arranged on those weld pads by those solder layers.

Semiconductor structure the most according to claim 1, it is characterised in that relative the two of described groove Sidewall is parallel to each other.

Semiconductor structure the most according to claim 2, it is characterised in that relative the two of described groove The surface of sidewall is matsurface.

Semiconductor structure the most according to claim 1, it is characterised in that relative the two of described groove Distance between sidewall is gradually reduced toward the direction near described core layer.

Semiconductor structure the most according to claim 1, it is characterised in that described at least one groove Quantity is multiple, and wherein the two of those grooves are arranged between wantonly two adjacent weld pads.

Semiconductor structure the most according to claim 1, it is characterised in that the degree of depth of each described groove Between 10 microns to 50 microns.

Semiconductor structure the most according to claim 1, it is characterised in that each described groove exposes institute State core layer.

Semiconductor structure the most according to claim 1, it is characterised in that each described groove does not exposes Described core layer.

Semiconductor structure the most according to claim 8, it is characterised in that the bottom surface of each described groove For matsurface.

Semiconductor structure the most according to claim 1, it is characterised in that also include welding resisting layer, It is arranged on described dielectric layer and exposes those weld pads.