CN106298521B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
- Publication number
- CN106298521B CN106298521B CN201510258284.9A CN201510258284A CN106298521B CN 106298521 B CN106298521 B CN 106298521B CN 201510258284 A CN201510258284 A CN 201510258284A CN 106298521 B CN106298521 B CN 106298521B
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor material
- material layer
- groove
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic device.The method includes the steps S1: providing semiconductor substrate, is formed with undoped semiconductor material layer and stressor layers on the semiconductor substrate；Step S2: source and drain injection is executed, in the stressor layers to form source-drain area；Step S3: patterning the stressor layers, to form opening, exposes the semiconductor material layer；Step S4: clearance wall is formed on the side wall of the opening；Step S5: with the opening for exposure mask, etching the semiconductor material layer, to form the groove that size is greater than the opening in the semiconductor material layer；Step S6: grid material is selected to fill the groove and the opening, to form gate structure.The method of the invention further reduced as OXIDATION ENHANCED DIFFUSION, and thus caused by transfer electrical benefits (TED) and short-channel effect, improve the mobility, junction capacity and drain junction of transistor channel, improve the yield and performance of device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular it relates to a kind of semiconductor devices and preparation method thereof,
Electronic device.
Background technique
With the increasingly increase of the semiconductor storage demand for high capacity, these semiconductor storages are integrated
More concerns of the density by people use many to increase the integration density of semiconductor storage in the prior art
Different methods, such as more are formed on single wafer by reducing memory cell size and/or changing structural unit
Storage unit.
In thermal oxidation process Central Plains, there are certain foreign atoms in silicon to show higher diffusivity, referred to as oxidation enhancing
It spreads (Oxidation-Enhanced Diffusion, OED), with the continuous diminution of grid length, the shadow of the OED effect
Ringing becomes the principal element that boron or phosphorus extend in NMOS and PMOS.The reallocation of transfer electrical benefits (TED) not only determines
The short-channel effect of transistor equally also affects the mobility, junction capacity and drain junction of transistor channel.
In the prior art in order to improve the performance of semiconductor devices, it will usually use various stress techniques, such as in PMOS
Middle formation SiGe stressor layers, in the case where no thermal oxide, Si and Si0.8Ge0.2In identical ion implanting, stress
Influence very little of the layer to ion doping, the two have the device of stressor layers almost without difference, but in rapid thermal annealing process
Since the diffusion of its ion of the effect of stress is well controlled in part, and a large amount of expand then is generated in the Si of not stressor layers
It dissipates.
Therefore forming stronger channel stress becomes a kind of effective technological means for solving current OXIDATION ENHANCED DIFFUSION how
Forming stronger channel stress becomes key.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
It is described existing in theprior art in order to solve the problems, such as, a kind of preparation method of semiconductor devices is provided, is wrapped
It includes:
Step S1: providing semiconductor substrate, be formed on the semiconductor substrate undoped semiconductor material layer and
Stressor layers；
Step S2: source and drain injection is executed, in the stressor layers to form source-drain area；
Step S3: patterning the stressor layers, to form opening, exposes the semiconductor material layer；
Step S4: clearance wall is formed on the side wall of the opening；
Step S5: with the opening for exposure mask, the semiconductor material layer is etched, with the shape in the semiconductor material layer
It is greater than the groove of the opening at size；
Step S6: grid material is selected to fill the groove and the opening, to form gate structure.
Optionally, in the step S5, the groove is oval-shaped groove.
Optionally, it is still further comprised between the step S5 and the step S6 and selects H2Or Ar to the groove into
The step of row processing, so that the groove profile is smooth.
Optionally, in the step S1, the semiconductor material layer selects group Ⅲ-Ⅴ compound semiconductor material or silicon
Material.
Optionally, in the step S1, threshold voltage adjustments layer is also formed with below the semiconductor material layer.
Optionally, the method that the semiconductor material layer and the threshold voltage adjustments layer pass through epitaxial growth is formed.
Optionally, in the step S1, oxide skin(coating) is also formed with below the threshold voltage adjustments layer.
Optionally, in the step S1, it is formed with low-doped LDD in the stressor layers or the light of anti-source and drain injection is mixed
It is miscellaneous.
Optionally, the step S2 includes:
Step S21: pad oxide skin(coating) is formed in the stressor layers；
Step S22: executing source and drain injection, to form source-drain area at the top of the stressor layers.
Optionally, in the step S5, semiconductor material layer described in wet etching is selected, the wet etching selects four
Ammonium hydroxide.
Optionally, it in the step S6, deposition of gate material lamination and is planarized in the groove and the opening,
To form the gate structure.
Optionally, the method may further include formation autoregistration silication on the gate structure and the source-drain area
The step of object.
The invention further relates to a kind of semiconductor devices being prepared based on above-mentioned method.
The invention further relates to a kind of electronic devices, including above-mentioned semiconductor devices.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices,
Semiconductor material layer undoped on a semiconductor substrate and stressor layers are formed on the semiconductor material layer in the method,
And the doping of anti-source and drain injection is formed in the stressor layers, to prevent the Doped ions in source and drain injection process from entering described half
In conductor material layer, the stressor layers and semiconductor material layer are then patterned, in the stressor layers and semiconductor material layer
The up-narrow and down-wide gate structure of middle formation further increases the stress of the channel by the setting of the stressor layers, and
The channel be it is undoped, further reduced for OXIDATION ENHANCED DIFFUSION (Oxidation-Enhanced Diffusion,
), and thus OED transfer electrical benefits (TED) and short-channel effect caused by improve mobility, the knot of transistor channel
Capacitor and drain junction improve the yield and performance of device.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 a-1j is the preparation process schematic diagram of heretofore described semiconductor devices；
Fig. 2 is the process flow chart of semiconductor devices preparation in the embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Embodiment 1
The present invention in order to solve the problems in the existing technology, step of preparation process to the semiconductor devices and
Parameter in the step is improved, and to eliminate the above problem, 1a-1j is partly led to of the present invention with reference to the accompanying drawing
The preparation method of body device is further described.
Firstly, executing step 101, semiconductor substrate 101 is provided, sequentially forms semiconductor material on the semiconductor substrate
The bed of material 102, the stressor layers 103 being lightly doped.
Specifically, as illustrated by figures 1 a-1 c, wherein the semiconductor substrate 101 can be in the following material being previously mentioned
At least one: silicon (SSOI) is laminated on insulator, SiGe (S- is laminated on insulator for silicon, silicon-on-insulator (SOI)
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Optionally, wherein the semiconductor substrate is N-type semiconductor substrate.
Wherein, the semiconductor material layer 102 is N-type drift region, and the semiconductor material layer passes through the method shape of extension
At, such as selective epitaxial method, the selective epitaxial be selected from LPCVD, VLPCVD, PECVD, UHVCVD, RTCVD, APCVD and
One of MBE.
Wherein, the semiconductor material layer 102 selects group Ⅲ-Ⅴ compound semiconductor material or silicon materials.Further, institute
A kind of semiconductor material that group Ⅲ-Ⅴ compound semiconductor material is made of III A race of the periodic table of elements and V A race element is stated, such as
GaAs, GaP etc., but it is not limited to the example.
Further, the semiconductor material layer 102 is undoped semiconductor material layer, and there is no the doping of any ion.
Optionally, the undoped channel region is between gate oxide and the semiconductor substrate.
Optionally, threshold voltage adjustments layer is also formed with below the undoped channel region (not show in figure
Out), to be used for adjusting threshold voltage.
Optionally, the method that the threshold voltage adjustments layer passes through epitaxial growth is formed.
Oxide skin(coating) is also formed with below the threshold voltage adjustments layer, (not shown) can be by normal
Rule deposition method is formed.
Stressor layers 103 are also formed on the semiconductor material layer, wherein the stressor layers are SiC or SiGe etc., but
It is to be not limited to the material.
Wherein, described in the stressor layers 103 is lightly doped as being lightly doped for LDD or the injection of anti-source and drain is lightly doped, with
Prevent ion doping from entering the semiconductor material layer in subsequent step.
Step 102 is executed, source and drain injection is executed in the stressor layers 103, to form source-drain area and undoped partly lead
Body material layer.
Specifically, as shown in Figure 1 d, pad oxide skin(coating) is formed in the stressor layers 103 in this step；Then it executes
Source and drain injection, to form source-drain area 104 at the top of the stressor layers 103.
In this step due in the stressor layers have be lightly doped LDD or anti-source and drain injection be lightly doped, can prevent
Ion doping enters the semiconductor material layer.
Further, the source and drain injection step can select method commonly used in the art, it is not limited to a certain.
Step 103 is executed, the stressor layers 103 are patterned, to form opening, exposes the semiconductor material layer 102.
Specifically, as shown in fig. le, it forms mask layer on the semiconductor substrate in this step, and patterns,
Then using the patterned mask layer as stressor layers 103 described in mask etch, to form opening, to define gate structure.
It can select dry etching or wet etching, in one embodiment, can choose N in this step2In
As etching atmosphere, other a small amount of gas such as CF can also be added simultaneously4、CO2、O2, the etching pressure can be 2-
200mTorr is chosen as 2-30mTorr, power 500-900W, and the etching period is 5-80s in the present invention, is chosen as
10-60s, while biggish gas flow is selected in the present invention, in N of the present invention2Flow be 30-300sccm, it is optional
For 50-100sccm.
Step 104 is executed, forms clearance wall 105 on the side wall of the opening.
Specifically, as shown in Figure 1 f, silicon nitride, silicon carbide, nitrogen oxidation can be used in the clearance wall 105 in this step
The material of silicon or combinations thereof.The first silicon oxide layer, the first silicon nitride layer and can be deposited in stressor layers and the opening
Silicon dioxide layer, then forms clearance wall using engraving method, and the clearance wall can have the thickness of 10-30NM.
Step 105 is executed, with the opening for exposure mask, the semiconductor material layer is etched, in the semiconductor material
Groove is formed in layer.
Specifically, as shown in Figure 1 g, semiconductor material layer described in wet etching, the wet etching are selected in this step
Select tetramethylammonium hydroxide.
Wherein, the groove be critical size be greater than the opening oval-shaped groove, due to the groove size compared with
Greatly, the short-channel effect of gate structure can be further decreased after the gate formation.
Further, after forming the groove, the method, which still further comprises, selects H2Or Ar to the groove into
Row processing, so that the groove profile is smooth, optionally, can also expand the critical size of the groove, such as Fig. 1 h institute simultaneously
Show.
Step 106 is executed, selects grid material to fill the groove and the opening, to form gate structure 106.
Specifically, as shown in figure 1i, wherein remove the oxygen pad layer above the stressor layers first in this step.
Then it the gate stacks such as deposited interfacial layer, diffusion barrier layer, work-function layer and conductive layer and planarizes, to be formed
Gate structure 106.
Execute step 107, the stars self-alignment silicide layer 107 on the gate structure and the source-drain area.
Specifically, as shown in fig. ij, the forming method of the self-aligned silicide in this step are as follows: Yu Suoshu grid knot
Then structure and source-drain area surface sputtered metal layer, such as nickel metal layer carry out rapid temperature annealing (RTA) technique, make
At metal silicide layer, completion is voluntarily directed at metal silication for the part reaction that metal layer is contacted with grid and regions and source/drain
Object technique (salicide).
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
It afterwards, can also include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices,
Semiconductor material layer undoped on a semiconductor substrate and stressor layers are formed on the semiconductor material layer in the method,
And the doping of anti-source and drain injection is formed in the stressor layers, to prevent the Doped ions in source and drain injection process from entering described half
In conductor material layer, the stressor layers and semiconductor material layer are then patterned, in the stressor layers and semiconductor material layer
The up-narrow and down-wide gate structure of middle formation further increases the stress of the channel by the setting of the stressor layers, and
The channel be it is undoped, further reduced for OXIDATION ENHANCED DIFFUSION (Oxidation-Enhanced Diffusion,
), and thus OED transfer electrical benefits (TED) and short-channel effect caused by improve mobility, the knot of transistor channel
Capacitor and drain junction improve the yield and performance of device.
Wherein, Fig. 2 is the process flow chart of semiconductor devices preparation in the embodiment of the present invention, specifically, including following step
It is rapid:
Step S1: providing semiconductor substrate, be formed on the semiconductor substrate undoped semiconductor material layer and
Stressor layers；
Step S2: source and drain injection is executed, in the stressor layers to form source-drain area；
Step S3: patterning the stressor layers, to form opening, exposes the semiconductor material layer；
Step S4: clearance wall is formed on the side wall of the opening；
Step S5: with the opening for exposure mask, the semiconductor material layer is etched, with the shape in the semiconductor material layer
It is greater than the groove of the opening at size；
Step S6: grid material is selected to fill the groove and the opening, to form gate structure.
Embodiment 2
The present invention also provides a kind of semiconductor devices, the semiconductor devices selects method preparation described in embodiment 1.
Channel described in the semiconductor devices that the method is prepared through the invention is undoped channel and top is formed with and answers
Power layer further increases the stress of channel, reduces as OXIDATION ENHANCED DIFFUSION (Oxidation-Enhanced
Diffusion, OED), and thus caused transfer electrical benefits (TED) and short-channel effect, improve transistor channel
Mobility, junction capacity and drain junction improve the yield and performance of device.
Embodiment 3
The present invention also provides a kind of electronic devices, including semiconductor devices as described in example 2.Wherein, semiconductor device
Part is semiconductor devices as described in example 2, or the semiconductor devices obtained according to preparation method described in embodiment 1.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used
Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510258284.9A CN106298521B (en) | 2015-05-20 | 2015-05-20 | A kind of semiconductor devices and preparation method thereof, electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510258284.9A CN106298521B (en) | 2015-05-20 | 2015-05-20 | A kind of semiconductor devices and preparation method thereof, electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298521A CN106298521A (en) | 2017-01-04 |
| CN106298521B true CN106298521B (en) | 2019-05-17 |
Family
ID=57632832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510258284.9A Active CN106298521B (en) | 2015-05-20 | 2015-05-20 | A kind of semiconductor devices and preparation method thereof, electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298521B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720250B1 (en) * | 2005-10-26 | 2007-05-22 | 주식회사 하이닉스반도체 | Recess gate formation method of semiconductor device |
| CN101663761A (en) * | 2006-12-15 | 2010-03-03 | 先进微装置公司 | Stress enhanced transistor and methods for its fabrication |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100853485B1 (en) * | 2007-03-19 | 2008-08-21 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device having recess gate |
-
2015
- 2015-05-20 CN CN201510258284.9A patent/CN106298521B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720250B1 (en) * | 2005-10-26 | 2007-05-22 | 주식회사 하이닉스반도체 | Recess gate formation method of semiconductor device |
| CN101663761A (en) * | 2006-12-15 | 2010-03-03 | 先进微装置公司 | Stress enhanced transistor and methods for its fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298521A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10325817B2 (en) | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors | |
| US8652891B1 (en) | Semiconductor device and method of manufacturing the same | |
| JP4301506B2 (en) | Low leakage heterojunction vertical transistor and its high performance device | |
| KR101667892B1 (en) | Conversion of thin transistor elements from silicon to silicon germanium | |
| JP4299736B2 (en) | Super-scalable high-speed heterojunction vertical N-channel MISFET and method | |
| US20180240715A1 (en) | Methods of forming vertical transistor devices with different effective gate lengths and the resulting devices | |
| US8853862B2 (en) | Contact structures for semiconductor transistors | |
| US9548387B2 (en) | Semiconductor device and method of manufacturing the same | |
| KR101482200B1 (en) | Recessed drain and source areas in combination with advanced silicide formation in transistor | |
| US8476131B2 (en) | Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same | |
| KR20090019693A (en) | Strained semiconductor device and manufacturing method thereof | |
| CN105762068A (en) | Semiconductor element and manufacturing method thereof | |
| CN106033725B (en) | Semiconductor element and manufacturing process thereof | |
| US7923346B2 (en) | Field effect transistor structure with an insulating layer at the junction | |
| US20110104864A1 (en) | Method of fabricating semiconductor device | |
| US20170117189A1 (en) | Method of forming field effect transistors (fets) with abrupt junctions and integrated circuit chips with the fets | |
| US9281398B2 (en) | Semiconductor structure and method for manufacturing the same | |
| KR102392695B1 (en) | A semiconductor device and a method of fabricating the same | |
| CN109103108A (en) | Method for forming semiconductor device | |
| CN106601678B (en) | A kind of semiconductor device and its preparation method, electronic device | |
| CN202633241U (en) | Transistor with a metal gate electrode | |
| WO2015027843A1 (en) | Maskless dual silicide contact formation | |
| CN106601675B (en) | A kind of semiconductor device and its preparation method, electronic device | |
| US7135365B2 (en) | Method of manufacturing MOS transistors | |
| CN106549016B (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |