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US20110104864A1 - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device Download PDF

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Publication number
US20110104864A1
US20110104864A1 US12/985,309 US98530911A US2011104864A1 US 20110104864 A1 US20110104864 A1 US 20110104864A1 US 98530911 A US98530911 A US 98530911A US 2011104864 A1 US2011104864 A1 US 2011104864A1
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source
region
drain
substrate
fabricating
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US12/985,309
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Li-Shian Jeng
Cheng-Tung Huang
Shyh-Fann Ting
Wen-Han Hung
Kun-Hsien Lee
Meng-Yi Wu
Tzyy-Ming Cheng
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHENG, TZYY-MING, HUANG, CHENG-TUNG, HUNG, WEN-HAN, JENG, LI-SHIAN, LEE, KUN-HSIEN, TING, SHYH-FANN, WU, MENG-YI
Publication of US20110104864A1 publication Critical patent/US20110104864A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Definitions

  • the present invention relates to a method of fabricating an integrated circuit. More particularly, the present invention relates to a method of fabricating a complementary metal oxide semiconductor (CMOS) device.
  • CMOS complementary metal oxide semiconductor
  • a method using a mechanical stress in channel to improve the moving speed of electrons and holes in the channel is an effective way to eliminate the limitation caused by the scaling down of a device.
  • a conventional technique using a material such as SiGe epitaxy as a main component of a source/drain region of a transistor has been proposed.
  • a portion of the substrate in which a source/drain region is predetermined to be formed is removed, and SiGe is refilled by using a selective area epitaxy growth technique.
  • SiGe is used as the main component of the source/drain region.
  • Ge has smaller electron effective mass and hole effective mass, so that the source/drain region formed by SiGe can increase the mobility of electrons and holes, thereby enhancing the performance of the device.
  • a layer of stress-transfer-scheme (STS) is covered on the substrate for providing a stress to a gate conductive layer, and then the STS is removed, such that the stress memory effect generated by the STS to the gate conductive layer is used to enhance the ion performance of the device.
  • RTA rapid thermal annealing
  • the STS when applied in a conventional transistor device is deposited after the ion implantation process for forming a source/drain contact region is performed.
  • the energy for the ion implantation process in the source/drain contact region is high enough to amorphize the polysilicon of the gate conductive layer into amorphous silicon, and the amorphous silicon has an excellent stress memory effect generated by the STS, so after the STS is removed, the stress memory of the amorphous silicon can improve the ion performance of the device.
  • the SiGe epitaxy process is performed at a temperature up to 700° C.-900° C. for 3-4 hours, thus generating an over-high thermal budget, such that the gate conductive layer is recrystallized into polysilicon.
  • the ion implantation process in the source/drain contact region of an n-type channel MOS (NMOS) is performed before the SiGe epitaxy process, so before the STS is formed, only an ion implantation process of low energy in a source/drain extension region is performed.
  • NMOS n-type channel MOS
  • the energy for the ion implantation process in the source/drain extension region is insufficient to completely amorphize the gate conductive layer into amorphous silicon, so the stress memory generated by the STS to the gate conductive layer is not sufficient to effectively enhance the ion performance of the device.
  • the present invention is directed to provide a method of fabricating a semiconductor device to prevent the influence caused by an over-high thermal budget of a SiGe epitaxy process, such that the stress memory effect generated by the STS to the gate conductive layer can be used to enhance the ion performance of a device.
  • the present invention is further directed to provide a method of fabricating a CMOS device so as to prevent the influence caused by an over-high thermal budget of the SiGe epitaxy process, such that the stress memory effect generated by the STS to the gate conductive layer can be used to enhance the ion performance of a device.
  • the present invention provides a method of fabricating a CMOS device.
  • a substrate comprising a first region and a second region is provided.
  • a first conductive type MOS field effect transistor (FET) is formed on the substrate in the first region, and the first conductive type MOSFET comprises a first gate structure and a first source/drain region using a semiconductor compound as a major material.
  • a second conductive type MOSFET is formed on the substrate in the second region, and the second conductive type MOSFET comprises a second gate structure and a second source/drain region.
  • a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second gate structure in the second region.
  • PAI pre-amorphous implantation
  • an STS is formed on the substrate in the second region after the PAI process.
  • an RTA process is performed. After that, the STS is removed.
  • the method of forming the first and second conductive type MOSFETs first forms a first gate structure and a second gate structure respectively in the first region and the second region of the substrate at the same time, wherein the first and second gate structures comprise a gate dielectric layer, a gate conductive layer, and a first spacer respectively. Then, a second conductive type source/drain contact region is formed in the substrate around the sidewalls of the first spacer of the second region and the first region respectively.
  • the substrate of the second conductive type source/drain contact region of the first region is removed, and the semiconductor compound having a first conductive type dopant is formed therein to form the first conductive type source/drain contact region.
  • the first spacers of the first region and the second region are removed.
  • a first conductive type source/drain extension region is formed in the substrate around the gate conductive layer in the first region, and a second conductive type source/drain extension region is formed in the substrate around the gate conductive layer in the second region.
  • a second spacer is formed at the sidewalls each of the gate conductive layers in the first region and in the second region.
  • the first conductive type is p-type
  • the second conductive type is n-type
  • the semiconductor compound layer comprises SiGe
  • the first conductive type is n-type
  • the second conductive type is p-type
  • the semiconductor compound layer comprises SiC
  • the atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof.
  • the second source/drain region comprises a second conductive type source/drain extension region and a second conductive type source/drain contact region, and the energy for performing the PAI process is less than the energy for performing the ion implantation process for forming the second source/drain contact region.
  • the second source/drain region comprises a second conductive type source/drain extension region and a second conductive type source/drain contact region, and the energy for performing the PAI process is larger than the energy for performing the ion implantation process for forming the second source/drain extension region.
  • the second source/drain region comprises a second conductive type source/drain extension region and a second conductive type source/drain contact region
  • the energy for performing the PAI process is between the energy for performing the ion implantation process for forming the second source/drain extension region and the energy for performing the ion implantation process for forming the second source/drain contact region.
  • the atom used in the PAI process is Ge, and the energy for the PAI process is about 5-20 KeV.
  • the material of the STS comprises Si x O y or Si x N y .
  • the present invention provides a method of fabricating a semiconductor device. First, an MOSFET comprising a gate structure and a source/drain region is formed in the substrate. Next, a PAI process is performed to amorphize a gate conductive layer of the gate structure. Afterwards, an STS is formed on the substrate. Then, an RTA process is performed. After that, the STS is removed.
  • the atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof.
  • the source/drain region comprises a source/drain extension region and a source/drain contact region
  • the energy for performing the PAI process is less than the energy for performing the ion implantation process for forming the source/drain contact region.
  • the source/drain region comprises a source/drain extension region and a source/drain contact region
  • the energy for performing the PAI process is larger than the energy for performing the ion implantation process for forming the source/drain extension region.
  • the energy for performing the PAI process is between the energy for performing the ion implantation process for forming the source/drain extension region and the energy for performing the ion implantation process for forming the source/drain contact region.
  • the atom used in the PAI process is Ge, and the energy for the PAI process is about 5-20 KeV.
  • the material of the STS comprises Si x O y or Si x N y .
  • the method of forming an MOSFET first forms a gate structure comprising a gate dielectric layer, a gate conductive layer, and a first spacer on the substrate. Then, a source/drain contact region is formed in the substrate. Afterwards, the first spacer is removed, and a source/drain extension region is formed in the substrate around the gate conductive layer. After that, a second spacer is formed at the sidewalls of the gate conductive layer.
  • the PAI process of the present invention can prevent the influence caused by an over-high thermal budget of the SiGe epitaxy process, such that the stress memory effect generated by the STS to the gate conductive layer is used to enhance the ion performance of the device.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2A-2F are schematic sectional views of the flow of a method of fabricating a CMOS device according to an embodiment of the present invention.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • an MOS transistor is first formed on a substrate (Step 10 ).
  • a PAI process is performed (Step 12 ) to amorphize a gate conductive layer into amorphous silicon, such that the stress memory effect generated by a subsequently deposited STS can be utilized to enhance an ion performance of device.
  • the atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof.
  • the energy for performing the PAI process is between the energy for performing an ion implantation process for forming a source/drain extension region and the energy for performing an ion implantation process for forming a source/drain contact region.
  • a layer of STS is formed on the substrate (Step 14 ), so as to transfer the stress to the gate conductive layer.
  • an RTA process is performed (Step 16 ) to activate the dopants in the source/drain region.
  • the STS is removed (Step 18 ).
  • the present invention performs the PAI process before the RTA process for activating the dopants in the source/drain region, so as to amorphize the gate conductive layer into amorphous silicon with a preferred stress memory characteristic. Therefore, after removing the STS, the stress generated by the STS to the gate conductive layer can still be memorized in the gate conductive layer for enhancing the ion performance.
  • CMOS device The manufacturing flow of a CMOS device is illustrated below.
  • FIGS. 2A-2F are schematic sectional views of the flow of a method of fabricating a CMOS device according to an embodiment of the present invention.
  • a substrate 100 for example, a monocrystalline silicon substrate.
  • An isolation structure 102 is formed in the substrate 100 to define active regions 104 and 105 .
  • the material of the isolation structure 102 is, for example, an insulating material such as silicon oxide.
  • the method of forming the isolation structure 102 involves, for example, forming a trench in the substrate 100 , depositing a layer of insulating material on the substrate 100 , and then removing the excessive insulating material by performing a chemical-mechanical polishing process.
  • a gate structure 110 is formed on the substrate 100 in the active regions 104 , 105 respectively.
  • the gate structure 110 is composed of, for example, a gate dielectric layer 106 , a gate conductive layer 108 , a cap layer 109 , and a spacer 112 .
  • the method of forming the gate structure 110 involves, for example, first forming a dielectric material layer (not shown) on the substrate 100 .
  • the material of the dielectric material layer is, for example, silicon oxide, and the forming method thereof is, for example, thermal oxidation.
  • a conductive material layer (not shown) is formed on the dielectric material layer to cover the entire substrate 100 .
  • the material of the conductive material layer is, for example, polysilicon or doped polysilicon, and the forming method is, for example, chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • a cap material layer (not shown) is formed on the conductive material layer, wherein the material of the cap material layer is, for example, Si x O y or Si x N y and the forming method is, for example, CVD.
  • a lithographic process and an etching process are performed to pattern the cap material layer, conductive material layer, and dielectric material layer, so as to form the cap layer 109 , conductive layer 108 , and gate dielectric layer 106 .
  • the spacer 112 is formed at the sidewalls of the cap layer 109 and the gate conductive layer 108 , and the material of the spacer 112 is, for example, Si x O y or Si x N y .
  • an ion implantation process is preformed to form a source/drain contact region 118 in the active regions 105 and 104 .
  • an NMOS transistor is preformed in the active region 105 , and the dopants in the source/drain contact region 118 are n-type.
  • a PMOS transistor is preformed in the active region 105 , and the dopants in the source/drain contact regions 118 are p-type.
  • n-type dopants are, for example, P or As, and the p-type dopants are, for example, B.
  • the energy for the ion implantation process in the source/drain contact region 118 is about 10-30 KeV.
  • a mask layer 113 is covered on the active region 105 .
  • the mask layer 113 can be formed by the following steps. First, a mask material layer (not shown) is covered on the substrate 100 . Next, a patterned photoresist layer (not shown) is formed on the cap material layer. Then, the photoresist layer is used as an etching mask to pattern the cap material layer. And finally, the patterned photoresist layer is removed.
  • the material of the cap material layer 113 is, for example, silicon oxide, and the forming method is, for example, high temperature oxide (HTO) process.
  • the substrate 100 in the active region 104 of the source/drain contact region 118 is removed to form grooves 114 in the substrate 100 at both sides of the spacer 112 in the active region 104 .
  • a semiconductor compound is refilled in the grooves 114 , which functions as a source/drain contact region.
  • the grooves 114 can be formed by anisotropic etching.
  • a selective area epitaxy growth process is performed to epitaxially grow semiconductor compound epitaxy layers in the grooves 114 and form dopants in the semiconductor compound epitaxy layers, so as to form source/drain contact regions 116 .
  • an NMOS transistor is preformed in the active region 105 , and the dopants in the source/drain contact region 118 are n-type.
  • a PMOS transistor is preformed in the active region 104 , and the semiconductor compound epitaxy layer in the source/drain contact region 116 is, for example, a SiGe layer, wherein the dopants in the source/drain contact region 116 are p-type.
  • the method of forming SiGe involves first introducing a gas source containing Si such as SiH 4 , CH 2 Cl 2 , or a combination thereof, a gas source containing Ge such as GeH 4 , HCl, and a dopant gas source such as BH 3 as a reactive gas source into a CVD reaction chamber and then depositing at a temperature of 700-900° C. for 3-4 hours.
  • a gas source containing Si such as SiH 4 , CH 2 Cl 2 , or a combination thereof
  • a gas source containing Ge such as GeH 4 , HCl
  • a dopant gas source such as BH 3
  • a PMOS transistor is preformed in the active region 105 , and the dopants in the source/drain contact region 118 are p-type.
  • An NMOS transistor is preformed in the active region 104 , and the semiconductor compound epitaxy layer in the source/drain contact region 116 is, for example, a SiC layer, wherein the dopants are n-type.
  • the mask layer 113 is removed, and the spacers 112 in the active regions 104 , 105 are also removed. Then, a photoresist mask layer is formed respectively, and an ion implantation process and a pocket ion implantation process are performed to form source/drain extension regions 120 and pocket implantation regions 134 and form source/drain extension regions 122 and pocket implantation regions 136 in the substrate 100 in the active regions 104 and 105 respectively.
  • the source/drain extension region 120 and the source/drain contact region 116 constitute a source/drain region 130 .
  • the source/drain extension region 122 and the source/drain contact region 118 constitute a source/drain region 132 .
  • an NMOS transistor is preformed in the active region 105 , and the dopants in the source/drain extension region 122 are n-type.
  • a PMOS transistor is preformed in the active region 104 , and the dopants in the source/drain extension region 120 are p-type.
  • a PMOS transistor is preformed in the active region 105 , and the dopants in the source/drain extension region 122 are p-type.
  • An NMOS transistor is preformed in the active region 104 , and the dopants in the source/drain extension region 120 are n-type.
  • a spacer 124 is formed at the sidewalls of the cap layer 109 and the gate conductive layer 108 in the active regions 104 , 105 respectively.
  • a PAI process 126 is performed to amorphize the gate conductive layer 108 of each gate structure 110 .
  • the atom used in the PAI process 126 is selected from a group consisting of Ge, As, C, Sb, and a combination thereof.
  • the energy for performing the PAI process 126 is between the energy for performing an ion implantation process for forming the source/drain extension region 122 and the energy for performing an ion implantation process for forming the source/drain contact region 118 .
  • the energy for the ion implantation process in the source/drain extension region 122 is about 2-4 KeV.
  • the energy for the ion implantation process in the source/drain contact region 118 is about 10-30 KeV.
  • the atom used in the PAI process is Ge and the energy required is about 5-20 KeV.
  • an STS 128 is formed on the active region 105 for producing a stress in the gate conductive layer 108 .
  • the STS 128 can be formed by the following steps. First, an STS material layer is formed on the substrate 100 . Then, a patterned photoresist layer is formed on the active region 105 of the substrate 100 . Afterwards, the patterned photoresist layer is used as an etching mask to etch the STS material layer while leaving the STS 128 on the active region 105 . Finally, the patterned photoresist layer is removed.
  • the STS material layer is, for example, a Si x N y layer or a Si x O y layer, and the forming method thereof can be CVD. Thereafter, an RTA process is performed to activate the dopants in the source/drain regions 130 , 132 .
  • the STS 128 is removed.
  • the STS 128 can be removed by isotropic etching, for example, wet etching.
  • hydrofluoric acid or buffered oxide etch (BOE) can be adopted as an etching solution to remove the STS 128 .
  • hot phosphoric acid can be adopted as an etching solution to remove the STS 128 .
  • the present invention performs the PAI process before the RTA process, so as to amorphize the gate conductive layer which is being crystallized under an over-high thermal budget of the epitaxy process into amorphous silicon with preferred stress memory characteristic. Therefore, after removing the STS, the stress generated by the STS to the gate conductive layer can still be memorized in the gate conductive layer for enhancing the ion performance.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This is a continuation application of U.S. patent application Ser. No. 11/681,987, filed on Mar. 5, 2007, and all benefits of such earlier application are hereby claimed for this new continuation application.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a method of fabricating an integrated circuit. More particularly, the present invention relates to a method of fabricating a complementary metal oxide semiconductor (CMOS) device.
  • 2. Description of the Prior Art
  • Along with the progress in the development of electronic devices such as communication electronic devices, the operating speed of transistors is growing faster. However, limited by the moving speed of electrons and holes in a silicon channel, the application range of transistors is also restricted.
  • A method using a mechanical stress in channel to improve the moving speed of electrons and holes in the channel is an effective way to eliminate the limitation caused by the scaling down of a device.
  • A conventional technique using a material such as SiGe epitaxy as a main component of a source/drain region of a transistor has been proposed. First, a portion of the substrate in which a source/drain region is predetermined to be formed is removed, and SiGe is refilled by using a selective area epitaxy growth technique. SiGe is used as the main component of the source/drain region. Compared with the material characteristics of Si, Ge has smaller electron effective mass and hole effective mass, so that the source/drain region formed by SiGe can increase the mobility of electrons and holes, thereby enhancing the performance of the device.
  • According to another method, after an ion implantation process in the source/drain region of the transistor and before a rapid thermal annealing (RTA) process, a layer of stress-transfer-scheme (STS) is covered on the substrate for providing a stress to a gate conductive layer, and then the STS is removed, such that the stress memory effect generated by the STS to the gate conductive layer is used to enhance the ion performance of the device.
  • However, if SiGe is used as the main component of the source/drain region and meanwhile the STS technology is adopted, the ion performance of the device cannot be effectively enhanced.
  • The reason is that the STS when applied in a conventional transistor device is deposited after the ion implantation process for forming a source/drain contact region is performed. The energy for the ion implantation process in the source/drain contact region is high enough to amorphize the polysilicon of the gate conductive layer into amorphous silicon, and the amorphous silicon has an excellent stress memory effect generated by the STS, so after the STS is removed, the stress memory of the amorphous silicon can improve the ion performance of the device.
  • However, when SiGe is used as the main component of the source/drain region, the SiGe epitaxy process is performed at a temperature up to 700° C.-900° C. for 3-4 hours, thus generating an over-high thermal budget, such that the gate conductive layer is recrystallized into polysilicon. The ion implantation process in the source/drain contact region of an n-type channel MOS (NMOS) is performed before the SiGe epitaxy process, so before the STS is formed, only an ion implantation process of low energy in a source/drain extension region is performed. However, the energy for the ion implantation process in the source/drain extension region is insufficient to completely amorphize the gate conductive layer into amorphous silicon, so the stress memory generated by the STS to the gate conductive layer is not sufficient to effectively enhance the ion performance of the device.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to provide a method of fabricating a semiconductor device to prevent the influence caused by an over-high thermal budget of a SiGe epitaxy process, such that the stress memory effect generated by the STS to the gate conductive layer can be used to enhance the ion performance of a device.
  • The present invention is further directed to provide a method of fabricating a CMOS device so as to prevent the influence caused by an over-high thermal budget of the SiGe epitaxy process, such that the stress memory effect generated by the STS to the gate conductive layer can be used to enhance the ion performance of a device.
  • The present invention provides a method of fabricating a CMOS device. First, a substrate comprising a first region and a second region is provided. A first conductive type MOS field effect transistor (FET) is formed on the substrate in the first region, and the first conductive type MOSFET comprises a first gate structure and a first source/drain region using a semiconductor compound as a major material. A second conductive type MOSFET is formed on the substrate in the second region, and the second conductive type MOSFET comprises a second gate structure and a second source/drain region. Then, after the first and second conductive type MOSFETs are formed, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second gate structure in the second region. Thereafter, an STS is formed on the substrate in the second region after the PAI process. Then, an RTA process is performed. After that, the STS is removed.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the method of forming the first and second conductive type MOSFETs first forms a first gate structure and a second gate structure respectively in the first region and the second region of the substrate at the same time, wherein the first and second gate structures comprise a gate dielectric layer, a gate conductive layer, and a first spacer respectively. Then, a second conductive type source/drain contact region is formed in the substrate around the sidewalls of the first spacer of the second region and the first region respectively. Afterwards, the substrate of the second conductive type source/drain contact region of the first region is removed, and the semiconductor compound having a first conductive type dopant is formed therein to form the first conductive type source/drain contact region. Then, the first spacers of the first region and the second region are removed. Afterwards, a first conductive type source/drain extension region is formed in the substrate around the gate conductive layer in the first region, and a second conductive type source/drain extension region is formed in the substrate around the gate conductive layer in the second region. After that, a second spacer is formed at the sidewalls each of the gate conductive layers in the first region and in the second region.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the first conductive type is p-type, the second conductive type is n-type, and the semiconductor compound layer comprises SiGe.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the first conductive type is n-type, the second conductive type is p-type, and the semiconductor compound layer comprises SiC.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the second source/drain region comprises a second conductive type source/drain extension region and a second conductive type source/drain contact region, and the energy for performing the PAI process is less than the energy for performing the ion implantation process for forming the second source/drain contact region.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the second source/drain region comprises a second conductive type source/drain extension region and a second conductive type source/drain contact region, and the energy for performing the PAI process is larger than the energy for performing the ion implantation process for forming the second source/drain extension region.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the second source/drain region comprises a second conductive type source/drain extension region and a second conductive type source/drain contact region, and the energy for performing the PAI process is between the energy for performing the ion implantation process for forming the second source/drain extension region and the energy for performing the ion implantation process for forming the second source/drain contact region.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the atom used in the PAI process is Ge, and the energy for the PAI process is about 5-20 KeV.
  • In the method of fabricating a CMOS device according to an embodiment of the present invention, the material of the STS comprises SixOy or SixNy.
  • The present invention provides a method of fabricating a semiconductor device. First, an MOSFET comprising a gate structure and a source/drain region is formed in the substrate. Next, a PAI process is performed to amorphize a gate conductive layer of the gate structure. Afterwards, an STS is formed on the substrate. Then, an RTA process is performed. After that, the STS is removed.
  • In the method of fabricating a semiconductor device according to an embodiment of the present invention, the atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof.
  • In the method of fabricating a semiconductor device according to an embodiment of the present invention, the source/drain region comprises a source/drain extension region and a source/drain contact region, and the energy for performing the PAI process is less than the energy for performing the ion implantation process for forming the source/drain contact region.
  • In the method of fabricating a semiconductor device according to an embodiment of the present invention, the source/drain region comprises a source/drain extension region and a source/drain contact region, and the energy for performing the PAI process is larger than the energy for performing the ion implantation process for forming the source/drain extension region.
  • In the method of fabricating a semiconductor device according to an embodiment of the present invention, the energy for performing the PAI process is between the energy for performing the ion implantation process for forming the source/drain extension region and the energy for performing the ion implantation process for forming the source/drain contact region.
  • In the method of fabricating a semiconductor device according to an embodiment of the present invention, the atom used in the PAI process is Ge, and the energy for the PAI process is about 5-20 KeV.
  • In the method of fabricating a semiconductor device according to an embodiment of the present invention, the material of the STS comprises SixOy or SixNy.
  • In the method of fabricating a semiconductor device according to an embodiment of the present invention, the method of forming an MOSFET first forms a gate structure comprising a gate dielectric layer, a gate conductive layer, and a first spacer on the substrate. Then, a source/drain contact region is formed in the substrate. Afterwards, the first spacer is removed, and a source/drain extension region is formed in the substrate around the gate conductive layer. After that, a second spacer is formed at the sidewalls of the gate conductive layer.
  • The PAI process of the present invention can prevent the influence caused by an over-high thermal budget of the SiGe epitaxy process, such that the stress memory effect generated by the STS to the gate conductive layer is used to enhance the ion performance of the device.
  • In order to make the aforementioned and other objectives, features, and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2A-2F are schematic sectional views of the flow of a method of fabricating a CMOS device according to an embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • Referring to FIG. 1, according to an embodiment of the present invention, an MOS transistor is first formed on a substrate (Step 10). After the fabrication of the MOS transistor and before an RTA process, a PAI process is performed (Step 12) to amorphize a gate conductive layer into amorphous silicon, such that the stress memory effect generated by a subsequently deposited STS can be utilized to enhance an ion performance of device. The atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof. The energy for performing the PAI process is between the energy for performing an ion implantation process for forming a source/drain extension region and the energy for performing an ion implantation process for forming a source/drain contact region. Then, a layer of STS is formed on the substrate (Step 14), so as to transfer the stress to the gate conductive layer. Afterwards, an RTA process is performed (Step 16) to activate the dopants in the source/drain region. Then, the STS is removed (Step 18).
  • The present invention performs the PAI process before the RTA process for activating the dopants in the source/drain region, so as to amorphize the gate conductive layer into amorphous silicon with a preferred stress memory characteristic. Therefore, after removing the STS, the stress generated by the STS to the gate conductive layer can still be memorized in the gate conductive layer for enhancing the ion performance.
  • The manufacturing flow of a CMOS device is illustrated below.
  • FIGS. 2A-2F are schematic sectional views of the flow of a method of fabricating a CMOS device according to an embodiment of the present invention.
  • First, referring to FIG. 2A, a substrate 100, for example, a monocrystalline silicon substrate, is provided. An isolation structure 102 is formed in the substrate 100 to define active regions 104 and 105. The material of the isolation structure 102 is, for example, an insulating material such as silicon oxide. The method of forming the isolation structure 102 involves, for example, forming a trench in the substrate 100, depositing a layer of insulating material on the substrate 100, and then removing the excessive insulating material by performing a chemical-mechanical polishing process.
  • Then, a gate structure 110 is formed on the substrate 100 in the active regions 104, 105 respectively. The gate structure 110 is composed of, for example, a gate dielectric layer 106, a gate conductive layer 108, a cap layer 109, and a spacer 112. The method of forming the gate structure 110 involves, for example, first forming a dielectric material layer (not shown) on the substrate 100. The material of the dielectric material layer is, for example, silicon oxide, and the forming method thereof is, for example, thermal oxidation. Afterwards, a conductive material layer (not shown) is formed on the dielectric material layer to cover the entire substrate 100. The material of the conductive material layer is, for example, polysilicon or doped polysilicon, and the forming method is, for example, chemical vapor deposition (CVD). Thereafter, a cap material layer (not shown) is formed on the conductive material layer, wherein the material of the cap material layer is, for example, SixOy or SixNy and the forming method is, for example, CVD. Then, a lithographic process and an etching process are performed to pattern the cap material layer, conductive material layer, and dielectric material layer, so as to form the cap layer 109, conductive layer 108, and gate dielectric layer 106. After that, the spacer 112 is formed at the sidewalls of the cap layer 109 and the gate conductive layer 108, and the material of the spacer 112 is, for example, SixOy or SixNy. Then, an ion implantation process is preformed to form a source/drain contact region 118 in the active regions 105 and 104. In an embodiment, an NMOS transistor is preformed in the active region 105, and the dopants in the source/drain contact region 118 are n-type. In another embodiment, a PMOS transistor is preformed in the active region 105, and the dopants in the source/drain contact regions 118 are p-type. The n-type dopants are, for example, P or As, and the p-type dopants are, for example, B. In an embodiment, the energy for the ion implantation process in the source/drain contact region 118 is about 10-30 KeV.
  • Next, referring to FIG. 2B, a mask layer 113 is covered on the active region 105. The mask layer 113 can be formed by the following steps. First, a mask material layer (not shown) is covered on the substrate 100. Next, a patterned photoresist layer (not shown) is formed on the cap material layer. Then, the photoresist layer is used as an etching mask to pattern the cap material layer. And finally, the patterned photoresist layer is removed. The material of the cap material layer 113 is, for example, silicon oxide, and the forming method is, for example, high temperature oxide (HTO) process.
  • Then, the substrate 100 in the active region 104 of the source/drain contact region 118 is removed to form grooves 114 in the substrate 100 at both sides of the spacer 112 in the active region 104. A semiconductor compound is refilled in the grooves 114, which functions as a source/drain contact region. The grooves 114 can be formed by anisotropic etching.
  • Thereafter, referring to FIG. 2B again, a selective area epitaxy growth process is performed to epitaxially grow semiconductor compound epitaxy layers in the grooves 114 and form dopants in the semiconductor compound epitaxy layers, so as to form source/drain contact regions 116.
  • In an embodiment, an NMOS transistor is preformed in the active region 105, and the dopants in the source/drain contact region 118 are n-type. A PMOS transistor is preformed in the active region 104, and the semiconductor compound epitaxy layer in the source/drain contact region 116 is, for example, a SiGe layer, wherein the dopants in the source/drain contact region 116 are p-type. The method of forming SiGe involves first introducing a gas source containing Si such as SiH4, CH2Cl2, or a combination thereof, a gas source containing Ge such as GeH4, HCl, and a dopant gas source such as BH3 as a reactive gas source into a CVD reaction chamber and then depositing at a temperature of 700-900° C. for 3-4 hours.
  • In another embodiment, a PMOS transistor is preformed in the active region 105, and the dopants in the source/drain contact region 118 are p-type. An NMOS transistor is preformed in the active region 104, and the semiconductor compound epitaxy layer in the source/drain contact region 116 is, for example, a SiC layer, wherein the dopants are n-type.
  • Afterwards, referring to 2C, the mask layer 113 is removed, and the spacers 112 in the active regions 104, 105 are also removed. Then, a photoresist mask layer is formed respectively, and an ion implantation process and a pocket ion implantation process are performed to form source/drain extension regions 120 and pocket implantation regions 134 and form source/drain extension regions 122 and pocket implantation regions 136 in the substrate 100 in the active regions 104 and 105 respectively. The source/drain extension region 120 and the source/drain contact region 116 constitute a source/drain region 130. The source/drain extension region 122 and the source/drain contact region 118 constitute a source/drain region 132. In an embodiment, an NMOS transistor is preformed in the active region 105, and the dopants in the source/drain extension region 122 are n-type. A PMOS transistor is preformed in the active region 104, and the dopants in the source/drain extension region 120 are p-type. In another embodiment, a PMOS transistor is preformed in the active region 105, and the dopants in the source/drain extension region 122 are p-type. An NMOS transistor is preformed in the active region 104, and the dopants in the source/drain extension region 120 are n-type.
  • Next, referring to FIG. 2D, a spacer 124 is formed at the sidewalls of the cap layer 109 and the gate conductive layer 108 in the active regions 104, 105 respectively. Next, a PAI process 126 is performed to amorphize the gate conductive layer 108 of each gate structure 110. The atom used in the PAI process 126 is selected from a group consisting of Ge, As, C, Sb, and a combination thereof. The energy for performing the PAI process 126 is between the energy for performing an ion implantation process for forming the source/drain extension region 122 and the energy for performing an ion implantation process for forming the source/drain contact region 118. In an embodiment, the energy for the ion implantation process in the source/drain extension region 122 is about 2-4 KeV. The energy for the ion implantation process in the source/drain contact region 118 is about 10-30 KeV. The atom used in the PAI process is Ge and the energy required is about 5-20 KeV.
  • Afterwards, referring to FIG. 2E, after the PAI process 126, an STS 128 is formed on the active region 105 for producing a stress in the gate conductive layer 108. The STS 128 can be formed by the following steps. First, an STS material layer is formed on the substrate 100. Then, a patterned photoresist layer is formed on the active region 105 of the substrate 100. Afterwards, the patterned photoresist layer is used as an etching mask to etch the STS material layer while leaving the STS 128 on the active region 105. Finally, the patterned photoresist layer is removed. The STS material layer is, for example, a SixNy layer or a SixOy layer, and the forming method thereof can be CVD. Thereafter, an RTA process is performed to activate the dopants in the source/ drain regions 130, 132.
  • Then, referring to FIG. 2F, the STS 128 is removed. The STS 128 can be removed by isotropic etching, for example, wet etching. When the material of the STS 128 is SixOy, hydrofluoric acid or buffered oxide etch (BOE) can be adopted as an etching solution to remove the STS 128. While when the material of the STS 128 is SixNy, hot phosphoric acid can be adopted as an etching solution to remove the STS 128.
  • The present invention performs the PAI process before the RTA process, so as to amorphize the gate conductive layer which is being crystallized under an over-high thermal budget of the epitaxy process into amorphous silicon with preferred stress memory characteristic. Therefore, after removing the STS, the stress generated by the STS to the gate conductive layer can still be memorized in the gate conductive layer for enhancing the ion performance.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (8)

1. A method of fabricating a semiconductor device, comprising:
providing a substrate;
forming a MOSFET in the substrate, wherein the MOSFET comprises a gate structure and a source/drain region;
after the MOSFET is formed, performing a PAI process to amorphize a gate conductive layer of the gate structure;
after the PAI process is performed, forming an STS on the substrate; and
performing an RTA process.
2. The method of fabricating a semiconductor device as claimed in claim 1, wherein the atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof.
3. The method of fabricating a semiconductor device as claimed in claim 1, wherein the source/drain region comprises a source/drain extension region and a source/drain contact region, and the energy for performing the PAI process is less than the energy for performing an ion implantation process for forming the source/drain contact region.
4. The method of fabricating a semiconductor device as claimed in claim 1, wherein the source/drain region comprises a source/drain extension region and a source/drain contact region, and the energy for performing the PAI process is greater than the energy for performing an ion implantation process for forming the source/drain extension region.
5. The method of fabricating a semiconductor device as claimed in claim 4, wherein the energy for performing the PAI process is between the energy for performing an ion implantation process for forming the source/drain extension region and the energy for performing an ion implantation process for forming the source/drain contact region.
6. The method of fabricating a semiconductor device as claimed in claim 5, wherein the atom used in the PAI process is Ge, and the energy for the PAI process is about 5-20 KeV.
7. The method of fabricating a semiconductor device as claimed in claim 1, wherein the material of the STS comprises SixOy or SixNy.
8. The method of fabricating a semiconductor device as claimed in claim 1, wherein the method of forming the MOSFET comprises:
forming the gate structure on the substrate, wherein the gate structure comprises a gate dielectric layer, a gate conductive layer, and a first spacer;
forming a source/drain contact region in the substrate;
removing the first spacer;
forming a source/drain extension region in the substrate around the gate conductive layer; and
forming a second spacer at the sidewalls of the gate conductive layer.
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