CN106226776A - A kind of LFSR counter for measuring photon flight time - Google Patents

Abstract

The invention discloses an LFSR counter for measuring photon flight time, which comprises 14 identical double-edge C ² MOS flip-flops, a four-input exclusive OR gate XNOR and a nmos setting switch. 14 identical double-edge C ² MOS flip-flops C ₀ ~C ₁₃ ; the source of the nmos set switch is the input control port VS, the gate of the nmos set switch is the input control port VG, and the substrate of the nmos set switch It is connected with the ground VSS; the drain of the nmos setting switch is connected with the input terminal D of the double-edge C ² MOS flip-flop C ₀ . The invention uses few devices and adopts double-edge trigger mode, which not only reduces the circuit area, but also reduces the clock frequency. An nmos set switch is used to avoid the cumbersome design of the combinational logic of the feedback network, so that the feedback network is realized by only a four-input XOR gate, which greatly reduces the circuit area and avoids the occurrence of dead loop phenomenon.

Description

A LFSR Counter for Measuring Photon Time-of-Flight

technical field

The invention belongs to the field of laser detection and readout circuits, in particular to an LFSR counter for measuring photon flight time.

Background technique

Active laser detection is a laser detection technology that uses a laser pulser to emit laser pulses to the target object to be detected, and calculates the distance to the target object by measuring the time between the echo pulse and the emitted pulse. In some special application fields, such as concealed military target detection, long-distance target detection and weak light target detection, etc., due to the requirements of detection concealment and the limitation of the target object's own lighting conditions, it is necessary to use high-sensitivity, fast-response Fast photodetectors are used for detection. Among the various photodetectors currently appearing, the Avalanche Photo Diode (APD) working in the Geiger mode can respond to a single photon and reach the limit of photon detection, so it is widely used in the above-mentioned fields.

With active laser detection, the distance from the transmitting optics to the target object can be obtained. If combined with the azimuth and elevation angles of the optical system, the three-dimensional information of the target object at the reflected photon can be obtained. If the detector array is used to receive the reflected photons of the target object, the three-dimensional information of the corresponding pixel can be obtained, and then the three-dimensional imaging of the target object can be realized through the corresponding algorithm.

Since the azimuth and elevation angles are provided by the optical system, at the circuit design level, it is the key for the circuit designer to realize the measurement of the time of flight (Time of Flight, TOF) of the photon. At present, the feature size of pixel circuits for 3D laser imaging using APD arrays is 50-100um. In order to adapt to such a small pixel area, it is necessary to carefully design each functional circuit module inside the pixel. On the basis of ensuring function and performance, a structure that is as stable and compact as possible is used to realize the time measurement function. In addition, the accuracy of time measurement mainly depends on the clock frequency - the higher the clock frequency, the higher the accuracy of the measured time. However, the high-frequency clock will be limited by the circuit layout and process in the actual circuit implementation, and its reliability is poor. Therefore, designing a reasonable circuit structure and making a better compromise between measurement accuracy and clock frequency has become another key to time measurement.

The essence of measuring time is counting clock cycles. From the moment the laser pulse is emitted, the main clock starts to oscillate synchronously, and a counter is used to count the number of clock cycles. Finally, the value of the counter is multiplied by the clock cycle, which is the round-trip flight time of the photon. A linear feedback shift register (Linear Feedback Shift Register, LFSR) is a counter commonly used to measure the flight time of photons. Figure 1 is a 14-bit LFSR with a traditional structure, which consists of 14 identical static D flip-flops C ₀ ~ C ₁₃ , 14 identical switches K ₀ ~ K ₁₃ and an XOR network. Among them, the output terminal Q of _C0 is connected to the input terminal D of _C1 , and the output terminal Q of _C1 is connected to the input terminal D of _C2 . By analogy, the output terminal Q of C ₁₂ is connected to the input terminal D of C ₁₃ ; the output terminals Q of C ₀ to C ₁₃ are respectively connected to the XOR network through switches K ₀ to K ₁₃ , and the output of the XOR network is connected to The input terminal D of C ₀ is used as feedback; the CLK terminals of C ₀ to C ₁₃ are all connected together as the clock input terminal CLK. The traditional LFSR has a simple structure, a small number of transistors, and a relatively moderate circuit area. However, as the mainstream counter structure of the current APD array 3D laser imaging, researchers often ignore the further simplification and innovation of its circuit structure, which leaves sufficient room for innovation in the present invention.

Contents of the invention

Aiming at the prior art, the present invention proposes a LFSR counter for measuring the photon flight time, which simplifies the combinational logic circuit of the feedback network by adopting the switch presetting mode, so that the circuit area is greatly reduced; The dynamic C ² MOS structure replaces the original static single-edge D flip-flop structure, and the clock frequency is reduced to half of the expected one under the premise of the same measurement accuracy. The invention provides a practical and effective solution for realizing the accurate measurement of the photon flight time and reducing the area of the pixel circuit.

In order to solve the above-mentioned technical problems, a kind of LFSR counter that the present invention proposes is used for measuring photon time-of-flight, comprises 14 identical double-edge C ² MOS flip-flops, 1 four-input XNOR and 1 nmos setting switch.

The 14 identical double-edge C ² MOS flip-flops are respectively recorded as double-edge C ² MOS flip-flop C ₀ , double-edge C ² MOS flip-flop C ₁ , double-edge C ² MOS flip-flop C ₂ , and double-edge C ² MOS trigger C ₃ , double edge C ² MOS flip flop C ₄ , double edge C ² MOS flip flop C ₅ , double edge C ² MOS flip flop C ₆ , double edge C ² MOS flip flop C ₇ , double edge C ² MOS trigger C ₈ , double-edge C ² MOS flip-flop C ₉ , double-edge C ² MOS flip-flop C ₁₀ , double-edge C ² MOS flip-flop C ₁₁ , double-edge C ² MOS flip-flop C ₁₂ and double-edge C ² MOS trigger Device C ₁₃ ; the source of the nmos setting switch is the input control port VS, the gate of the nmos setting switch is the input control port VG, and the substrate of the nmos setting switch is connected to the ground VSS; the The drain of the nmos setting switch is connected to the input terminal D of the double-edge C ² MOS flip-flop C ₀ .

The output Q of the ^double -edge ^C2 MOS flip-flop _C0 is connected to the input D of the double-edge ^C2 MOS flip-flop _C1 , and the output Q of the double-edge C2 MOS flip-flop _C1 is connected to the _The input terminal D of the ^double -edge ^C2 MOS flip-flop C2 is connected, the output Q of the _double -edge ^C2 MOS flip-flop C2 is connected with the input _D of the double-edge C2 MOS flip-flop C3, so _The output Q of the ^double -edge ^C2 MOS flip-flop C3 is connected to the input D of the double-edge ^C2 MOS flip-flop _C4 , and the output Q of the double-edge C2 MOS flip-flop _C4 is connected to the The input terminal D of the ^double -edge ^C2 MOS flip-flop _C5 is connected, the output Q of the double-edge ^C2 MOS flip-flop _C5 is connected with the input D of the double-edge C2 MOS flip-flop _C6 , and the The output Q of the ^double -edge ^C2 MOS flip _- flop _C6 is connected to the input D of the double-edge C2 MOS flip _- flop C7, and the output Q of the double-edge C2 MOS flip-flop C7 is connected to the double-edge ^C2 MOS flip-flop C7. _The input terminal D of the edge ^C2 MOS flip-flop C8 is connected, the output Q of the ^double -edge C2 _MOS flip-flop C8 is connected with the input D of the double-edge ^C2 MOS flip-flop _C9 , and the double-edge The output terminal Q of the edge C ² MOS flip-flop C ₉ is connected to the input terminal D of the double-edge C ² MOS flip-flop C ₁₀ , and the output Q of the double-edge C ² MOS flip-flop C ₁₀ is connected to the double-edge The input terminal D of the C ² MOS flip-flop C ₁₁ is connected, the output Q of the ^double -edge C MOS flip ^- flop C ₁₁ is connected with the input D of the double-edge C MOS flip-flop C ₁₂ , and the double-edge The output Q of the C ² MOS flip-flop C ₁₂ is connected to the input D of the double-edge C ² MOS flip-flop C ₁₃ ; the output of the double-edge C ² MOS flip-flop C ₁₃ is connected to the exclusive OR gate XNOR The input terminal A of the double-edge C ² MOS flip-flop C ₁₂ is connected to the input B of the exclusive OR gate XNOR, and the output terminal of the double-edge C ² MOS flip-flop C ₁₀ is connected to the _The input terminal C of the exclusive OR gate XNOR is connected, and the output terminal of the double-edge ^C2 MOS flip-flop C8 is connected with the input terminal D of the exclusive OR gate XNOR; the output terminal Q of the exclusive OR gate XNOR is connected with the The input terminal D of the double-edge C ² MOS flip-flop C ₀ is connected; the input terminals CLK of the 14 double-edge C ² MOS flip-flops C ₀ ~C ₁₃ are all connected together; the 14 double-edge C ² MOS flip-flops C ₀ ~ The input terminals CLKN of C ₁₃ are all connected together.

The internal structure of each double-edge C ² MOS flip-flop and the connection relationship between each device are as follows:

Each double-edge C ² MOS flip-flop includes 7 pmos tubes and 7 nmos tubes, and the 7 pmos tubes are respectively recorded as pmos tube P ₁ , pmos tube P ₂ , pmos tube P ₃ , pmos tube P ₄ , and pmos tube P _5. Pmos tube P ₆ and pmos tube P ₇ ; 7 nmos tubes are recorded as nmos tube N ₁ , nmos tube N ₂ , nmos tube N ₃ , nmos tube N ₄ , nmos tube N ₅ , nmos tube N ₆ and nmos tube tube N7 _; the sources of the _pmos tube P1, _pmos tube P2 and _pmos tube P6 are all connected to VDD; the sources _of the nmos tube N3, _nmos tube _N4 and nmos tube N7 are all connected to VSS connected; the substrates of the pmos tube P ₁ , pmos tube P ₂ , pmos tube P ₃ , pmos tube P ₄ , pmos tube P ₆ and pmos tube P ₇ are all connected to VDD; the nmos tube N ₁ , nmos tube The substrates of N ₂ , nmos tube N ₃ , nmos tube N ₄ , nmos tube N ₆ and nmos tube N ₇ are all connected to VSS; the drain of the pmos tube P ₁ , the source of the pmos tube P ₃ and The sources of the pmos transistor _P5 are all connected, the drain of the _pmos transistor P2 is connected to the source of the _pmos transistor P4, the drain of the _pmos transistor _P3 is connected to the nmos transistor N1 The drains are connected, the drain of the _pmos tube P4 is connected with the drain of the nmos tube _N2 , the source _of the nmos tube N1, the drain _of the nmos tube N3 and the nmos tube N ₅ sources are all connected, the source of the nmos tube _N2 is connected to the drain of the nmos tube _N4 ; the substrate of the pmos tube _P5 is connected to its source, and the drain of the pmos tube _P5 pole is connected with the drain of the nmos transistor _N5 , the substrate of the nmos transistor _N5 is connected with its source _; the drain of the pmos transistor P6 is connected with the source of the _pmos transistor P7, and the The drain of the pmos transistor P ₇ is connected to the drain of the nmos transistor N ₆ , the source of the nmos transistor N 6 is connected to the drain of the nmos transistor N ₇ ; the drain of the pmos transistor P ₃ is connected to the drain of the nmos transistor N ₆ The gate of the _pmos transistor P2 and the gate of the nmos transistor _N4 are connected, and the drain of the _pmos transistor _P5 is connected to the gate of the _pmos transistor P6 and the gate of the nmos transistor N7 connected, the drain of the _pmos tube P4, the drain of the nmos tube _N2 , the drain of the _pmos tube P7 and the drain of the nmos tube _N6 are all connected, and the _pmos tube P1 The grid of the nmos tube N3 is connected to the grid; the grids of the _pmos tube _P3 , _pmos tube P7, the nmos tube _N2 , nmos The gates of the transistor N ₅ are all connected; the gates of the pmos transistor P ₄ and the pmos transistor P ₅ , the gates of the nmos transistor N ₁ and the nmos transistor N ₆ are all connected.

The internal structure of the exclusive OR gate XNOR and the connection relationship between each device are as follows:

The exclusive OR gate XNOR includes 8 pmos tubes and 8 nmos tubes, and the 8 pmos tubes are respectively recorded as pmos tube P ₁₁ , pmos tube P ₁₂ , pmos tube P ₁₃ , pmos tube P ₁₄ , pmos tube P 15 , pmos tube P ₁₅ , pmos tube Tube P ₁₆ , pmos tube P ₁₇ and pmos tube P ₁₈ , and 8 nmos tubes are recorded as nmos tube N ₁₁ , nmos tube N ₁₂ , nmos tube N ₁₃ , nmos tube N ₁₄ , nmos tube N ₁₅ , nmos tube N ₁₆ , nmos tube N ₁₇ and nmos tube N ₁₈ ; the sources of the pmos tubes P ₁₁ , P ₁₂ , P ₁₃ , and P ₁₄ and the substrates of the pmos tubes P ₁₁ to P ₁₈ are all connected to VDD, and the nmos tubes The sources of the tubes N ₁₄ and N ₁₈ and the substrates of the nmos tubes N ₁₁ -N ₁₈ are connected to VSS; the drains of the pmos tubes P ₁₁ -P ₁₄ are connected to the pmos tubes P ₁₅ -P ₁₈ The sources are all connected, the drains of the _pmos tubes P15- _P18 are connected to the drains of the _nmos tubes N11 and _N15 ; the source _of the _nmos tube N11 is connected to the nmos tube N12 The drain of the nmos tube N12 is connected to the drain of the nmos tube _N13 , the source _of the _nmos tube _N13 is connected to the drain of the nmos tube N14, the nmos The source of the tube N ₁₅ is connected to the drain of the nmos tube N ₁₆ , the source of the nmos tube N ₁₆ is connected to the drain of the nmos tube N ₁₇ , the source of the nmos tube N ₁₇ is connected to the drain of the nmos tube N 17 The drain of the nmos transistor N18 is connected; the gate of the _pmos transistor _P11 is connected to the gate of the nmos transistor N15, and the gate of the _pmos transistor _P12 is connected to the gate of the nmos transistor _N16 The grid of the pmos transistor P ₁₃ is connected to the grid of the nmos transistor N ₁₇ , the grid of the pmos transistor P ₁₄ is connected to the grid of the nmos transistor N ₁₈ , and the grid of the pmos transistor P ₁₅ The grid of the _pmos transistor N11 is connected to the grid of the nmos transistor N11, the grid _of the _pmos transistor P16 is connected to the grid of the nmos transistor N12, the grid of the _pmos transistor P17 is connected to the nmos transistor The gate of the N ₁₃ is connected, and the gate of the pmos transistor P ₁₈ is connected with the gate of the nmos transistor N ₁₄ .

Compared with prior art, the beneficial effect of the present invention is:

The LFSR counter of the invention can accurately realize the measurement of the photon flight time, and the circuit structure is simple and optimized. Due to the optimization of the internal D flip-flop structure, the D flip-flop in the present invention adopts a dynamic C ² MOS structure triggered by double edges, which is realized with 24 transistors, while the static single-edge D flip-flop in the traditional design needs 26 transistors Realization, compared with the two, the present invention uses fewer transistors and smaller circuit area, and the double-edge trigger mode can also reduce the clock frequency by half, thus reducing the circuit area and simultaneously reducing the clock frequency. In addition, an nmos set switch is adopted in the present invention, which avoids the cumbersome design of the combinational logic of the feedback network, so that the feedback network is only realized by a four-input XOR gate, which greatly reduces the circuit area and avoids the dead loop phenomenon at the same time happened.

Description of drawings

Fig. 1 is a schematic diagram of a traditional linear feedback shift register (LFSR);

Fig. 2 is four input XOR gate circuit diagrams of the present invention;

Fig. 3 is the circuit diagram of double-edge trigger ^C2 MOS structure of the present invention;

Fig. 4 is a schematic diagram of a linear feedback shift register (LFSR) of the present invention;

detailed description

The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the described specific embodiments are only for explaining the present invention, and are not intended to limit the present invention.

As shown in Figure 4, it is a kind of LFSR counter for measuring photon flight time proposed by the present invention, including 14 identical double-edge C ² MOS flip-flops, 1 four-input exclusive OR gate XNOR and 1 nmos setting switch.

The 14 identical double-edge C ² MOS flip-flops are respectively recorded as double-edge C ² MOS flip-flop C ₀ , double-edge C ² MOS flip-flop C ₁ , double-edge C ² MOS flip-flop C ₂ , and double-edge C ² MOS trigger C ₃ , double edge C ² MOS flip flop C ₄ , double edge C ² MOS flip flop C ₅ , double edge C ² MOS flip flop C ₆ , double edge C ² MOS flip flop C ₇ , double edge C ² MOS trigger C ₈ , double-edge C ² MOS flip-flop C ₉ , double-edge C ² MOS flip-flop C ₁₀ , double-edge C ² MOS flip-flop C ₁₁ , double-edge C ² MOS flip-flop C ₁₂ and double-edge C ² MOS trigger device C ₁₃ .

The source of the nmos setting switch is the input control port VS, the gate of the nmos setting switch is the input control port VG, and the substrate of the nmos setting switch is connected to the ground VSS; the nmos setting switch The drain of is connected to the input terminal D of the double-edge C ² MOS flip-flop C ₀ .

The output Q of the ^double -edge ^C2 MOS flip-flop _C0 is connected to the input D of the double-edge ^C2 MOS flip-flop _C1 , and the output Q of the double-edge C2 MOS flip-flop _C1 is connected to the _The input terminal D of the ^double -edge ^C2 MOS flip-flop C2 is connected, the output Q of the _double -edge ^C2 MOS flip-flop C2 is connected with the input _D of the double-edge C2 MOS flip-flop C3, so _The output Q of the ^double -edge ^C2 MOS flip-flop C3 is connected to the input D of the double-edge ^C2 MOS flip-flop _C4 , and the output Q of the double-edge C2 MOS flip-flop _C4 is connected to the The input terminal D of the ^double -edge ^C2 MOS flip-flop _C5 is connected, the output Q of the double-edge ^C2 MOS flip-flop _C5 is connected with the input D of the double-edge C2 MOS flip-flop _C6 , and the The output Q of the ^double -edge ^C2 MOS flip _- flop _C6 is connected to the input D of the double-edge C2 MOS flip _- flop C7, and the output Q of the double-edge C2 MOS flip-flop C7 is connected to the double-edge ^C2 MOS flip-flop C7. _The input terminal D of the edge ^C2 MOS flip-flop C8 is connected, the output Q of the ^double -edge C2 _MOS flip-flop C8 is connected with the input D of the double-edge ^C2 MOS flip-flop _C9 , and the double-edge The output terminal Q of the edge C ² MOS flip-flop C ₉ is connected to the input terminal D of the double-edge C ² MOS flip-flop C ₁₀ , and the output Q of the double-edge C ² MOS flip-flop C ₁₀ is connected to the double-edge The input terminal D of the C ² MOS flip-flop C ₁₁ is connected, the output Q of the ^double -edge C MOS flip ^- flop C ₁₁ is connected with the input D of the double-edge C MOS flip-flop C ₁₂ , and the double-edge The output terminal Q of the C ² MOS flip-flop C ₁₂ is connected to the input terminal D of the double-edge C ² MOS flip-flop C ₁₃ .

The output end of the double-edge C ² MOS flip-flop C ₁₃ is connected to the input A of the exclusive OR gate XNOR, and the output end of the double-edge C ² MOS flip-flop C ₁₂ is connected to the input of the exclusive OR gate XNOR Terminal B is connected, the output terminal of the double-edge C ² MOS flip-flop C ₁₀ is connected to the input terminal C of the exclusive OR gate XNOR, and the output terminal of the double-edge C ² MOS flip-flop C ₈ is connected to the exclusive-or gate XNOR The input terminal D of the gate XNOR is connected; the output terminal Q of the XNOR gate is connected with the input terminal D of the double-edge C ² MOS flip-flop C ₀ .

The input terminals CLK of the 14 double-edge C ² MOS flip-flops C ₀ -C ₁₃ are all connected together; the input terminals CLKN of the 14 double-edge C ² MOS flip-flops C ₀ -C ₁₃ are all connected together.

The internal structure of each double-edge C ² MOS flip-flop and the connection relationship between each device are as follows:

As shown in Figure 3, each double-edge C ² MOS flip-flop includes 7 pmos tubes and 7 nmos tubes, and the 7 pmos tubes are respectively recorded as pmos tube P ₁ , pmos tube P ₂ , pmos tube P ₃ , and pmos tube P ₄ , pmos tube P ₅ , pmos tube P ₆ and pmos tube P ₇ ; the seven nmos tubes are recorded as nmos tube N ₁ , nmos tube N ₂ , nmos tube N ₃ , nmos tube N ₄ , nmos tube N ₅ , nmos tube N ₆ and nmos tube N ₇ .

The sources of the pmos tube P ₁ , pmos tube P ₂ and pmos tube P ₆ are all connected to VDD; the sources of the nmos tube N ₃ , nmos tube N ₄ and nmos tube N ₇ are all connected to VSS; the The substrates of pmos tube P ₁ , pmos tube P ₂ , pmos tube P ₃ , pmos tube P ₄ , pmos tube P ₆ and pmos tube P ₇ are all connected to VDD; the nmos tube N ₁ , nmos tube N ₂ , nmos tube The substrates of tube N ₃ , nmos tube N ₄ , nmos tube N ₆ and nmos tube N ₇ are all connected to VSS; the drain of the pmos tube P ₁ , the source of the pmos tube P ₃ and the pmos tube The sources of _P5 are all connected, the drain of the _pmos transistor P2 is connected with the source of the _pmos transistor P4, the drain of the pmos transistor _P3 is connected with the drain _of the nmos transistor N1, The drain of the _pmos tube P4 is connected to the drain of the nmos tube _N2 , the source _of the nmos tube N1, the drain _of the nmos tube N3 and the source of the nmos tube _N5 are connected, the source of the nmos tube _N2 is connected to the drain of the nmos tube _N4 ; the substrate of the pmos tube _P5 is connected to its source, and the drain of the pmos tube _P5 is connected to the drain of the nmos tube N4 The drain of the nmos tube _N5 is connected, the substrate of the nmos tube _N5 is connected to its source _; the drain of the pmos tube P6 is connected to the source of the _pmos tube P7, and the _pmos tube P7 The drain of the nmos tube _N6 is connected to the drain of the nmos tube _N6 , the source of the nmos tube N6 is connected to the drain of the nmos tube N7 _; the drain of the pmos tube _P3 is connected to the pmos tube _The gate of P2 is connected to the gate of the nmos transistor _N4 , the drain of the _pmos transistor _P5 is connected to the gate of the _pmos transistor P6 and the gate of the nmos transistor N7, the The drain of the _pmos transistor P4, the drain of the nmos transistor _N2 , the drain of the _pmos transistor P7 and the drain of the nmos transistor _N6 are all connected, and the gate of the _pmos transistor P1 and The gates of the nmos transistor N3 are connected; the gates of the _pmos transistor _P3 and the _pmos transistor P7, the gates of the nmos transistor _N2 and the nmos transistor _N5 are all connected; the _pmos transistors P4, The grid of the pmos transistor _P5 , the grids _of the nmos transistor N1 and the nmos transistor _N6 are all connected;

As shown in Figure 2, the internal structure of the exclusive OR gate XNOR and the connection relationship between each device are as follows:

The exclusive OR gate XNOR includes 8 pmos tubes and 8 nmos tubes, and the 8 pmos tubes are respectively recorded as pmos tube P ₁₁ , pmos tube P ₁₂ , pmos tube P ₁₃ , pmos tube P ₁₄ , pmos tube P 15 , pmos tube P ₁₅ , pmos tube Tube P ₁₆ , pmos tube P ₁₇ and pmos tube P ₁₈ , and 8 nmos tubes are recorded as nmos tube N ₁₁ , nmos tube N ₁₂ , nmos tube N ₁₃ , nmos tube N ₁₄ , nmos tube N ₁₅ , nmos tube N ₁₆ , nmos tube N ₁₇ and nmos tube N ₁₈ .

The sources of the pmos transistors P ₁₁ , P ₁₂ , P ₁₃ , and P ₁₄ and the substrates of the pmos transistors P ₁₁ -P ₁₈ are all connected to VDD, and the sources of the nmos transistors N ₁₄ and N ₁₈ are connected to the The substrates of the nmos transistors N ₁₁ to N ₁₈ are all connected to VSS; the drains of the pmos transistors P ₁₁ to P ₁₄ are connected to the sources of the pmos transistors P ₁₅ to P ₁₈ , and the P of the pmos transistors P The drains of ₁₅ to P ₁₈ are connected to the drains of the nmos tubes N ₁₁ and N ₁₅ ; the source of the nmos tube N ₁₁ is connected to the drain of the nmos tube N ₁₂ , and the nmos tube N ₁₂ The source of the nmos tube _N13 is connected to the drain of the nmos tube _N13 , the source of the nmos tube _N13 is connected to the drain of the nmos tube _N14 , the source of the nmos tube N15 is connected to the nmos tube The drain of N ₁₆ is connected, the source of the nmos tube N ₁₆ is connected to the drain of the nmos tube N ₁₇ , the source of the nmos tube N ₁₇ is connected to the drain of the nmos tube N ₁₈ ; The grid of the _pmos transistor P11 is connected to the grid of the nmos transistor N15, the grid of the _pmos transistor _P12 is connected to the grid of the nmos transistor N16, and the grid of the _pmos transistor _P13 It is connected to the gate of the nmos transistor N17, the gate of the _pmos transistor P14 is connected to the gate of the nmos transistor N18, the gate of the _pmos transistor _P15 is connected to the gate of the _nmos transistor _N11 The grid of the _pmos transistor P16 is connected to the grid of the nmos transistor N12, the grid of the _pmos transistor P17 is connected to the grid of the nmos transistor N13, and the grid of the _pmos transistor _N13 is connected. The gate of P ₁₈ is connected to the gate of the nmos transistor N ₁₄ .

The working process of the LFSR counter that the present invention is used to measure photon time-of-flight is as follows:

Before the circuit starts to work, the input terminal D of the C ² MOS flip-flop C ₀ is input with a high level "1" by the nmos setting switch. When timing starts, the main clock signal is input to the CLK terminal of the circuit, and the clock signal reversed by the main clock signal is input to the CLKN terminal of the circuit. During the timing process, the high level "1" of the input terminal D of the C ² MOS flip-flop C ₀ will transmit "1" to the input terminal D of the C ² MOS flip-flop C ₁ along with the first rising edge of the CLK signal; When the falling edge of the first CLK signal comes, "1" is sent to the input terminal D of C ² MOS flip-flop C ₂ ; when the rising edge of the second CLK signal comes, "1" is sent to C ² The input terminal D of MOS flip-flop C ₃ ; when the falling edge of the second CLK signal comes, "1" is transmitted to the input terminal D of C ² MOS flip-flop C ₄ ; and so on until the seventh CLK signal When the falling edge comes, "1" is sent to the input A of the exclusive OR gate XNOR. At this time, the "1" of the output terminal Q of the C ² MOS flip-flop C ₁₂ , the "1" of the output terminal Q of the C ² MOS flip-flop C ₁₀ and the "1" of the output terminal Q of the C ² MOS flip-flop C ₈ are respectively input to In the input terminals B, C and D of the exclusive OR gate XNOR, after an exclusive OR operation, the output "0" is fed back to the input terminal D of the C ² MOS flip-flop C ₀ . Afterwards, "0" or "1" is sequentially transmitted to the next C ² MOS structure according to the arrival of the rising and falling edges of the CLK signal, and the calculated value is fed back to the C ² MOS flip-flop C by the exclusive OR gate XNOR ₀ on input D. The counting continues as long as the clock is not stopped.

In the present invention, when the power supply voltage is 1.8V and the clock frequency is within 1GHz, accurate measurement of photon flight time can be realized.

Although the present invention has been described above in conjunction with the drawings, the present invention is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, rather than restrictive. Under the inspiration, many modifications can be made without departing from the gist of the present invention, and these all belong to the protection of the present invention.

Claims (1)

1. A kind of LFSR counter that is used to measure photon flight time is characterized in that, comprises 14 identical double-edge C ² MOS flip-flops, 1 four-input exclusive OR gate XNOR and 1 nmos setting switch; The 14 identical double-edge C ² MOS flip-flops are respectively recorded as double-edge C ² MOS flip-flop C ₀ , double-edge C ² MOS flip-flop C ₁ , double-edge C ² MOS flip-flop C ₂ , and double-edge C ² MOS trigger C ₃ , double edge C ² MOS flip flop C ₄ , double edge C ² MOS flip flop C ₅ , double edge C ² MOS flip flop C ₆ , double edge C ² MOS flip flop C ₇ , double edge C ² MOS trigger C ₈ , double-edge C ² MOS flip-flop C ₉ , double-edge C ² MOS flip-flop C ₁₀ , double-edge C ² MOS flip-flop C ₁₁ , double-edge C ² MOS flip-flop C ₁₂ and double-edge C ² MOS trigger Device C ₁₃ ; The source of the nmos setting switch is the input control port VS, the gate of the nmos setting switch is the input control port VG, and the substrate of the nmos setting switch is connected to the ground VSS; the nmos setting switch The drain is connected to the input terminal D of the double-edge C ² MOS flip-flop C ₀ ; The output Q of the ^double -edge ^C2 MOS flip-flop _C0 is connected to the input D of the double-edge ^C2 MOS flip-flop _C1 , and the output Q of the double-edge C2 MOS flip-flop _C1 is connected to the _The input terminal D of the ^double -edge ^C2 MOS flip-flop C2 is connected, the output Q of the _double -edge ^C2 MOS flip-flop C2 is connected with the input _D of the double-edge C2 MOS flip-flop C3, so _The output Q of the ^double -edge ^C2 MOS flip-flop C3 is connected to the input D of the double-edge ^C2 MOS flip-flop _C4 , and the output Q of the double-edge C2 MOS flip-flop _C4 is connected to the The input terminal D of the ^double -edge ^C2 MOS flip-flop _C5 is connected, the output Q of the double-edge ^C2 MOS flip-flop _C5 is connected with the input D of the double-edge C2 MOS flip-flop _C6 , and the The output Q of the ^double -edge ^C2 MOS flip _- flop _C6 is connected to the input D of the double-edge C2 MOS flip _- flop C7, and the output Q of the double-edge C2 MOS flip-flop C7 is connected to the double-edge ^C2 MOS flip-flop C7. _The input terminal D of the edge ^C2 MOS flip-flop C8 is connected, the output Q of the ^double -edge C2 _MOS flip-flop C8 is connected with the input D of the double-edge ^C2 MOS flip-flop _C9 , and the double-edge The output terminal Q of the edge C ² MOS flip-flop C ₉ is connected to the input terminal D of the double-edge C ² MOS flip-flop C ₁₀ , and the output Q of the double-edge C ² MOS flip-flop C ₁₀ is connected to the double-edge The input terminal D of the C ² MOS flip-flop C ₁₁ is connected, the output Q of the ^double -edge C MOS flip ^- flop C ₁₁ is connected with the input D of the double-edge C MOS flip-flop C ₁₂ , and the double-edge The output Q of the C ² MOS flip-flop C ₁₂ is connected to the input D of the ^double -edge C MOS flip-flop C ₁₃ ; The output end of the double-edge C ² MOS flip-flop C ₁₃ is connected to the input A of the exclusive OR gate XNOR, and the output end of the double-edge C ² MOS flip-flop C ₁₂ is connected to the input of the exclusive OR gate XNOR Terminal B is connected, the output terminal of the double-edge C ² MOS flip-flop C ₁₀ is connected to the input terminal C of the exclusive OR gate XNOR, and the output terminal of the double-edge C ² MOS flip-flop C ₈ is connected to the exclusive-or gate XNOR The input terminal D of the gate XNOR is connected; the output terminal Q of the exclusive OR gate XNOR is connected with the input terminal D of the double-edge ^C2 MOS flip-flop _C0 ; The input terminals CLK of the 14 double-edge C ² MOS flip-flops C ₀ -C ₁₃ are all connected together; the input terminals CLKN of the 14 double-edge C ² MOS flip-flops C ₀ -C ₁₃ are all connected together; The internal structure of each double-edge C ² MOS flip-flop and the connection relationship between each device are as follows: Each double-edge C ² MOS flip-flop includes 7 pmos tubes and 7 nmos tubes, and the 7 pmos tubes are respectively recorded as pmos tube P ₁ , pmos tube P ₂ , pmos tube P ₃ , pmos tube P ₄ , and pmos tube P _5. Pmos tube P ₆ and pmos tube P ₇ ; 7 nmos tubes are recorded as nmos tube N ₁ , nmos tube N ₂ , nmos tube N ₃ , nmos tube N ₄ , nmos tube N ₅ , nmos tube N ₆ and nmos tube Tube _N7 ; The sources of the pmos tube P ₁ , pmos tube P ₂ and pmos tube P ₆ are all connected to VDD; the sources of the nmos tube N ₃ , nmos tube N ₄ and nmos tube N ₇ are all connected to VSS; the The substrates of pmos tube P ₁ , pmos tube P ₂ , pmos tube P ₃ , pmos tube P ₄ , pmos tube P ₆ and pmos tube P ₇ are all connected to VDD; the nmos tube N ₁ , nmos tube N ₂ , nmos tube The substrates of tube N ₃ , nmos tube N ₄ , nmos tube N ₆ and nmos tube N ₇ are all connected to VSS; the drain of the pmos tube P ₁ , the source of the pmos tube P ₃ and the pmos tube The sources of _P5 are all connected, the drain of the _pmos transistor P2 is connected with the source of the _pmos transistor P4, the drain of the pmos transistor _P3 is connected with the drain _of the nmos transistor N1, The drain of the _pmos tube P4 is connected to the drain of the nmos tube _N2 , the source _of the nmos tube N1, the drain _of the nmos tube N3 and the source of the nmos tube _N5 are connected, the source of the nmos tube _N2 is connected to the drain of the nmos tube _N4 ; the substrate of the pmos tube _P5 is connected to its source, and the drain of the pmos tube _P5 is connected to the drain of the nmos tube N4 The drain of the nmos tube _N5 is connected, the substrate of the nmos tube _N5 is connected to its source _; the drain of the pmos tube P6 is connected to the source of the _pmos tube P7, and the _pmos tube P7 The drain of the nmos tube _N6 is connected to the drain of the nmos tube _N6 , the source of the nmos tube N6 is connected to the drain of the nmos tube N7 _; the drain of the pmos tube _P3 is connected to the pmos tube _The gate of P2 is connected to the gate of the nmos transistor _N4 , the drain of the _pmos transistor _P5 is connected to the gate of the _pmos transistor P6 and the gate of the nmos transistor N7, the The drain of the _pmos transistor P4, the drain of the nmos transistor _N2 , the drain of the _pmos transistor P7 and the drain of the nmos transistor _N6 are all connected, and the gate of the _pmos transistor P1 and The gates of the nmos transistor N3 are connected; the gates of the _pmos transistor _P3 and the _pmos transistor P7, the gates of the nmos transistor _N2 and the nmos transistor _N5 are all connected; the _pmos transistors P4, The grid of the pmos transistor _P5 , the grids _of the nmos transistor N1 and the nmos transistor _N6 are all connected; The internal structure of the exclusive OR gate XNOR and the connection relationship between each device are as follows: The exclusive OR gate XNOR includes 8 pmos tubes and 8 nmos tubes, and the 8 pmos tubes are respectively recorded as pmos tube P ₁₁ , pmos tube P ₁₂ , pmos tube P ₁₃ , pmos tube P ₁₄ , pmos tube P 15 , pmos tube P ₁₅ , pmos tube Tube P ₁₆ , pmos tube P ₁₇ and pmos tube P ₁₈ , and 8 nmos tubes are recorded as nmos tube N ₁₁ , nmos tube N ₁₂ , nmos tube N ₁₃ , nmos tube N ₁₄ , nmos tube N ₁₅ , nmos tube N ₁₆ , nmos tube N ₁₇ and nmos tube N ₁₈ ; The sources of the pmos transistors P ₁₁ , P ₁₂ , P ₁₃ , and P ₁₄ and the substrates of the pmos transistors P ₁₁ -P ₁₈ are all connected to VDD, and the sources of the nmos transistors N ₁₄ and N ₁₈ are connected to the The substrates of the nmos transistors N ₁₁ to N ₁₈ are all connected to VSS; the drains of the pmos transistors P ₁₁ to P ₁₄ are connected to the sources of the pmos transistors P ₁₅ to P ₁₈ , and the P of the pmos transistors P The drains of ₁₅ to P ₁₈ are connected to the drains of the nmos tubes N ₁₁ and N ₁₅ ; the source of the nmos tube N ₁₁ is connected to the drain of the nmos tube N ₁₂ , and the nmos tube N ₁₂ The source of the nmos tube _N13 is connected to the drain of the nmos tube _N13 , the source of the nmos tube _N13 is connected to the drain of the nmos tube _N14 , the source of the nmos tube N15 is connected to the nmos tube The drain of N ₁₆ is connected, the source of the nmos tube N ₁₆ is connected to the drain of the nmos tube N ₁₇ , the source of the nmos tube N ₁₇ is connected to the drain of the nmos tube N ₁₈ ; The grid of the _pmos transistor P11 is connected to the grid of the nmos transistor N15, the grid of the _pmos transistor _P12 is connected to the grid of the nmos transistor N16, and the grid of the _pmos transistor _P13 It is connected to the gate of the nmos transistor N17, the gate of the _pmos transistor P14 is connected to the gate of the nmos transistor N18, the gate of the _pmos transistor _P15 is connected to the gate of the _nmos transistor _N11 The grid of the _pmos transistor P16 is connected to the grid of the nmos transistor N12, the grid of the _pmos transistor P17 is connected to the grid of the nmos transistor N13, and the grid of the _pmos transistor _N13 is connected. The gate of P ₁₈ is connected to the gate of the nmos transistor N ₁₄ .