CN106206898B - A kind of production method of light emitting diode - Google Patents
A kind of production method of light emitting diode Download PDFInfo
- Publication number
- CN106206898B CN106206898B CN201610809998.9A CN201610809998A CN106206898B CN 106206898 B CN106206898 B CN 106206898B CN 201610809998 A CN201610809998 A CN 201610809998A CN 106206898 B CN106206898 B CN 106206898B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- emitting diode
- light emitting
- particles
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 83
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000002245 particle Substances 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000000137 annealing Methods 0.000 claims abstract description 21
- 238000009826 distribution Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 127
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims 1
- 239000000460 chlorine Substances 0.000 claims 1
- 229910052801 chlorine Inorganic materials 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 8
- 238000000059 patterning Methods 0.000 abstract description 5
- 239000002086 nanomaterial Substances 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000000717 retained effect Effects 0.000 description 6
- 239000007771 core particle Substances 0.000 description 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 3
- 238000004880 explosion Methods 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004049 embossing Methods 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
- H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biophysics (AREA)
- Optics & Photonics (AREA)
- Led Devices (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
本发明提出一种发光二极管的制作方法,包括:提供一磊晶片,并沉积一金属Ni层;将所述金属Ni层图案化,定义P型半导体区域上的金属Ni层保留,N型半导体区域上的金属Ni层去除;将具图案化金属Ni层的磊晶片进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布;在所述金属Ni颗粒上形成掩膜层;以所述金属Ni颗粒及掩膜层作为掩膜结构,进行蚀刻工艺,先进行第一步蚀刻,使得掩膜层内缩,然后再进行第二步蚀刻,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构。
The present invention proposes a method for manufacturing a light-emitting diode, comprising: providing an epitaxial wafer, and depositing a metal Ni layer; patterning the metal Ni layer, defining the metal Ni layer on the P-type semiconductor region to remain, and the N-type semiconductor region The metal Ni layer on the epiwafer is removed; the epiwafer with the patterned metal Ni layer is annealed, and after annealing, the metal Ni layer presents a granular distribution on the epiwafer; a mask layer is formed on the metal Ni particles; The metal Ni particles and the mask layer are used as a mask structure, and the etching process is carried out. The first step of etching is first performed to make the mask layer shrink inward, and then the second step of etching is performed to obtain a light-emitting diode with an inclined surface, and the inclined surface form nanostructures.
Description
技术领域technical field
本发明涉及半导体技术领域,尤其是一种具有纳米微结构倾斜侧面的发光二极管的制作方法。The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a light-emitting diode with inclined side surfaces of nano-microstructures.
背景技术Background technique
现有的具有倾斜侧面的LED结构,制作N电极,大部分是黄光光罩后,直接利用干法蚀刻的方式,蚀刻到N型半导体层,然后制作电极,如此会出现两方面问题:(1)金属N电极对侧面光的吸收;(2)光滑的侧面使得LED芯粒内部发出的光容易出射,不能被利用,如图(1)所示。In the existing LED structure with slanted sides, after making N electrodes, most of them are yellow light masks, and then directly use dry etching to etch to the N-type semiconductor layer, and then make electrodes, so there will be two problems: (1) The metal N electrode absorbs side light; (2) The smooth side makes the light emitted inside the LED chip easy to exit and cannot be used, as shown in Figure (1).
中国专利CN105378950A公开了一种顶发射式半导体发光器件,提出先将每一个独立的发光单元以固定间距固定在载体上面,然后在两个发光单元之间通过分发或模制透明层或者颗粒,达到反射光的目的,但是该方法存在一些不足:(1)在发光部件的周围沉积一层介质,容易引入杂质,造成侧面P层、MQW层和N层连通,最后短路。在实际的LED生产中很大一部分失效如漏电或者ESD爆点出现在发光部件周围。(2)只在发光部件周围布置一层透明层或者颗粒,对于N电极的吸收部分不能避免。Chinese patent CN105378950A discloses a top-emitting semiconductor light-emitting device, which proposes to fix each independent light-emitting unit on the carrier at a fixed distance, and then distribute or mold a transparent layer or particles between the two light-emitting units to achieve The purpose of reflecting light, but this method has some shortcomings: (1) A layer of medium is deposited around the light-emitting component, which is easy to introduce impurities, causing the side P layer, MQW layer and N layer to be connected, and finally short-circuited. In the actual LED production, a large part of the failures such as leakage or ESD explosion occurs around the light-emitting components. (2) Only arrange a layer of transparent layer or particles around the light-emitting component, and the absorption part of the N electrode cannot be avoided.
发明内容Contents of the invention
本发明的目的在于:提出一种发光二极管的制作方法,其倾斜侧面形成纳米微结构,增加了光的漫反射,使得芯片侧面发出的光改变光路,从正向发出,减少N电极对光的吸光,使得亮度增加;纳米微结构与芯片材料同质,不会由于引入其他材料造成漏电或者ESD爆点。The object of the present invention is to: propose a kind of manufacturing method of light-emitting diode, its inclined side forms nanometer structure, has increased the diffuse reflection of light, makes the light that chip side sends changes optical path, sends out from positive direction, reduces N electrode to light Light absorption increases the brightness; the nano-microstructure is homogeneous with the chip material, and will not cause leakage or ESD burst due to the introduction of other materials.
根据本发明的第一方面,提供一种发光二极管的制作方法,包括步骤:According to a first aspect of the present invention, a method for manufacturing a light emitting diode is provided, comprising the steps of:
(1)提供一磊晶片,并沉积一金属Ni层;(1) Provide an epitaxial wafer and deposit a metal Ni layer;
(2)将所述金属Ni层图案化,定义P型半导体区域上的金属Ni层保留,N型半导体区域上的金属Ni层去除;(2) Patterning the metal Ni layer, defining that the metal Ni layer on the P-type semiconductor region is retained, and the metal Ni layer on the N-type semiconductor region is removed;
(3)将具图案化金属Ni层的磊晶片进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布;(3) Annealing the epiwafer with the patterned metal Ni layer, after annealing, the metal Ni layer presents a granular distribution on the epiwafer;
(4)在所述金属Ni颗粒上形成掩膜层;(4) forming a mask layer on the metal Ni particles;
(5)以所述金属Ni颗粒及掩膜层作为掩膜结构,进行蚀刻工艺,先进行第一步蚀刻,使得掩膜层内缩,然后再进行第二步蚀刻,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构。(5) Using the metal Ni particles and the mask layer as a mask structure, an etching process is performed. First, the first step of etching is performed to shrink the mask layer, and then the second step of etching is performed to obtain a luminescent surface with an inclined surface. Diode, and the inclined surface forms nano-microstructures.
根据本发明的第二方面,还提供另一种发光二极管的制作方法,包括步骤:According to the second aspect of the present invention, there is also provided another method for manufacturing a light emitting diode, comprising the steps of:
(1)提供一磊晶片,并沉积一金属Ni层;(1) Provide an epitaxial wafer and deposit a metal Ni layer;
(2)将具金属Ni层的磊晶片进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布;(2) Annealing the epiwafer with the metal Ni layer, after annealing, the metal Ni layer presents a granular distribution on the epiwafer;
(3)将所述金属Ni颗粒图案化,定义P型半导体区域上的金属Ni颗粒保留,N型半导体区域上的金属Ni颗粒去除;(3) Patterning the metal Ni particles, defining that the metal Ni particles on the P-type semiconductor region are retained, and the metal Ni particles on the N-type semiconductor region are removed;
(4)在所述金属Ni颗粒上形成掩膜层;(4) forming a mask layer on the metal Ni particles;
(5)以所述金属Ni颗粒及掩膜层作为掩膜结构,进行蚀刻工艺,先进行第一步蚀刻,使得掩膜层内缩,然后再进行第二步蚀刻,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构。(5) Using the metal Ni particles and the mask layer as a mask structure, an etching process is performed. First, the first step of etching is performed to shrink the mask layer, and then the second step of etching is performed to obtain a luminescent surface with an inclined surface. Diode, and the inclined surface forms nano-microstructures.
优选地,所述金属Ni层的厚度为3~200nm。Preferably, the thickness of the metal Ni layer is 3-200 nm.
优选地,所述退火处理条件:温度为500~800℃,时间为0.5~10min。Preferably, the annealing treatment conditions: the temperature is 500-800° C., and the time is 0.5-10 min.
优选地,所述步骤(4)中的掩膜层选用光阻或氧化物或金属。Preferably, the mask layer in the step (4) is selected from photoresist or oxide or metal.
优选地,所述步骤(4)之前还包括步骤:沉积一绝缘保护层用于保护位于所述N型半导体区域的磊晶层在步骤(5)蚀刻工艺中不被先蚀刻。Preferably, before the step (4), a step is further included: depositing an insulating protection layer for protecting the epitaxial layer located in the N-type semiconductor region from being etched first in the etching process of the step (5).
优选地,所述步骤(5)中第一步蚀刻用于先使得掩膜层内缩0.1~1μm。Preferably, the first step of etching in the step (5) is used to shrink the mask layer by 0.1-1 μm.
优选地,所述步骤(5)中第一步蚀刻采用湿法蚀刻或者干法蚀刻工艺。Preferably, the first step of etching in the step (5) adopts a wet etching or dry etching process.
优选地,所述步骤(5)中第一步干法蚀刻工艺,包括:通入氧气或四氟化碳或前述组合,上电极功率:150~2000W,下电极功率:0~400W,时间:20~200s。Preferably, the first dry etching process in the step (5) includes: introducing oxygen or carbon tetrafluoride or a combination of the above, upper electrode power: 150~2000W, lower electrode power: 0~400W, time: 20~200s.
优选地,所述步骤(5)中第二步蚀刻采用干法蚀刻工艺。Preferably, the second etching step in the step (5) adopts a dry etching process.
优选地,所述步骤(5)中第二步干法蚀刻工艺,包括:通入三氯化硼或氯气或前述组合,上电极功率:150~500W,下电极功率:50~500W,时间:300~600s。Preferably, the second dry etching process in the step (5) includes: feeding boron trichloride or chlorine gas or the aforementioned combination, upper electrode power: 150~500W, lower electrode power: 50~500W, time: 300~600s.
现有技术制作具有倾斜侧面的LED结构,通常是先制作P型半导体区域和N型半导体区域,此时芯粒倾斜表面为光滑结构,然后再在芯粒侧面通过沉积或者模制颗粒。与现有技术相比,本发明提供的一种发光二极管的制作方法,至少包括以下技术效果:In the prior art, the LED structure with sloped side is manufactured by first manufacturing the P-type semiconductor region and the N-type semiconductor region. At this time, the sloped surface of the core particle is a smooth structure, and then depositing or molding particles on the side of the core particle. Compared with the prior art, a method for manufacturing a light-emitting diode provided by the present invention at least includes the following technical effects:
(1)现有技术工艺流程较为复杂,成本较高,而本发明利用金属颗粒和掩膜层作为掩膜结构,在发光二极管的制作P型半导体区域和N型半导体区域的同时,在倾斜侧面形成纳米微结构,增加了光的漫反射,使得芯片侧面发出的光改变光路,从正向朝上发出,减少N电极对光的吸光,使得亮度增加;(1) The process flow of the prior art is relatively complicated and the cost is high, but the present invention uses metal particles and a mask layer as a mask structure, and at the same time of making the P-type semiconductor region and the N-type semiconductor region of the light-emitting diode, on the inclined side The nano-microstructure is formed to increase the diffuse reflection of light, so that the light emitted from the side of the chip changes the optical path, and is emitted from the positive direction, reducing the light absorption of the N electrode and increasing the brightness;
(2)现有技术在芯粒侧面通过沉积或者模制颗粒,即引入了异质材料,而本发明是在发光二极管的倾斜侧面形成纳米微结构,与芯片材料同质,不会由于引入其他材料造成漏电或者ESD爆点。(2) In the prior art, heterogeneous materials are introduced by depositing or molding particles on the side of the core particle, while the present invention forms a nano-microstructure on the inclined side of the light-emitting diode, which is homogeneous with the chip material and will not be caused by the introduction of other materials. The material causes electric leakage or ESD explosion point.
本发明的其它特征和优点将在随后的说明书中阐述,并且,部分地从说明书中变得显而易见,或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
附图说明Description of drawings
附图用来提供对本发明的进一步理解,并且构成说明书的一部分,与本发明的实施例一起用于解释本发明,并不构成对本发明的限制。此外,附图数据是描述概要,不是按比例绘制。The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, and are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In addition, the drawing data are descriptive summaries and are not drawn to scale.
图1为现有的具有倾斜侧面的LED结构示意图。FIG. 1 is a schematic structural diagram of a conventional LED with inclined sides.
图2为根据本发明实施例1的一种发光二极管的制作方法流程图。FIG. 2 is a flowchart of a method for manufacturing a light emitting diode according to Embodiment 1 of the present invention.
图3~8为根据本发明实施例1的一种发光二极管的制作过程。3-8 are the manufacturing process of a light emitting diode according to Embodiment 1 of the present invention.
图9为根据本发明实施例2的一种发光二极管的制作方法流程图。FIG. 9 is a flow chart of a method for manufacturing a light emitting diode according to Embodiment 2 of the present invention.
图10~15为根据本发明实施例2的一种发光二极管的制作过程。10-15 are the manufacturing process of a light emitting diode according to Embodiment 2 of the present invention.
图中各标号表示如下:The symbols in the figure are as follows:
100:磊晶片;101:衬底;102:N型半导体层;103:发光层;104:P型半导体层;200:金属Ni层;201:金属Ni颗粒;205:纳米微结构;300:掩膜层;400:绝缘保护层。100: Epiwafer; 101: Substrate; 102: N-type semiconductor layer; 103: Light-emitting layer; 104: P-type semiconductor layer; 200: Metal Ni layer; 201: Metal Ni particles; 205: Nano microstructure; 300: Mask Film layer; 400: insulation protection layer.
具体实施方式Detailed ways
下面将结合实施例和附图对本发明的具体实施方式作详细说明。The specific implementation of the present invention will be described in detail below in conjunction with the embodiments and the accompanying drawings.
实施例1Example 1
如图2所示,公开了一种制作发光二极管的流程图,包括步骤S101~S105,包括:提供一磊晶片,并沉积一金属Ni层;将所述金属Ni层图案化,定义P型半导体区域上的金属Ni层保留,N型半导体区域上的金属Ni层去除;将具图案化金属Ni层的磊晶片进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布;在金属Ni颗粒上形成掩膜层;以金属Ni颗粒及掩膜层作为掩膜结构,进行蚀刻工艺,先进行第一步蚀刻,使得掩膜层内缩,然后再进行第二步蚀刻,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构。下面对各步骤进行进展开说明。As shown in Fig. 2, a flow chart of manufacturing a light-emitting diode is disclosed, including steps S101 to S105, including: providing an epitaxial wafer and depositing a metal Ni layer; patterning the metal Ni layer to define a P-type semiconductor The metal Ni layer on the region remains, and the metal Ni layer on the N-type semiconductor region is removed; the epiwafer with the patterned metal Ni layer is annealed, and after annealing, the metal Ni layer presents a granular distribution on the epiwafer; A mask layer is formed on the Ni particles; the metal Ni particles and the mask layer are used as the mask structure to carry out the etching process, and the first step of etching is performed to make the mask layer retract, and then the second step of etching is performed to obtain a The light-emitting diodes on the surface, and the inclined surface forms nano-microstructures. The progress of each step is described below.
步骤S101:如图3所示,提供一磊晶片100,该磊晶片包括衬底101和磊晶层,该磊晶层包括N型半导体层101、发光层102和P型半导体层103;在该磊晶片100上沉积金属Ni层200,厚度介于3~200nm之间,沉积方法可以采用蒸镀或者溅镀或者原子层沉积或者其他镀膜方法,本实施例优选蒸镀方法。Step S101: As shown in FIG. 3, an epitaxial wafer 100 is provided, the epitaxial wafer includes a substrate 101 and an epitaxial layer, and the epitaxial layer includes an N-type semiconductor layer 101, a light-emitting layer 102, and a P-type semiconductor layer 103; The metal Ni layer 200 is deposited on the epiwafer 100 with a thickness between 3-200 nm. The deposition method can be vapor deposition or sputtering or atomic layer deposition or other coating methods. The vapor deposition method is preferred in this embodiment.
步骤S102:如图4所示,将金属Ni层200图案化,定义P型半导体区域上的金属Ni层保留,N型半导体区域上的金属Ni层去除,该P型半导体区域用于后续制作P电极,N型半导体区域用于后续制作N电极。Step S102: As shown in FIG. 4, the metal Ni layer 200 is patterned to define that the metal Ni layer on the P-type semiconductor region is retained, and the metal Ni layer on the N-type semiconductor region is removed. The P-type semiconductor region is used for subsequent fabrication of P The electrode, the N-type semiconductor region is used for subsequent fabrication of the N electrode.
步骤S103:如图5所示,将具图案化金属Ni层201的磊晶片100进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布,退火处理的条件包括:温度为500~800℃,时间为0.5~10min,气氛为N2:25~95L。Step S103: As shown in FIG. 5, the epiwafer 100 with the patterned metal Ni layer 201 is subjected to annealing treatment. After annealing, the metal Ni layer presents a granular distribution on the epiwafer. The annealing treatment conditions include: the temperature is 500~ 800°C, the time is 0.5~10min, the atmosphere is N 2 : 25~95L.
步骤S104:如图6所示,在金属Ni颗粒201上形成掩膜层300,掩膜层的面积与金属Ni颗粒相当,掩膜层的材料可以选用光阻或氧化物或金属,本实施例优选光阻作为掩膜层,光阻厚度可为0.5~3μm,运用黄光制程制作出由柱状光阻构成的图形,此过程可采用步进式曝光机、接触式曝光机、投影式曝光机或压印方式。Step S104: As shown in FIG. 6, a mask layer 300 is formed on the metal Ni particles 201. The area of the mask layer is equivalent to that of the metal Ni particles. The material of the mask layer can be photoresist, oxide or metal. In this embodiment The photoresist is preferably used as the mask layer, the thickness of the photoresist can be 0.5~3μm, and the pattern composed of columnar photoresist is produced by using the yellow light process. This process can use a stepper exposure machine, a contact exposure machine, and a projection exposure machine. or embossing method.
步骤S105:如图7所示,以金属Ni颗粒201及掩膜层300作为掩膜结构,进行感应耦合等离子体蚀刻工艺,先进行第一步干法蚀刻,使得掩膜层内缩0.1~1μm,第一步干法蚀刻工艺,参数包括:通入氧气100~200sccm,上电极功率:1000~2000W,下电极功率:0~50W,时间:20~200s;然后如图8所示,再进行第二步干法蚀刻,使得磊晶层形成具有纳米微结构205的倾斜面且裸露出部分N型半导体层102,蚀刻工艺参数包括:通入三氯化硼5~50sccm,通入氯气60~180sccm,上电极功率:150~500W,下电极功率:50~500W,时间:300~600s,最后分别在P型半导体层104和裸露的N型半导体层102上制作P电极600和N电极500,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构105,如图8所示。Step S105: As shown in FIG. 7 , the metal Ni particles 201 and the mask layer 300 are used as the mask structure, and the inductively coupled plasma etching process is performed, and the first step of dry etching is performed first, so that the mask layer shrinks inward by 0.1-1 μm , the first step of dry etching process, the parameters include: oxygen 100~200sccm, upper electrode power: 1000~2000W, lower electrode power: 0~50W, time: 20~200s; then as shown in Figure 8, proceed The second step is dry etching, so that the epitaxial layer forms an inclined surface with nano-microstructure 205 and exposes part of the N-type semiconductor layer 102. The etching process parameters include: feeding boron trichloride 5~50 sccm, feeding chlorine gas 60~ 180sccm, upper electrode power: 150~500W, lower electrode power: 50~500W, time: 300~600s, finally make P electrode 600 and N electrode 500 on P type semiconductor layer 104 and exposed N type semiconductor layer 102 respectively, A light emitting diode with an inclined surface is obtained, and the inclined surface forms a nanostructure 105, as shown in FIG. 8 .
实施例2Example 2
如图9所示,公开了另一种制作发光二极管的流程图,包括步骤S201~S205,包括:提供一磊晶片,并沉积一金属Ni层;将具金属Ni层的磊晶片进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布;将所述金属Ni颗粒图案化,定义P型半导体区域上的金属Ni颗粒保留,N型半导体区域上的金属Ni颗粒去除;在所述金属Ni颗粒上形成掩膜层;以所述金属Ni颗粒及掩膜层作为掩膜结构,进行蚀刻工艺,先进行第一步蚀刻,使得掩膜层内缩,然后再进行第二步蚀刻,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构。下面对各步骤进行进展开说明。As shown in FIG. 9, another flow chart for manufacturing a light-emitting diode is disclosed, including steps S201 to S205, including: providing an epitaxial wafer and depositing a metal Ni layer; annealing the epitaxial wafer with the metal Ni layer, After annealing, the metal Ni layer presents a granular distribution on the epiwafer; the metal Ni particles are patterned to define that the metal Ni particles on the P-type semiconductor region are retained, and the metal Ni particles on the N-type semiconductor region are removed; A mask layer is formed on the metal Ni particles; the metal Ni particles and the mask layer are used as a mask structure to carry out an etching process, and the first step of etching is first performed to shrink the mask layer, and then the second step of etching is performed, A light-emitting diode with an inclined surface is obtained, and the inclined surface forms a nanometer structure. The progress of each step is described below.
步骤S201:如图10所示,提供一磊晶片100,该磊晶片包括衬底101和磊晶层,该磊晶层包括N型半导体层101、发光层102和P型半导体层103;在该磊晶片100上沉积金属Ni层200,厚度介于3~200nm之间,沉积方法可以采用蒸镀或者溅镀或者原子层沉积或者其他镀膜方法,本实施例优选溅镀方法。Step S201: As shown in FIG. 10, an epitaxial wafer 100 is provided, the epitaxial wafer includes a substrate 101 and an epitaxial layer, and the epitaxial layer includes an N-type semiconductor layer 101, a light-emitting layer 102, and a P-type semiconductor layer 103; A metal Ni layer 200 is deposited on the epiwafer 100 with a thickness between 3-200 nm. The deposition method can be vapor deposition, sputtering, atomic layer deposition or other coating methods. The sputtering method is preferred in this embodiment.
步骤S202:如图11所示,将具金属Ni层的磊晶片201的磊晶片100进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布,退火处理的条件包括:温度为500~800℃,时间为0.5~10min,气氛为N2:25~95L。Step S202: As shown in FIG. 11 , the epiwafer 100 of the epiwafer 201 with the metal Ni layer is annealed. After annealing, the metal Ni layer presents a granular distribution on the epiwafer. The annealing conditions include: the temperature is 500 ~800℃, the time is 0.5~10min, the atmosphere is N 2 : 25~95L.
步骤S203:如图12所示,将金属Ni颗粒201图案化,定义P型半导体区域上的金属Ni颗粒保留,N型半导体区域上的金属Ni颗粒去除,该P型半导体区域用于后续制作P电极,N型半导体区域用于后续制作N电极。Step S203: As shown in Figure 12, pattern the metal Ni particles 201, define the metal Ni particles on the P-type semiconductor region to be retained, and the metal Ni particles on the N-type semiconductor region to be removed, and the P-type semiconductor region is used for subsequent manufacturing of P The electrode, the N-type semiconductor region is used for subsequent fabrication of the N electrode.
步骤S204:如图13所示,在金属Ni颗粒201上先沉积一绝缘保护层400,再形成掩膜层300。该绝缘保护层400可以选用SiO2或SiN或Al2O3,本实施例优选化学气相沉积(CVD)10~30nm厚度的SiO2形成,绝缘保护层的面积与磊晶层相当(面积大于金属Ni颗粒),用于保护位于N型半导体区域的磊晶层在步骤S205蚀刻工艺中不被先蚀刻,作为缓冲作用;该掩膜层300的面积与金属Ni颗粒相当,掩膜层的材料可以选用光阻或氧化物或金属,本实施例优选光阻作为掩膜层,光阻厚度可为0.5μm~3μm,运用黄光制程制作出由柱状光阻构成的图形,此过程可采用步进式曝光机、接触式曝光机、投影式曝光机或压印方式。Step S204 : as shown in FIG. 13 , first deposit an insulating protection layer 400 on the metal Ni particles 201 , and then form a mask layer 300 . The insulating protective layer 400 can be made of SiO 2 or SiN or Al 2 O 3 . In this embodiment, SiO 2 with a thickness of 10-30 nm is preferably formed by chemical vapor deposition (CVD). Ni particles), used to protect the epitaxial layer located in the N-type semiconductor region from being etched first in the step S205 etching process, as a buffer; the area of the mask layer 300 is equivalent to the metal Ni particles, and the material of the mask layer can be Use photoresist or oxide or metal. In this embodiment, photoresist is preferred as the mask layer. The thickness of the photoresist can be 0.5 μm to 3 μm. Exposure machine, contact exposure machine, projection exposure machine or embossing method.
步骤S205:如图14所示,以金属Ni颗粒201、绝缘保护层400及掩膜层300作为掩膜结构,进行感应耦合等离子体蚀刻工艺,先进行第一步干法蚀刻,使得绝缘保护层、掩膜层的单边尺寸相对于金属Ni颗粒均向内缩0.1~1μm,第一步干法蚀刻工艺,包括:通入四氟化碳50~300sccm,通入氧气5~200sccm,上电极功率:150~900W,下电极功率:50~400W,时间:20~200s;然后如图15所示,再进行第二步干法蚀刻,使得磊晶层形成具有纳米微结构205的倾斜面且裸露出部分N型半导体层102,蚀刻工艺参数包括:通入三氯化硼5~50sccm,通入氯气60~180sccm,上电极功率:150~500W,下电极功率:50~500W,时间:300~600s,最后分别在P型半导体层104和裸露的N型半导体层102上制作P电极600和N电极500,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构105,如图15所示。Step S205: As shown in FIG. 14, the metal Ni particles 201, the insulating protective layer 400 and the mask layer 300 are used as the mask structure to perform an inductively coupled plasma etching process, and the first step of dry etching is performed first, so that the insulating protective layer 1. The unilateral size of the mask layer is shrunk inward by 0.1~1μm relative to the metal Ni particles. The first step of the dry etching process includes: introducing carbon tetrafluoride 50~300sccm, oxygen 5~200sccm, and the upper electrode Power: 150~900W, lower electrode power: 50~400W, time: 20~200s; then, as shown in Figure 15, the second step of dry etching is carried out, so that the epitaxial layer forms an inclined surface with nano-microstructure 205 and Part of the N-type semiconductor layer 102 is exposed, and the etching process parameters include: boron trichloride 5~50 sccm, chlorine gas 60~180 sccm, upper electrode power: 150~500W, lower electrode power: 50~500W, time: 300 ~600s, finally make P-electrode 600 and N-electrode 500 respectively on P-type semiconductor layer 104 and exposed N-type semiconductor layer 102, obtain light-emitting diode with inclined surface, and the inclined surface forms nano-microstructure 105, as shown in Figure 15 Show.
实施例3Example 3
本实施例的公开了再一种制作发光二极管的制作方法,包括工艺步骤:This embodiment discloses yet another method for manufacturing a light-emitting diode, including process steps:
(1)提供一磊晶片,并沉积一金属Ni层;(1) Provide an epitaxial wafer, and deposit a metal Ni layer;
(2)将所述金属Ni层图案化,定义P型半导体区域上的金属Ni层保留,N型半导体区域上的金属Ni层去除;(2) Patterning the metal Ni layer, defining that the metal Ni layer on the P-type semiconductor region is retained, and the metal Ni layer on the N-type semiconductor region is removed;
(3)将具图案化金属Ni层的磊晶片进行退火处理,退火后,金属Ni层在磊晶片上呈现颗粒状分布;(3) Annealing the epiwafer with the patterned metal Ni layer, after annealing, the metal Ni layer presents a granular distribution on the epiwafer;
(4)在所述金属Ni颗粒上形成掩膜层,并采用湿法蚀刻,使得掩膜层内缩;(4) forming a mask layer on the metal Ni particles, and using wet etching to shrink the mask layer;
(5)以所述金属Ni颗粒及掩膜层作为掩膜结构,进行感应耦合等离子体蚀刻,得到具有倾斜表面的发光二极管,且倾斜表面形成纳米微结构。(5) Using the metal Ni particles and the mask layer as a mask structure, performing inductively coupled plasma etching to obtain a light emitting diode with an inclined surface, and the inclined surface forms a nano-microstructure.
本实施例与实施例1的区别在于:实施例1的步骤S105中的位于金属Ni颗粒之上的掩膜层内缩是通过干法蚀刻工艺完成,而本实施的掩膜层内缩是通过湿法蚀刻工艺完成。本实施例的掩膜层内缩采用湿法蚀刻工艺成本较低,工艺条件简单,便于生产操作;而实施例1中掩膜层内缩采用干法蚀刻工艺便于控制相关尺寸的均匀性。The difference between this embodiment and Embodiment 1 is that the retraction of the mask layer above the metal Ni particles in step S105 of Embodiment 1 is accomplished by a dry etching process, while the retraction of the mask layer in this embodiment is achieved by The wet etching process is completed. In this embodiment, the shrinkage of the mask layer adopts a wet etching process with low cost, simple process conditions, and is convenient for production operation; while the dry etching process is used for the shrinkage of the mask layer in Embodiment 1 to facilitate the control of the uniformity of related dimensions.
综上所述,本发明是利用金属颗粒和掩膜层作为掩膜结构,在制作P型半导体区域和N型半导体区域的同时,在芯粒倾斜表面形成纳米微结构。与现有技术相比,具有以下技术优势:To sum up, the present invention uses metal particles and a mask layer as a mask structure to form nano-microstructures on the inclined surface of core grains while making P-type semiconductor regions and N-type semiconductor regions. Compared with the existing technology, it has the following technical advantages:
(1)充分利用现有产线的技术条件及材料,不会引入新的工艺步骤及新材料;(1) Make full use of the technical conditions and materials of the existing production line, and will not introduce new process steps and new materials;
(2)芯粒倾斜表面形成纳米微颗粒与外延层同质,避免造成侧面P型半导体层、发光层和P型半导体层连通,最后短路,造成漏电或者ESD爆点;(2) Nano particles formed on the inclined surface of the core particle are homogeneous with the epitaxial layer, so as to avoid the connection between the side P-type semiconductor layer, the light-emitting layer and the P-type semiconductor layer, and finally short circuit, resulting in leakage or ESD explosion point;
(3)不仅在LED芯粒的发光区周围设置有纳米微结构,同时由于该纳米微结构位于N电极周围,避免了N金属电极对光的吸收。(3) Not only is the nano-microstructure arranged around the light-emitting area of the LED core particle, but at the same time, since the nano-microstructure is located around the N electrode, the absorption of light by the N metal electrode is avoided.
应当理解的是,上述具体实施方案仅为本发明的部分优选实施例,以上实施例还可以进行各种组合、变形。本发明的范围不限于以上实施例,凡依本发明所做的任何变更,皆属本发明的保护范围之内。It should be understood that the above specific embodiments are only some preferred embodiments of the present invention, and various combinations and modifications can be made to the above embodiments. The scope of the present invention is not limited to the above embodiments, and any changes made according to the present invention are within the protection scope of the present invention.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610809998.9A CN106206898B (en) | 2016-09-08 | 2016-09-08 | A kind of production method of light emitting diode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610809998.9A CN106206898B (en) | 2016-09-08 | 2016-09-08 | A kind of production method of light emitting diode |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106206898A CN106206898A (en) | 2016-12-07 |
CN106206898B true CN106206898B (en) | 2018-07-06 |
Family
ID=58067299
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610809998.9A Active CN106206898B (en) | 2016-09-08 | 2016-09-08 | A kind of production method of light emitting diode |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106206898B (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102306623A (en) * | 2011-09-23 | 2012-01-04 | 厦门市三安光电科技有限公司 | Method for preparing nanoscale silica graphic mask layer |
CN102983235A (en) * | 2012-12-11 | 2013-03-20 | 映瑞光电科技(上海)有限公司 | Manufacturing method of nanoscale patterned substrate |
CN103053034A (en) * | 2010-08-02 | 2013-04-17 | 光州科学技术院 | Method for preparing anti-reflection nanostructure and method for preparing optical device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06310428A (en) * | 1993-04-26 | 1994-11-04 | Matsushita Electric Ind Co Ltd | Manufacture of quantum box |
KR100682877B1 (en) * | 2005-07-12 | 2007-02-15 | 삼성전기주식회사 | Light emitting diode and manufacturing method |
KR101047639B1 (en) * | 2010-04-19 | 2011-07-07 | 엘지이노텍 주식회사 | Method of manufacturing semiconductor light emitting device, light emitting device package and semiconductor light emitting device |
KR101729263B1 (en) * | 2010-05-24 | 2017-04-21 | 엘지이노텍 주식회사 | Light emitting device, method for fabricating the light emitting device and light emitting device package |
TWI488336B (en) * | 2012-06-07 | 2015-06-11 | Lextar Electronics Corp | Light-emitting diode and manufacturing method thereof |
-
2016
- 2016-09-08 CN CN201610809998.9A patent/CN106206898B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103053034A (en) * | 2010-08-02 | 2013-04-17 | 光州科学技术院 | Method for preparing anti-reflection nanostructure and method for preparing optical device |
CN102306623A (en) * | 2011-09-23 | 2012-01-04 | 厦门市三安光电科技有限公司 | Method for preparing nanoscale silica graphic mask layer |
CN102983235A (en) * | 2012-12-11 | 2013-03-20 | 映瑞光电科技(上海)有限公司 | Manufacturing method of nanoscale patterned substrate |
Also Published As
Publication number | Publication date |
---|---|
CN106206898A (en) | 2016-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106025012A (en) | Preparation method of LED chip and LED chip prepared by adopting method | |
JP5584845B1 (en) | SOLAR CELL, MANUFACTURING METHOD THEREOF, AND SOLAR CELL MODULE | |
CN106409994A (en) | AlGaInP-based light-emitting diode chip and manufacturing method thereof | |
CN106784192A (en) | A kind of light-emitting diode chip for backlight unit and preparation method thereof | |
CN107464868A (en) | A kind of preparation method of high voltage LED chip | |
CN105140354A (en) | Preparation method of GaN-based light-emitting diode chip | |
CN103972423B (en) | A kind of OLED light-emitting device and its preparation method, display device | |
CN106058003B (en) | A method of promoting LED chip brightness | |
CN107331736A (en) | LED component and its manufacture method having improved properties | |
CN107026221A (en) | LED chip with high brightness and preparation method thereof | |
CN102122686A (en) | Method for manufacturing light-emitting diode | |
CN106206898B (en) | A kind of production method of light emitting diode | |
CN214336736U (en) | LED chip structure of double-layer ITO film | |
CN102832297A (en) | Preparation methods of semiconductor light emitting device and current diffusion layer | |
JP6301353B2 (en) | Light emitting device with improved internal outcoupling and method for supplying said light emitting device | |
JP2017216280A (en) | Group iii nitride semiconductor light-emitting device and method for manufacturing the same | |
CN214336733U (en) | LED chip structure for ALD deposition of current expansion layer | |
CN106887496B (en) | A kind of production method of light emitting diode | |
CN215377431U (en) | Light emitting diode chip structure and light emitting diode | |
CN114709312A (en) | LED chip and preparation method thereof | |
WO2020238430A1 (en) | Photodiode device, array substrate and manufacturing method therefor, display panel and display apparatus | |
CN103311379B (en) | A kind of GaN base LED and the method manufacturing GaN base LED | |
KR100871649B1 (en) | Sapphire substrate patterning method of light emitting diode | |
CN102456788B (en) | Light emitting diode and manufacturing method thereof | |
CN112366254B (en) | LED chip preparation method and LED chip thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20231025 Address after: Yuanqian village, Shijing Town, Nan'an City, Quanzhou City, Fujian Province Patentee after: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY Co.,Ltd. Address before: No. 1721 Lvling Road, Siming District, Xiamen City, Fujian Province, 361003 Patentee before: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |
|
TR01 | Transfer of patent right |