CN106206588B - non-volatile memory - Google Patents

Abstract

The present invention provides a non-volatile memory having a memory cell. The memory cell has a stacking structure, a first and a second floating gate, an erase gate dielectric layer, an auxiliary gate dielectric layer, a first and a second doping region, and a first and a second control gate. The stacking structure has a gate dielectric layer, an auxiliary gate, an insulating layer and an erase gate arranged in sequence. The first and the second floating gates are respectively arranged on the side walls of both sides of the stacking structure. The erase gate dielectric layer is arranged between the erase gate and the first and the second floating gates. The auxiliary gate dielectric layer is arranged between the auxiliary gate and the first and the second floating gates. The first and the second doping regions are respectively arranged on both sides of the stacking structure and the first and the second floating gates. The first and the second control gates are respectively arranged on the first and the second floating gates. The present invention can operate at a low operating voltage, thereby increasing the reliability of the semiconductor element.

Description

non-volatile memory

technical field

The invention relates to a semiconductor element, in particular to a nonvolatile memory.

Background technique

Non-volatile memory has been widely used in personal computers and electronic devices due to its advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear after power failure.

A typical non-volatile memory is designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a floating gate (Floating gate), and an inter-gate dielectric that are sequentially arranged on the substrate. layer and control gate (Control Gate). When programming or erasing the flash memory device, appropriate voltages are applied to the source region, the drain region, and the control gate, so that electrons are injected into the polysilicon floating gate, or electrons are removed from the polysilicon floating gate. Set the gate to pull out.

In the operation of non-volatile memory, generally the greater the Gate-Coupling Ratio (GCR) between the floating gate and the control gate is, the lower the operating voltage required for its operation will be. The operation speed and efficiency of the flash memory will be greatly improved. The method of increasing the gate coupling ratio includes increasing the overlap area (Overlap Area) between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the floating gate. The dielectric constant (Dielectric Constant; k) of the inter-gate dielectric layer between the gate and the control gate, etc.

However, as integrated circuits are developing towards miniaturized devices with higher integration, it is necessary to reduce the size of memory cells of non-volatile memories to increase their integration. Wherein, reducing the size of the memory cell can be achieved by reducing the length of the gate of the memory cell and the distance between the bit lines. However, the shortening of the gate length will shorten the channel length (Channel Length) under the tunnel oxide layer, which will easily cause abnormal electrical penetration (Punch Through) between the drain and the source, which will seriously affect the memory cell. electrical performance. Moreover, when programming and/or erasing the memory cell, electrons repeatedly pass through the tunnel oxide layer, which will wear out the tunnel oxide layer, resulting in reduced reliability of the memory element.

Contents of the invention

The invention provides a non-volatile memory which can be operated at a low operating voltage, thereby increasing the reliability of semiconductor elements.

The invention provides a non-volatile memory, which can increase the accumulation degree of components.

The invention provides a non-volatile memory, which has a first storage unit arranged on a substrate. The first memory unit includes: a stack structure, a first floating gate and a second floating gate, a first tunneling dielectric layer and a second tunneling dielectric layer, a first erasing gate dielectric layer and a second tunneling dielectric layer Two erasing gate dielectric layers, the first auxiliary gate dielectric layer and the second auxiliary gate dielectric layer, the first doped region and the second doped region, the first control gate and the second control gate, and the inter-gate dielectric layer. The stack structure includes a gate dielectric layer, an auxiliary gate, an insulating layer and an erasing gate sequentially arranged on the substrate. The first floating gate and the second floating gate are respectively arranged on the sidewalls on both sides of the stack structure, and the tops of the first floating gate and the second floating gate respectively have corners, and the corners are adjacent to the wipers. The gate is removed, and the height of the corner part falls between the heights of the erasing gate. The first tunnel dielectric layer and the second tunnel dielectric layer are respectively disposed between the first floating gate and the substrate and between the second floating gate and the substrate. The first erasing gate dielectric layer and the second erasing gate dielectric layer are respectively disposed between the erasing gate and the first floating gate and between the erasing gate and the second floating gate. The first auxiliary gate dielectric layer and the second auxiliary gate dielectric layer are respectively disposed between the auxiliary gate and the first floating gate and between the auxiliary gate and the second floating gate. The first doped region and the second doped region are respectively arranged in the substrate, wherein the first floating gate, the stack structure and the second floating gate are connected and arranged between the first doped region and the second doped region on the base of the room. The first control gate and the second control gate are respectively disposed on the first floating gate and the second floating gate. The inter-gate dielectric layer is disposed between the first control gate and the first floating gate and between the second control gate and the second floating gate.

In an embodiment of the present invention, the non-volatile memory has a first bit line and a second bit line. The first bit line and the second bit line are arranged on the substrate in parallel, wherein the first doped region is electrically connected to the first bit line, and the second doped region is electrically connected to the second bit line.

In an embodiment of the present invention, the above-mentioned non-volatile memory further includes a second storage unit in the row direction, the second storage unit is arranged on the substrate, the structure of the second storage unit is the same as that of the first storage unit, and shares the second doped region.

In an embodiment of the present invention, the non-volatile memory has a first bit line and a second bit line. The first bit line and the second bit line are arranged on the substrate in parallel, wherein the second doped region shared by the first memory unit and the second memory unit is electrically connected to the first bit line, and the first doped region of the first memory unit The region and the third doped region of the second memory unit are respectively electrically connected to the second bit line.

In an embodiment of the present invention, the first storage unit and the second storage unit share the first control gate or the second control gate, and the first control gate or the second control gate fills the first storage unit and the opening between the second storage unit.

In an embodiment of the present invention, the above-mentioned non-volatile memory further includes a third storage unit in the column direction, the third storage unit is arranged on the substrate, the structure of the third storage unit is the same as that of the first storage unit, The third storage unit and the first storage unit are connected in series through the first doped region, share the auxiliary gate, the erase gate, the first control gate and the second control gate, and the first control gate and the second control gate The two control gates fill the space between the first storage unit and the third storage unit.

In an embodiment of the present invention, the non-volatile memory has a first bit line, a second bit line and a third bit line. The first bit line, the second bit line and the third bit line are arranged in parallel on the substrate, wherein the first doped region connecting the first memory unit and the third memory unit in series is electrically connected to the second bit line, and the first The second doped region of the memory unit is electrically connected to the first bit line, and the third doped region of the third memory unit is electrically connected to the third bit line.

In an embodiment of the present invention, the above-mentioned first tunneling dielectric layer is also arranged between the first control gate and the first doped region; the second tunneling dielectric layer is also arranged between the second control gate and the first doped region. between the second doped regions.

In an embodiment of the present invention, the thicknesses of the first auxiliary gate dielectric layer and the second auxiliary gate dielectric layer are greater than or equal to the thicknesses of the first erasing gate dielectric layer and the second erasing gate dielectric layer.

In an embodiment of the present invention, the material of the first auxiliary gate dielectric layer and the second auxiliary gate dielectric layer includes silicon oxide/silicon nitride, silicon oxide/silicon nitride/silicon oxide or silicon oxide.

In an embodiment of the present invention, the insulating layer is made of silicon oxide.

In an embodiment of the present invention, the material of the inter-gate dielectric layer includes silicon oxide/silicon nitride/silicon oxide or silicon nitride/silicon oxide or other high dielectric constant materials (k>4).

In an embodiment of the present invention, the material of the first tunneling dielectric layer and the second tunneling dielectric layer includes silicon oxide, and the thicknesses of the first tunneling dielectric layer and the second tunneling dielectric layer are between Between 60 Angstroms and 200 Angstroms.

In an embodiment of the present invention, the material of the gate dielectric layer includes silicon oxide, and the thickness of the gate dielectric layer is less than or equal to the thickness of the first tunnel dielectric layer and the second tunnel dielectric layer.

In an embodiment of the present invention, the material of the first erasing gate dielectric layer and the second erasing gate dielectric layer includes silicon oxide, and the first erasing gate dielectric layer and the second erasing gate dielectric layer The thickness is between 100 angstroms and 180 angstroms.

In an embodiment of the present invention, the above-mentioned corner angle is less than or equal to 90 degrees. The threshold voltage of the first memory cell after being programmed is between Vcc and 0: the threshold voltage of the first memory cell after being erased is less than 0.

In the nonvolatile memory of the present invention, two adjacent memory cells in the X direction (row direction) have the same structure and share the first doped region or the second doped region. The two adjacent memory cells in the Y direction (column direction) have the same structure, sharing the first doped region or the second doped region, the auxiliary gate (word line), the erasing gate and the control gate. Therefore, the integration degree of components can be improved.

In the non-volatile memory of the present invention, the auxiliary gate and the erasing gate are arranged in parallel, so the integration of elements can be improved.

In the nonvolatile memory of the present invention, the thickness of the gate dielectric layer under the auxiliary gate is relatively thin, and when operating the memory cell, a smaller voltage can be used to open/close the channel region under the auxiliary gate, that is, it can Reduce operating voltage.

In the non-volatile memory of the present invention, the control gate covers the floating gate, which can increase the area between the control gate and the floating gate, thereby improving the coupling rate of the memory element.

In the nonvolatile memory of the present invention, since the floating gate is provided with a corner portion between the heights of the erasing gate, and the angle of the corner portion is less than or equal to 90 degrees, the electric field is concentrated through the corner portion, which can reduce the erasure. Voltage, efficiently pulls electrons from the floating gate, increasing the speed of erasing data.

In the nonvolatile memory of the present invention, since there is no gap between the first floating gate, the stacked structure and the second floating gate, the accumulation degree of the memory cells can be improved. Moreover, charge can be stored in both the first floating gate and the second floating gate, so two bits of data can be stored in a single memory cell, thereby increasing the storage capacity.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a top view of a non-volatile memory shown in an embodiment of the present invention;

FIG. 1B is a schematic cross-sectional view of a non-volatile memory shown in an embodiment of the present invention;

FIG. 1C is a schematic circuit diagram of a non-volatile memory shown in an embodiment of the present invention;

FIG. 2A and FIG. 2B are schematic diagrams of an example of programming operations on memory cells;

2C and 2D are schematic diagrams of an example of performing an erase operation on a memory cell;

2E and 2F are schematic diagrams of an example of performing a read operation on a memory cell;

FIG. 3A is a top view of a non-volatile memory shown in an embodiment of the present invention;

3B is a schematic cross-sectional view of a non-volatile memory shown in an embodiment of the present invention;

FIG. 3C is a schematic circuit diagram of a non-volatile memory shown in an embodiment of the present invention;

4A and FIG. 4B are schematic diagrams of an example of a programming operation on a memory cell;

4C and 4D are schematic diagrams of an example of performing an erase operation on a memory cell;

4E and 4F are schematic diagrams of an example of a read operation on a memory cell.

Explanation of reference signs:

100: base;

102: isolation structure;

104: active zone;

118: top cover layer;

120: stacking structure;

122: gate dielectric layer;

124: auxiliary grid;

126, 166: insulating layer;

128: erase grid;

130a, 130b: auxiliary gate dielectric layer;

132a, 132b: erasing the gate dielectric layer;

140a, 140b, FGa, FGb: floating gates;

141: corner part;

142a, 142b: tunneling dielectric layer;

146, 148: doped regions;

150a, 150b: control grid;

152: inter-gate dielectric layer;

162: plug;

164: opening;

BL0～BL3: bit lines;

CG0～CG5: control gate lines;

EG0～EG2: erase lines;

M, M11~M33: storage unit;

WL0~WL2: character lines.

Detailed ways

FIG. 1A is a top view of a non-volatile memory shown in an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the present invention. FIG. 1B shows a cross-sectional view along line AA' in FIG. 1A. FIG. 1C is a schematic circuit diagram of a non-volatile memory shown in an embodiment of the present invention.

Please refer to FIG. 1A, FIG. 1B and FIG. 1C. The non-volatile memory includes a plurality of memory cells M11-M33, word lines WL0-WL2, erase lines EG0-EG2, bit lines BL0-BL3, control gate lines CG0- CG5. The memory cells M11-M33 are arranged in a row/column array.

A nonvolatile memory is provided on the substrate 100 . For example, an isolation structure 102 is disposed in the substrate 100 to define an active region 104 . The isolation structure 102 is, for example, a shallow trench isolation structure.

As shown in FIG. 1B, the memory cell M includes a stack structure 120, an auxiliary gate dielectric layer 130a (130b), an erasing gate dielectric layer 132a (132b), a floating gate 140a (140b), and a tunneling dielectric layer 142a. ( 142 b ), doped region 146 , doped region 148 , control gate 150 a ( 150 b ), and inter-gate dielectric layer 152 .

The stack structure 120 is sequentially composed of a gate dielectric layer 122 , an auxiliary gate 124 , an insulating layer 126 and an erasing gate 128 from the substrate 100 . The gate dielectric layer 122 is, for example, disposed between the auxiliary gate 124 and the substrate 100 . The material of the gate dielectric layer 122 is, for example, silicon oxide. The thickness of the gate dielectric layer 122 is, for example, smaller than or equal to the thickness of the tunnel dielectric layer 142 .

The auxiliary gate 124 is, for example, disposed between the gate dielectric layer 122 and the insulating layer 126 . The erase gate 128 is, for example, disposed on the insulating layer 126 . The auxiliary gate 124 and the erasing gate 128 extend in the Y direction, for example. The materials of the auxiliary gate 124 and the erasing gate 128 are, for example, conductive materials such as doped polysilicon. The insulating layer 126 is, for example, disposed between the auxiliary gate 124 and the erase gate 128 . The material of the insulating layer 126 is, for example, silicon oxide. A capping layer 118 can be optionally disposed on the erasing gate 128 , and the material of the capping layer 118 is, for example, silicon oxide or silicon nitride.

The auxiliary gate dielectric layer 130 a ( 130 b ), for example, is disposed between the floating gate 140 a ( 140 b ) and the auxiliary gate 124 . The material of the auxiliary gate dielectric layer 130 a ( 130 b ) is, for example, silicon oxide/silicon nitride/silicon oxide, silicon nitride/silicon oxide or silicon oxide. The thickness of the auxiliary gate dielectric layer 130a ( 130b ) is, for example, greater than or equal to the thickness of the erasing gate dielectric layer 132a ( 132b ). The erase gate dielectric layer 132 a ( 132 b ), for example, is disposed between the erase gate 128 and the floating gate 140 a ( 140 b ). The material of the erasing gate dielectric layer 132a ( 132b ) is, for example, silicon oxide. The thickness of the erase gate dielectric layer 132a ( 132b ) is, for example, between 100 angstroms and 180 angstroms.

The floating gate 140 a and the floating gate 140 b are, for example, disposed on sidewalls on both sides of the stack structure 120 , and the tops of the floating gate 140 a and the floating gate 140 b respectively have corner portions 141 . The corner portion 141 is adjacent to the erasing gate 128 , and the height of the corner portion 141 falls between the heights of the erasing gate 128 . The angle of the corner portion 141 is less than or equal to 90 degrees. The material of the floating gate 140 a and the floating gate 140 b is, for example, a conductive material such as doped polysilicon. The floating gate 140a and the floating gate 140b can be composed of one or more conductor layers respectively.

The tunnel dielectric layer 142 a is, for example, disposed between the floating gate 140 a and the substrate 100 ; the tunnel dielectric layer 142 b is, for example, disposed between the floating gate 140 b and the substrate 100 . The tunneling dielectric layer 142 a is further disposed between the control gate 150 a and the doped region 146 ; the tunneling dielectric layer 142 b is further disposed between the control gate 150 b and the doped region 148 , for example. The material of the tunneling dielectric layer 142 a and the tunneling dielectric layer 142 b is, for example, silicon oxide. The thickness of the tunneling dielectric layer 142a and the tunneling dielectric layer 142b is between 60 angstroms and 200 angstroms.

The doped region 146 is, for example, disposed in the substrate 100 beside the floating gate 140a. The doped region 148 is, for example, disposed in the substrate 100 beside the floating gate 140b. The floating gate 140 a , the stack structure 120 and the floating gate 140 b are connected and disposed on the substrate 100 between the doped region 146 and the doped region 148 . The doped region 146 and the doped region 148 are, for example, doped regions containing N-type or P-type dopants, depending on the design of the device.

The control gate 150a is, for example, disposed on the floating gate 140a; the control gate 150b is, for example, disposed on the floating gate 140b. The control gate 150a and the control gate 150b extend in the Y direction (column direction), for example. The material of the control gate 150 a and the control gate 150 b is, for example, a conductive material such as doped polysilicon. The inter-gate dielectric layer 152 is, for example, disposed between the control gate 150a and the floating gate 140a and between the control gate 150b and the floating gate 140b. The material of the inter-gate dielectric layer 152 is, for example, silicon oxide/silicon nitride/silicon oxide or silicon nitride/silicon oxide or other high dielectric constant materials (k>4).

An interlayer insulating layer (not shown) is disposed on the substrate 100 and covers the memory cells M, for example. The material of the interlayer insulating layer is, for example, silicon oxide, phosphosilicate glass, borophosphosilicate glass or other suitable dielectric materials. The plurality of plugs 162 are, for example, disposed in an interlayer insulating layer. The material of the plug 162 is, for example, conductive materials such as aluminum and tungsten. A plurality of bit lines BL0 - BL3 are disposed on the interlayer insulating layer, for example, and the bit lines BL0 - BL3 are respectively electrically connected to the doped regions 146 or 148 of the memory cells M through the plugs 162 . The material of the bit lines BL0 - BL3 is, for example, conductive materials such as aluminum, tungsten, and copper. As shown in FIG. 1C, the memory cells M11-M33 have the structures shown in FIGS. 1A and 1B. In the following description, the memory cell M in FIG. 1B is divided into a left bit a and a right bit b.

In the X direction (row direction), a plurality of memory cells M are connected in series through the doped region (the doped region 146 or the doped region 148 ). For example, the memory cell M11 has the same structure as the memory cell M12 and shares a doped region (doped region 146 or doped region 148); the memory cell M12 has the same structure as the memory cell M13 and shares a doped region. The impurity region (doped region 146 or doped region 148); ...; the structure of the memory cell M31 is the same as that of the memory cell M32, sharing one doped region (the doped region 146 or the doped region 148); the memory cell M32 The structure is the same as that of the memory cell M33, sharing one doped region (the doped region 146 or the doped region 148).

In the Y direction (column direction), a plurality of memory cells M are connected in series through the doped region (the doped region 146 or the doped region 148), and share the auxiliary gate 124, the erasing gate 128 and the control gate. 150a and control grid 150b. The control gate 150 a and the control gate 150 b fill up between the memory cells M (eg, the memory cell M11 , the memory cell M21 and the memory cell M31 ). For example, the memory cell M11 has the same structure as the memory cell M21 and shares a doped region (doped region 146 or doped region 148), and the memory cell M21 has the same structure as the memory cell M31 and shares a doped region. Region (doped region 146 or doped region 148); ...; the structure of the memory cell M13 is the same as that of the memory cell M23, sharing a doped region (doped region 146 or doped region 148), the structure of the memory cell M23 The same structure as the memory cell M33 shares a doped region (the doped region 146 or the doped region 148 ).

The bit lines BL0 to BL3 are respectively provided on the substrate, for example, and these bit lines BL0 to BL3 are arranged in parallel in the row direction. A row of memory cells is arranged among two adjacent bit lines, and the doped regions included in the row of memory cells are respectively connected to two corresponding adjacent bit lines (doped regions 146 or doped regions 148). For example, the memory cell M11, the memory cell M12, and the memory cell M13 are connected in series to form a row of memory cells. Counting from the memory cell M11, the first and third doped regions are electrically connected to the bit line BL0, and the second and third doped regions are electrically connected to the bit line BL0. The four doped regions are electrically connected to the bit line BL1. Memory cell M21, memory cell M22, and memory cell M23 are connected in series to form a row of memory cells, the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected to the third line bit line BL1. The memory cell M31, the memory cell M32, and the memory cell M33 are connected in series to form a row of memory cells, the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected to the third line bit line BL3.

Moreover, in the row direction, for example, the doped regions shared by the memory cells M11 and M12 connected in series are electrically connected to the bit line BL1, and the doped regions not shared by the memory cells M11 and M12 are electrically connected separately. Connect to bit line BL0. In the column direction, for example, the doped region shared by the series-connected memory cells M11 and M21 is electrically connected to the bit line BL1, and the other doped region of the memory cell M11 is electrically connected to the bit line BL0. Another doped region of the unit M21 is electrically connected to the bit line BL2.

The word lines WL0 - WL2 are respectively disposed on the substrate, for example. These word lines WL0 - WL2 are arranged in parallel in the column direction, and respectively connected to the auxiliary gates 124 of the memory cells in the same column. For example, the word line WL0 is connected to the auxiliary gates 124 of the memory cells M11-M31. The word line WL1 is connected to the auxiliary gates 124 of the memory cells M12-M32. The word line WL2 is connected to the auxiliary gates 124 of the memory cells M13-M33.

The erase lines EG0 - EG2 are respectively disposed on the substrate, for example. These erase lines EG0 - EG2 are arranged in parallel in the column direction, and respectively connected to the erase gates 128 of the memory cells in the same column. For example, the erase line EG 0 is connected to the erase gates 128 of the memory cells M11 - M31 . The erase line EG1 is connected to the erase gates 128 of the memory cells M12 - M32 . The erase line EG2 is connected to the erase gates 128 of the memory cells M13 - M33 .

The control gate lines CG0 - CG5 are arranged on the substrate respectively. These control gate lines CG0 - CG5 are arranged in parallel in the column direction, and are respectively connected to the control gates 150a or 150b of the memory cells in the same column. In this embodiment, the control gate lines CG0 , CG2 , and CG4 are connected to the control gates 150 a of the memory cells in the same column. The control gate lines CG1, CG3, and CG5 are connected to the control gates 150b of the memory cells in the same column.

In the above-mentioned nonvolatile memory, two adjacent memory cells M in the X direction (row direction) have the same structure and share the first doped region 146 or the second doped region 148 . The two adjacent memory cells M in the Y direction (column direction) have the same structure, sharing the first doped region 146 or the second doped region 148, the auxiliary gate (word line) 124, the erasing gate 128 and the control gate. Pole 150a (150b). Therefore, the integration degree of components can be improved.

In the above-mentioned non-volatile memory, the auxiliary gate and the erasing gate are arranged in a stacked structure, so that the density of elements can be increased.

In the above-mentioned non-volatile memory, the thickness of the gate dielectric layer 122 is relatively thin, and when the memory cell is operated, a smaller voltage can be used to open/close the channel region under the auxiliary gate 124, that is, the operating voltage can be reduced. . The control gate 150a (150b) covers the floating gate 140a (140b), which can increase the area between the control gate 150a (150b) and the floating gate 140a (140b), thereby improving the coupling of the memory element. Rate. Since the floating gate 140a (140b) is provided with a corner portion 141 between the heights of the erasing gate 128, and the angle of the corner portion 141 is less than or equal to 90 degrees, the electric field is concentrated through the corner portion 141, which can reduce the erasing voltage effectively. Electrons are efficiently pulled out from the floating gate 140a ( 140b ), increasing the speed of erasing data.

In the non-volatile memory of the present invention, since there is no gap between the floating gate 140a, the stacked structure 120 and the floating gate 140b, the accumulation degree of the memory cells can be improved. Moreover, charge can be stored in both the floating gate 140a and the floating gate 140b, so two bits of data can be stored in a single memory cell, thereby increasing the storage capacity.

Next, the operation modes of the nonvolatile memory of the present invention are described, including operation modes such as programming, erasing, and data reading. 2A and 2B are schematic diagrams of an example of programming operations on memory cells. 2C and 2D are schematic diagrams of an example of erasing operations on memory cells. 2E and 2F are schematic diagrams of an example of a read operation on a memory cell.

Please refer to FIG. 2A, when the floating gate FGa (left side bit) of the selected memory cell M22 is programmed, a voltage Vwlp is applied to the auxiliary gate (word line WL1) of the selected memory cell M22 to A channel is formed in the substrate below the gate, and the voltage Vwlp is, for example, 0.6-1.2 volts. A voltage of 0 volts is applied to the auxiliary gates (word lines WL0, WL2) of the unselected memory cells. Apply a voltage Vblp to the doped region (bit line BL1) of the selected memory cell M22; apply a voltage Vbli to the doped region (bit line BL2); apply a voltage Vcgp to the control gate (control gate line CG2); (Control gate line CG3 ) Apply voltage Vcc. A voltage Vegp is applied to the erase gate (erase line EG1 ) of the selected memory cell M22 and 0 volts is applied to the erase gate (erase line EG0 , EG2 ) of the unselected memory cell. The voltage Vblp is, for example, 3-7 volts; the voltage Vbli is, for example, 0.3 volts; the voltage Vcgp is, for example, 5-9 volts; and the voltage Vegp is, for example, 3-7 volts. Under this bias voltage, electrons are moved from the drain (bit line BL2) to the source (bit line BL1), and injected into the floating gate FGa ( left bit). Since the auxiliary gates (word lines WL0, WL2) of the non-selected memory cells apply a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gates of the non-selected memory cells, so the non-selected memory cells will not be programmed.

Please refer to FIG. 2B, when the floating gate FGb (right bit) of the selected memory cell M22 is programmed, a voltage Vwlp is applied to the auxiliary gate (word line WL1) of the selected memory cell M22 to A channel is formed in the substrate below the gate, and the voltage Vwlp is, for example, 0.6-1.2 volts. A voltage of 0 volts is applied to the auxiliary gates (word lines WL0, WL2) of the unselected memory cells. Apply a voltage Vblp to the doped region (bit line BL2) of the selected memory cell M22; apply a voltage Vbli to the doped region (bit line BL1); apply a voltage Vcgp to the control gate (control gate line CG3); (Control gate line CG2 ) Apply voltage Vcc. A voltage Vegp is applied to the erase gate (erase line EG1 ) of the selected memory cell M22 and 0 volts is applied to the erase gate (erase line EG0 , EG2 ) of the unselected memory cell. The voltage Vblp is, for example, 3-7 volts; the voltage Vbli is, for example, 0.3 volts; the voltage Vcgp is, for example, 5-9 volts; and the voltage Vegp is, for example, 3-7 volts. Under this bias voltage, electrons are moved from the drain (bit line BL1) to the source (bit line BL2), and injected into the floating gate FGb ( right bit). Since the auxiliary gates (word lines WL0, WL2) of the non-selected memory cells apply a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gates of the non-selected memory cells, so the non-selected memory cells will not be programmed.

Referring to FIG. 2C, when performing an erase operation on the floating gate FGa (the left bit) of the selected memory cell M22, a voltage Vcge is applied to the control gate (control gate line CG2) of the selected memory cell M22; A voltage of 0 volts is applied to the control gate (control gate line CG3) of the selected memory cell M22; a voltage Vege is applied to the erase gate (erase line EG1) of the selected memory cell M22; A voltage of 0 volts is applied to the erase gates (erase lines EG0 , EG2 ) of . The voltage Vege is, for example, 6-12 volts; the voltage Vcge is, for example, -8-0 volts. The voltage difference between the control gate (control gate line CG2) and the erasing gate (erasing line EG1) is used to induce the FN tunneling effect, and pull the electrons stored in the floating gate FGa (left bit) of the memory cell to out and remove.

Referring to FIG. 2D, when performing an erasing operation on the floating gate FGb (bit on the right) of the selected memory cell M22, a voltage Vcge is applied to the control gate (control gate line CG3) of the selected memory cell M22; A voltage of 0 volts is applied to the control gate (control gate line CG2) of the selected memory cell M22; a voltage Vege is applied to the erase gate (erase line EG1) of the selected memory cell M22; A voltage of 0 volts is applied to the erase gates (erase lines EG0 , EG2 ) of . The voltage Vege is, for example, 6-12 volts; the voltage Vcge is, for example, -8-0 volts. The voltage difference between the control gate (control gate line CG3) and the erasing gate (erase line EG1) is used to induce the FN tunneling effect, and pull the electrons stored in the floating gate FGb (bit on the right) of the memory cell to out and remove.

Please refer to FIG. 2E, when performing a read operation, a voltage Vcc is applied to the auxiliary gate (word line WL1) of the selected memory cell M22; 0 is applied to the control gate (control gate line CG2) of the selected memory cell M22. The voltage of volts, the voltage Vcc is applied to the control gate (control gate line CG3); 0 volts is applied to the erase gate (erase line EG1) of the selected memory cell M22; the doped region of the selected memory cell M22 A voltage Vcc is applied to (bit line BL2 ); a voltage of 0 volts is applied to the doped region (bit line BL1 ); and 0 volts is applied to the erase gates (erase lines EG0 , EG2 ) of unselected memory cells. Here, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the floating gate FGa (the left bit) of the memory cell can be judged by detecting the magnitude of the channel current of the memory cell.

Please refer to FIG. 2F, when performing a read operation, a voltage Vcc is applied to the auxiliary gate (word line WL1) of the selected memory cell M22; 0 is applied to the control gate (control gate line CG3) of the selected memory cell M22. The voltage of volts, the voltage Vcc is applied to the control gate (control gate line CG2); 0 volts is applied to the erase gate (erase line EG1) of the selected memory cell M22; the doped region of the selected memory cell M22 A voltage Vcc is applied to (bit line BL1 ); a voltage of 0 volts is applied to the doped region (bit line BL2 ); and 0 volts is applied to the erase gates (erase lines EG0 , EG2 ) of unselected memory cells. Here, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the floating gate FGb (right bit) of the memory cell can be determined by detecting the magnitude of the channel current of the memory cell.

In the operation method of the non-volatile memory of the present invention, when performing the programming operation, a low voltage is applied to the auxiliary gate to form a channel in the substrate under the auxiliary gate in the mode of hot electron injection on the source side , to write electrons into the floating gate. During the erasing operation, the erasing gate is used to erase data, so that electrons are removed through the erasing gate dielectric layer, which can reduce the number of times electrons pass through the tunneling dielectric layer, thereby improving reliability. In addition, the corner portion of the floating gate is set between the heights of the erasing gate, and the angle of the corner portion is less than or equal to 90 degrees. The electric field is concentrated through the corner portion, and electrons can be efficiently pulled out from the floating gate. , to increase the speed of erasing data. The programmed threshold voltage of the memory cell of the present invention is between Vcc and 0; the threshold voltage of the memory cell after erasing is less than 0.

FIG. 3A is a top view of a non-volatile memory shown in another embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of a non-volatile memory according to another embodiment of the present invention. FIG. 3B is a cross-sectional view along line AA' in FIG. 3A. FIG. 3C is a schematic circuit diagram of a non-volatile memory shown in an embodiment of the present invention. In FIGS. 3A to 3C , components that are the same as those in FIGS. 1A to 1C are assigned the same reference numerals, and detailed description thereof will be omitted.

Please refer to FIG. 3A, FIG. 3B and FIG. 3C. The non-volatile memory includes a plurality of memory cells M11-M33, word lines WL0-WL2, erase lines EG0-EG2, bit lines BL0-BL3, control gate lines CG0- CG3. The memory cells M11-M33 are arranged in a row/column array.

A nonvolatile memory is provided on the substrate 100 . For example, an isolation structure 102 is disposed in the substrate 100 to define an active region 104 . The isolation structure 102 is, for example, a shallow trench isolation structure.

As shown in FIG. 3B, the memory cell M includes a stack structure 120, an auxiliary gate dielectric layer 130a (130b), an erasing gate dielectric layer 132a (132b), a floating gate 140a (140b), and a tunneling dielectric layer 142a. ( 142 b ), doped region 146 , doped region 148 , control gate 150 a ( 150 b ), and inter-gate dielectric layer 152 .

The stack structure 120 is sequentially composed of a gate dielectric layer 122 , an auxiliary gate 124 , an insulating layer 126 and an erasing gate 128 from the substrate 100 . A capping layer 118 is optionally disposed on the erase gate 128 .

The floating gate 140 a and the floating gate 140 b are, for example, disposed on sidewalls on both sides of the stack structure 120 , and the tops of the floating gate 140 a and the floating gate 140 b respectively have corner portions 141 . The corner portion 141 is adjacent to the erasing gate 128 , and the height of the corner portion 141 falls between the heights of the erasing gate 128 . The angle of the corner portion 141 is less than or equal to 90 degrees.

The tunnel dielectric layer 142 a is, for example, disposed between the floating gate 140 a and the substrate 100 ; the tunnel dielectric layer 142 b is, for example, disposed between the floating gate 140 b and the substrate 100 . The tunneling dielectric layer 142 a is, for example, disposed between the control gate 150 a and the doped region 146 ; the tunneling dielectric layer 142 b is, for example, disposed between the control gate 150 b and the doped region 148 .

The doped region 146 is, for example, disposed in the substrate 100 beside the floating gate 140a. The doped region 148 is, for example, disposed in the substrate 100 beside the floating gate 140b. The floating gate 140 a , the stack structure 120 and the floating gate 140 b are connected and disposed on the substrate 100 between the doped region 146 and the doped region 148 . The doped region 146 and the doped region 148 are, for example, doped regions containing N-type or P-type dopants, depending on the design of the device.

The control gate 150a and the control gate 150b are respectively disposed on the floating gate 140a and the floating gate 140b of two adjacent memory cells. The control gate 150a and the control gate 150b extend in the Y direction (column direction), for example. Two adjacent memory cells share the control gate 150a or the control gate 150b, and the control gate 150a and the control gate 150b respectively fill the opening between the two adjacent memory cells.

The inter-gate dielectric layer 152 is, for example, disposed between the control gate 150a and the floating gate 140a and between the control gate 150b and the floating gate 140b.

An interlayer insulating layer (not shown) is disposed on the substrate 100 and covers the memory cells M, for example. The plurality of plugs 162 are, for example, disposed in an interlayer insulating layer. A plurality of bit lines BL0 - BL3 are disposed on the interlayer insulating layer, for example, and the bit lines BL0 - BL3 are respectively electrically connected to the doped regions 146 or 148 of the memory cells M through the plugs 162 . Referring to FIG. 3A , the opening 164 for forming the plug 162 penetrates through the interlayer insulating layer, the control gate 150 a and the control gate 150 b until the doped region 146 and the doped region 148 are exposed. An insulating layer 166 is formed between the plug 162 and the control gate 150a and between the plug 162 and the control gate 150b. The material of the bit lines BL0 - BL3 is, for example, conductive materials such as aluminum, tungsten, and copper.

As shown in FIG. 3C , the memory cells M11 - M33 have the structures shown in FIGS. 3A and 3B . In the following description, the memory cell M in FIG. 1B is divided into a left bit a and a right bit b.

In the X direction (row direction), a plurality of memory cells M are connected in series through the doped region (the doped region 146 or the doped region 148 ), and adjacent memory cells M share a control gate. For example, the structure of the memory cell M11 is the same as that of the memory cell M12, sharing a doped region (the doped region 146 or the doped region 148), and sharing a control gate (the control gate 150a or the control gate 150b ); the structure of the memory cell M12 is the same as that of the memory cell M13, sharing a doped region (doped region 146 or doped region 148), and sharing a control gate (control gate 150a or control gate 150b); ...; the structure of the memory cell M31 is the same as that of the memory cell M32, sharing a doped region (doped region 146 or doped region 148), and sharing a control gate (control gate 150a or control gate 150b); The structure of the memory cell M32 is the same as that of the memory cell M33, sharing a doped region (the doped region 146 or the doped region 148) and a control gate (the control gate 150a or the control gate 150b).

In the Y direction (column direction), a plurality of memory cells M are connected in series through the doped region (the doped region 146 or the doped region 148), and share the auxiliary gate 124, the erasing gate 128 and the control gate. 150a and control grid 150b. The control gate 150 a and the control gate 150 b fill up between the memory cells M (eg, the memory cell M11 , the memory cell M21 and the memory cell M31 ). For example, the memory cell M11 has the same structure as the memory cell M21 and shares a doped region (doped region 146 or doped region 148), and the memory cell M21 has the same structure as the memory cell M31 and shares a doped region. Region (doped region 146 or doped region 148); ...; the structure of the memory cell M13 is the same as that of the memory cell M23, sharing a doped region (doped region 146 or doped region 148), the structure of the memory cell M23 The same structure as the memory cell M33 shares a doped region (the doped region 146 or the doped region 148 ).

The bit lines BL0 to BL3 are respectively provided on the substrate, for example, and these bit lines BL0 to BL3 are arranged in parallel in the row direction. A row of memory cells is arranged among two adjacent bit lines, and the doped regions included in the row of memory cells are respectively connected to two corresponding adjacent bit lines (doped regions 146 or doped regions 148). For example, the memory cell M11, the memory cell M12, and the memory cell M13 are connected in series to form a row of memory cells. Counting from the memory cell M11, the first and third doped regions are electrically connected to the bit line BL0, and the second and third doped regions are electrically connected to the bit line BL0. The four doped regions are electrically connected to the bit line BL1. Memory cell M21, memory cell M22, and memory cell M23 are connected in series to form a row of memory cells, the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected to the third line bit line BL1. The memory cell M31, the memory cell M32, and the memory cell M33 are connected in series to form a row of memory cells, the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected to the third line bit line BL3.

Moreover, in the row direction, for example, the doped regions shared by the memory cells M11 and M12 connected in series are electrically connected to the bit line BL1, and the doped regions not shared by the memory cells M11 and M12 are electrically connected separately. Connect to bit line BL0. In the column direction, for example, the doped region shared by the series-connected memory cells M11 and M21 is electrically connected to the bit line BL1, and the other doped region of the memory cell M11 is electrically connected to the bit line BL0. Another doped region of the unit M21 is electrically connected to the bit line BL2.

The word lines WL0 - WL2 are respectively disposed on the substrate, for example. These word lines WL0 - WL2 are arranged in parallel in the column direction, and respectively connected to the auxiliary gates 124 of the memory cells in the same column. For example, the word line WL0 is connected to the auxiliary gates 124 of the memory cells M11-M31. The word line WL1 is connected to the auxiliary gates 124 of the memory cells M12-M32. The word line WL2 is connected to the auxiliary gates 124 of the memory cells M13-M33.

The erase lines EG0 - EG2 are respectively disposed on the substrate, for example. These erase lines EG0 - EG2 are arranged in parallel in the column direction, and respectively connected to the erase gates 128 of the memory cells in the same column. For example, the erase line EG 0 is connected to the erase gates 128 of the memory cells M11 - M31 . The erase line EG1 is connected to the erase gates 128 of the memory cells M12 - M32 . The erase line EG2 is connected to the erase gates 128 of the memory cells M13 - M33 .

The control gate lines CG0 - CG3 are arranged on the substrate respectively, and these control gate lines CG0 - CG3 are arranged in parallel in the column direction, respectively connected to the control gates 150 a ( 150 b ) of memory cells in two adjacent columns. In this embodiment, the control gate line CG0 is connected to the control gate 150a (150b) on the left side of the memory cells M11, M21, M31; the control gate line CG1 is connected to the control gates on the right side of the memory cells M11, M21, M31. Pole 150a (150b) and the control gate 150a (150b) on the left side of memory cell M12, M22, M32; Control gate line CG2 connects the control gate 150a (150b) and The left control gates 150a (150b) of the memory cells M13, M23, M33; the control gate line CG3 is connected to the right control gates 150a (150b) of the memory cells M13, M23, M33.

In the above-mentioned nonvolatile memory, two adjacent memory cells M in the X direction (row direction) have the same structure, sharing the doped region 146 or the doped region 148 and the control gate 150a ( 150b ). And in the Y direction (column direction) adjacent two memory cell M structures are the same, common doping region 146 or doping region 148, auxiliary gate (word line) 124, erase gate 128 and control gate 150a (150b ). Therefore, the integration degree of components can be improved.

In the above-mentioned non-volatile memory, the auxiliary gate and the erasing gate are arranged in a stacked structure, so that the density of elements can be increased.

In the above-mentioned non-volatile memory, the thickness of the gate dielectric layer 122 is relatively thin, and when the memory cell is operated, a smaller voltage can be used to open/close the channel region under the auxiliary gate 124, that is, the operating voltage can be reduced. . The control gate 150a (150b) wraps the floating gate 140a (140b), which can increase the area between the control gate 150a (150b) and the floating gate 140a (140b), thereby improving the memory element. Coupling rate. Since the floating gate 140a (140b) is provided with a corner portion 141 between the heights of the erasing gate 128, and the angle of the corner portion 141 is less than or equal to 90 degrees, the electric field is concentrated through the corner portion 141, which can reduce the erasing voltage effectively. Electrons are efficiently pulled out from the floating gate 140a ( 140b ), increasing the speed of erasing data.

In the non-volatile memory of the present invention, since there is no gap between the floating gate 140a, the stacked structure 120 and the floating gate 140b, the accumulation degree of the memory cells can be improved. Moreover, charge can be stored in both the floating gate 140a and the floating gate 140b, so two bits of data can be stored in a single memory cell, thereby increasing the storage capacity.

Next, the operation modes of the nonvolatile memory of the present invention are described, including operation modes such as programming, erasing, and data reading. 4A and 4B are schematic diagrams of an example of programming operations on memory cells. 4C and 4D are schematic diagrams of an example of erasing operations on memory cells. 4E and 4F are schematic diagrams of an example of a read operation on a memory cell.

Please refer to FIG. 4A, when the floating gate FGa (left bit) of the selected memory cell M22 is programmed, a voltage Vwlp is applied to the auxiliary gate (word line WL1) of the selected memory cell M22 to A channel is formed in the substrate below the gate, and the voltage Vwlp is, for example, 0.6-1.2 volts. A voltage of 0 volts is applied to the auxiliary gates (word lines WL0, WL2) of the unselected memory cells. Apply a voltage Vblp to the doped region (bit line BL1) of the selected memory cell M22; apply a voltage Vbli to the doped region (bit line BL2); apply a voltage Vcgp to the control gate (control gate line CG1); (Control gate line CG2 ) Apply voltage Vcc. The erase gates of the selected memory cell M22 (erase line EG1 ) and the erase gates of the unselected memory cells (erase lines EG0 , EG2 ) are applied with a voltage Vegp. The voltage Vblp is, for example, 3-7 volts; the voltage Vbli is, for example, 0.3 volts; the voltage Vcgp is, for example, 5-9 volts; and the voltage Vegp is, for example, 3-7 volts. Under this bias voltage, electrons are moved from the drain (bit line BL2) to the source (bit line BL1), and injected into the floating gate FGa ( left bit). Since the auxiliary gates (word lines WL0, WL2) of the non-selected memory cells apply a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gates of the non-selected memory cells, so the non-selected memory cells will not be programmed.

Please refer to FIG. 4B, when the floating gate FGb (bit on the right side) of the selected memory cell M22 is programmed, a voltage Vwlp is applied to the auxiliary gate (word line WL1) of the selected memory cell M22 to A channel is formed in the substrate below the gate, and the voltage Vwlp is, for example, 0.6-1.2 volts. A voltage of 0 volts is applied to the auxiliary gates (word lines WL0, WL2) of the unselected memory cells. Apply a voltage Vblp to the doped region (bit line BL2) of the selected memory cell M22; apply a voltage Vbli to the doped region (bit line BL1); apply a voltage Vcgp to the control gate (control gate line CG2); (Control gate line CG1 ) Apply voltage Vcc. The erase gates of the selected memory cell M22 (erase line EG1 ) and the erase gates of the unselected memory cells (erase lines EG0 , EG2 ) are applied with a voltage Vegp. The voltage Vblp is, for example, 3-7 volts; the voltage Vbli is, for example, 0.3 volts; the voltage Vcgp is, for example, 5-9 volts; and the voltage Vegp is, for example, 3-7 volts. Under this bias voltage, electrons are moved from the drain (bit line BL1) to the source (bit line BL2), and injected into the floating gate FGb ( right bit). Since the auxiliary gates (word lines WL0, WL2) of the non-selected memory cells apply a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gates of the non-selected memory cells, so the non-selected memory cells will not be programmed.

Referring to FIG. 4C, when performing an erase operation on the floating gate FGa (the left bit) of the selected memory cell M22, a voltage Vcge is applied to the control gate (control gate line CG1) of the selected memory cell M22; A voltage of 0 volts is applied to the control gate (control gate line CG2) of the selected memory cell M22; a voltage Vege is applied to the erase gate (erase line EG1) of the selected memory cell M22; A voltage of 0 volts is applied to the erase gates (erase lines EG0 , EG2 ) of . The voltage Vege is, for example, 6-12 volts; the voltage Vcge is, for example, -8-0 volts. The voltage difference between the control gate (control gate line CG1) and the erasing gate (erasing line EG1) is used to induce the FN tunneling effect, and pull the electrons stored in the floating gate FGa (left bit) of the memory cell to out and remove.

Referring to FIG. 4D, when performing an erasing operation on the floating gate FGb (bit on the right) of the selected memory cell M22, a voltage Vcge is applied to the control gate (control gate line CG2) of the selected memory cell M22; A voltage of 0 volts is applied to the control gate (control gate line CG1) of the selected memory cell M22; a voltage Vege is applied to the erase gate (erase line EG1) of the selected memory cell M22; A voltage of 0 volts is applied to the erase gates (erase lines EG0 , EG2 ) of . The voltage Vege is, for example, 6-12 volts; the voltage Vcge is, for example, -8-0 volts. The voltage difference between the control gate (control gate line CG2) and the erasing gate (erasing line EG1) is used to induce the FN tunneling effect, and pull the electrons stored in the floating gate FGb (bit on the right) of the memory cell to out and remove.

Please refer to FIG. 4E, when performing a read operation, a voltage Vcc is applied to the auxiliary gate (word line WL1) of the selected memory cell M22; 0 is applied to the control gate (control gate line CG1) of the selected memory cell M22. The voltage of volts is applied to the control gate (control gate line CG2); the voltage of 0 volts is applied to the erase gate (erase line EG1) of the selected memory cell M22; A voltage Vcc is applied to the impurity region (bit line BL2 ); a voltage of 0 volts is applied to the doped region (bit line BL1 ); and a voltage of 0 volts is applied to the erase gates (erase lines EG0 and EG2 ) of the unselected memory cells. Here, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the floating gate FGa (the left bit) of the memory cell can be judged by detecting the magnitude of the channel current of the memory cell.

Please refer to FIG. 4F, when performing a read operation, a voltage Vcc is applied to the auxiliary gate (word line WL1) of the selected memory cell M22; a voltage is applied to the control gate (control gate line CG1) of the selected memory cell M22 Vcc, apply a voltage of 0 volts to the control gate (control gate line CG2); apply a voltage of 0 volts to the erase gate (erase line EG1) of the selected memory cell M22; A voltage Vcc is applied to the impurity region (bit line BL1 ); a voltage of 0 volts is applied to the doped region (bit line BL2 ); and a voltage of 0 volts is applied to the erase gates (erase lines EG0 and EG2 ) of the unselected memory cells. Here, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the floating gate FGb (right bit) of the memory cell can be determined by detecting the magnitude of the channel current of the memory cell.

In the operation method of the non-volatile memory of the present invention, when performing programming operation, a low voltage is applied to the auxiliary gate, so that a channel can be formed in the substrate under the auxiliary gate, and the hot electron injection mode of the source side is used. , to write electrons into the floating gate. During the erasing operation, the erasing gate is used to erase data, so that electrons are removed through the erasing gate dielectric layer, which can reduce the number of times electrons pass through the tunneling dielectric layer, thereby improving reliability. In addition, the corner portion of the floating gate is set between the heights of the erasing gate, and the angle of the corner portion is less than or equal to 90 degrees. The electric field is concentrated through the corner portion, and electrons can be efficiently pulled out from the floating gate. , to increase the speed of erasing data. The programmed threshold voltage of the memory cell of the present invention is between Vcc and 0; the threshold voltage of the memory cell after erasing is less than 0.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (16)

1. A non-volatile memory, characterized in that, comprising: The first storage unit is arranged on the substrate, and the first storage unit includes: a stack structure, including a gate dielectric layer, an auxiliary gate, an insulating layer and an erasing gate sequentially disposed on the substrate; The first floating gate and the second floating gate are respectively arranged on the sidewalls on both sides of the stack structure, and the tops of the first floating gate and the second floating gate respectively have a corner portion, the corner portion is adjacent to the erasing gate, and the height of the corner portion falls between the heights of the erasing gate; A first tunneling dielectric layer and a second tunneling dielectric layer are disposed between the first floating gate and the substrate and between the second floating gate and the substrate, respectively; The first erasing gate dielectric layer and the second erasing gate dielectric layer are arranged between the erasing gate and the first floating gate and between the erasing gate and the second floating gate, respectively. Between the floating gates, the material of the first erasing gate dielectric layer and the second erasing gate dielectric layer includes silicon oxide; The first auxiliary gate dielectric layer and the second auxiliary gate dielectric layer are respectively arranged between the auxiliary gate and the first floating gate and between the auxiliary gate and the second floating gate. Between, the materials of the first auxiliary gate dielectric layer and the second auxiliary gate dielectric layer include a double stack structure of silicon oxide and silicon nitride and a triple stack structure of silicon oxide, silicon nitride and silicon oxide structure; The first doped region and the second doped region are respectively arranged in the substrate, wherein the first floating gate, the stack structure and the second floating gate are connected and arranged on the first floating gate. on the substrate between the doped region and the second doped region; a first control gate and a second control gate respectively disposed on the first floating gate and the second floating gate; and An inter-gate dielectric layer is disposed between the first control gate and the first floating gate and between the second control gate and the second floating gate. 2. The nonvolatile memory according to claim 1, further comprising: A first bit line and a second bit line are arranged in parallel on the substrate, wherein the first doped region is electrically connected to the first bit line, and the second doped region is electrically connected to the second bit line. 3. The nonvolatile memory according to claim 1, further comprising a second storage unit in the row direction, the second storage unit is arranged on the substrate, and the structure of the second storage unit The structure is the same as that of the first memory unit, sharing the second doped region. 4. The nonvolatile memory according to claim 3, further comprising: A first bit line and a second bit line are arranged on the substrate in parallel, wherein the second doped region shared by the first memory unit and the second memory unit is electrically connected to the first bit line, the first doped region of the first memory unit and the third doped region of the second memory unit are respectively electrically connected to the second bit line. 5. The nonvolatile memory according to claim 3, wherein the first storage unit and the second storage unit share the first control gate or the second control gate, and The first control gate or the second control gate fills an opening between the first memory unit and the second memory unit. 6. The nonvolatile memory according to claim 1, further comprising a third storage unit in the column direction, the third storage unit is arranged on the substrate, and the third storage unit The structure is the same as that of the first storage unit, the third storage unit and the first storage unit are connected in series through the first doped region, and share the auxiliary gate and the erasing gate electrode, the first control gate and the second control gate, and the first control gate and the second control gate fill the gap between the first memory unit and the third memory unit between. 7. The non-volatile memory according to claim 6, further comprising: The first bit line, the second bit line and the third bit line are arranged in parallel on the substrate, wherein the first memory unit is connected in series with the first doped region of the third memory unit and is electrically connected to the second bit line, the second doped region of the first memory cell is electrically connected to the first bit line, and the third doped region of the third memory cell is electrically connected to the Describe the third bit line. 8. The nonvolatile memory according to claim 1, wherein the first tunneling dielectric layer is further disposed between the first control gate and the first doped region; The second tunneling dielectric layer is further disposed between the second control gate and the second doped region. 9. The nonvolatile memory according to claim 1, wherein the first auxiliary gate dielectric layer and the second auxiliary gate dielectric layer are thicker than the first erasing gate dielectric layer. layer with the thickness of the second erase gate dielectric layer. 10. The nonvolatile memory according to claim 1, wherein a material of the insulating layer comprises silicon oxide. 11. The non-volatile memory according to claim 1, wherein the material of the inter-gate dielectric layer comprises a triple stack structure of silicon oxide, silicon nitride and silicon oxide or silicon oxide and silicon nitride double-layer structure or other materials with a dielectric constant k>4. 12. The nonvolatile memory according to claim 1, wherein the material of the first tunneling dielectric layer and the second tunneling dielectric layer comprises silicon oxide, and the first tunneling dielectric layer The thickness of the dielectric layer and the second tunneling dielectric layer is between 60 angstroms and 200 angstroms. 13. The nonvolatile memory according to claim 1, wherein the material of the gate dielectric layer comprises silicon oxide, and the thickness of the gate dielectric layer is less than or equal to that of the first tunneling dielectric layer. layer with the thickness of the second tunneling dielectric layer. 14. The nonvolatile memory according to claim 1, wherein the thickness of the first erasing gate dielectric layer and the second erasing gate dielectric layer is between 100 angstroms and 180 angstroms. between. 15. The non-volatile memory according to claim 1, wherein the corner angle is less than or equal to 90 degrees. 16. The nonvolatile memory according to claim 1, wherein the programmed threshold voltage of the first memory cell is between Vcc and 0: the erased first memory cell The threshold voltage is less than zero.