CN106169478A - Flash memories and forming method thereof - Google Patents

Abstract

The present invention provides a flash memory and its forming method. The flash memory device includes at least one device area and at least one word line lead-out area. An isolation structure for isolating memory cells is provided in the device region, a first insulating layer and a second insulating layer are provided in the word line lead-out region, and one end of the first insulating layer and the second insulating layer are both connected to the isolation structure, so that the first insulating layer and the second insulating layer can be prevented from being independent island structures, and in the formation process of the flash memory, the first insulating layer and the second insulating layer can be effectively avoided Layer detachment occurs.

Description

Flash memory and method of forming the same

technical field

The invention relates to the technical field of semiconductors, in particular to a flash memory and a method for forming the flash memory.

Background technique

Flash memory (Flash EPROM) is a form of electronically erasable programmable read-only memory (electrically erasable programmable read-only memory EEPROM). Flash memory is widely used in portable computers, mobile phones, In electronic products such as digital music players. Flash memory is a kind of non-volatile memory. Its operating principle is to control the switch of the gate channel by changing the critical voltage of the storage unit, so as to achieve the purpose of storing data, so that the data stored in the storage unit will not be lost due to power interruption. disappear.

According to the different gate structures of the transistors constituting the memory cells, generally, flash memory can be divided into two types: stacked gate flash memory and split gate flash memory. Among them, the stacked flash memory has the problem of over-erasing, and the difference from the stacked gate flash memory is that the split gate flash memory also has a memory cell word line for controlling erasure and programming on one side of the memory cell with a floating gate, so Split-gate flash avoids the problem of over-erasing. Specifically, the word line of the memory cell on one side of the memory cell needs to pass through the conductive plug to apply or extract the electrical signal, wherein there are many ways to extract the electrical signal of the word line of the memory cell. For example, a conductive plug can be directly formed on the memory cell word line on one side of the memory cell or a word line lead-out area can be defined, and a contact word line is formed on the word line lead-out area, that is, a contact word line can be formed on the contact word line. Conductive plugs are formed to lead out word lines of the memory cells located on one side of the memory cells.

1A is a top view of a word line lead-out area formed with a contact word line, and FIG. 1B is a cross-sectional view of a word line lead-out area formed with a contact word line. As shown in FIGS. 1A and 1B, the word line lead-out area includes a first An insulating layer 11, a second insulating layer 12, and a contact word line 13, wherein the contact word line 13 is formed between the first insulating layer 11 and the second insulating layer 12, which is used for conducting with the subsequently formed Plug connection. However, as shown in FIG. 1A , usually the first insulating layer 11 or the second insulating layer 12 is an independent structure with a small area. Therefore, when forming the first insulating layer 11 and the second insulating layer 12 During the process, the first insulating layer 11 and the second insulating layer 12 are easily peeled off, so that the contact word line 13 formed subsequently cannot meet the process requirements, and the conductive plugs formed on the contact word line 13 The connection of the plug to the contact word line 13 is abnormal.

Contents of the invention

The object of the present invention is to provide a flash memory and a method for forming the flash memory, so as to solve the problem in the existing flash memory that the insulating layer used to support the contact word line is prone to peeling off.

In order to solve the above technical problems, the present invention provides a method for forming a flash memory, comprising:

S11. A substrate is provided, the substrate includes at least one device region and at least one word line lead-out region, and a first dielectric layer is covered on the device region and the word line lead-out region, and a first dielectric layer is formed on the device region There is at least one storage unit, and the first dielectric layer has an opening exposing the storage unit;

S12, forming a first groove and a second groove in the lead-out region of the word line, one end of the first groove and the second groove both communicate with the opening;

S13, filling the opening, the first groove and the second groove with a second dielectric layer;

S14, removing the first dielectric layer, forming an isolation structure covering the memory cell and forming a first insulating layer and a second insulating layer located in the word line lead-out region, the first insulating layer and the second insulating layer One end of each is connected to the isolation structure;

S15, deposit a conductive material on the substrate, and etch the conductive material to form a memory cell word line located on one side of the isolation structure and a contact word line located in the word line lead-out area, the memory cell word line and the contact word line The lines are connected to form a word line strip.

Optionally, in S11, two memory cells and a common source line are formed on the device region, the two memory cells are formed on both sides of the common source line, and the two memory cells There is an opening exposing the storage unit above.

Optionally, the two openings communicate with each other to form an annular opening surrounding the common source line.

Optionally, in S11, the first layout is used to define the annular opening, and the first layout includes a ring-shaped dark pattern arranged in a bright area.

Optionally, in S12, a second layout is used to define the first groove and the second groove of the lead-out area of the word line, and the second layout includes the first strip-shaped dark pattern and the second strip-shaped pattern arranged in the bright area. dark graphics.

Optionally, when the first layout and the second layout are projected on the substrate, one end of the projection of the first dark strip pattern and the projection of the second dark strip pattern is connected to the ring The projective connection of dark graphs.

Optionally, in S13, the second dielectric layer is formed by high density plasma chemical vapor deposition.

Optionally, after S13 , further comprising performing chemical mechanical polishing on the substrate filled with the second dielectric layer, so that the heights of the first dielectric layer and the second dielectric layer are consistent.

Optionally, the material of the first dielectric layer is silicon nitride.

Optionally, the material of the second dielectric layer is silicon oxide.

Another object of the present invention is to provide a flash memory, including at least one device area and at least one word line lead-out area; the device area includes at least one storage unit, an isolation structure covering the storage unit, and an isolation structure formed on the The memory cell word line on one side of the isolation structure; the word line lead-out area includes a first insulating layer, a second insulating layer and a contact word line, and the contact word line is formed on the first insulating layer and the second insulating layer between; at least one of the memory cell word lines and at least one of the contact word lines are connected to form a word line strip, and it is characterized in that one end of the first insulating layer and the second insulating layer are connected to the isolation structure .

Optionally, there are two storage units in the device region, and a common source line is also included in the device region, the two storage units are formed on both sides of the common source line, and the two storage units The cells are covered with the isolation structure, and the memory cell word line is formed on the side of the two isolation structures away from the common source line.

Optionally, the two isolation structures are connected to each other to form a ring structure surrounding the common source line.

Optionally, the two memory cell word lines are respectively connected to contact word lines in different word line lead-out areas to form two word line strips, and the two word line strips form a word line strip pair.

Optionally, the second insulating layer isolates two of the word line strips.

Optionally, the pair of word line stripes is connected to multiple device regions and two word line lead-out regions, wherein one word line stripe in the pair of word line stripes is a storage device of each device region in the plurality of device regions. The cell word line is formed by connecting the contact word line of a word line lead-out area, and the other word line band in the word line band pair is formed by another memory cell word line in each device area in the plurality of device areas. The two memory cell word lines in the same device area are respectively connected to the contact word lines of the two word line lead-out areas.

Optionally, among the plurality of device regions, some of the device regions have a strip structure, and the plurality of device regions and two word line lead-out regions are formed along the length direction of the device regions of the strip structure A strip-shaped structure, the word line lead-out area is located between two device areas.

Optionally, both the first insulating layer and the second insulating layer are strip structures, and the first insulating layer and the second insulating layer are arranged in parallel along a length direction perpendicular to the device region of the strip structure.

Optionally, both ends of the second insulating layer are connected to adjacent isolation structures.

Optionally, the flash memory includes a plurality of word line stripe pairs, and the plurality of word line stripe pairs are arranged in parallel.

Compared with the prior art, in the flash memory provided by the present invention, one end of the first insulating layer and the second insulating layer located in the lead-out area of the word line are both connected to the isolation structure in the device area, so that the formed first Neither the insulating layer nor the second insulating layer exists independently. That is, the first insulating layer and the second insulating layer are connected to the isolation structure to form an integral body, so that neither the first insulating layer nor the second insulating layer forms an island structure with a small area, so that the flash memory During the forming process of the memory, the falling off of the first insulating layer and the second insulating layer can be effectively avoided, and further, the contact word line formed between the first insulating layer and the second insulating layer can be ensured to have a certain height and flatness.

Description of drawings

1A is a top view of a word line lead-out region formed with a contact word line in the prior art;

1B is a cross-sectional view of a word line lead-out region formed with a contact word line in the prior art;

2 is a schematic flow chart of a method for forming a flash memory according to an embodiment of the present invention;

3A-7A are structural top views during the formation process of the flash memory according to an embodiment of the present invention;

3B to 7B are structural cross-sectional views during the formation of the flash memory according to an embodiment of the present invention;

FIG. 4C is a schematic diagram of the projection of the first layout and the second layout on the substrate used in the method for forming the flash memory according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a word line band pair in a flash memory formed in an embodiment of the present invention;

9 is a top view of the structure of the flash memory in an embodiment of the present invention;

Fig. 10 is a sectional view along the AA' direction of the device region in the structure of the flash memory in one embodiment of the present invention;

Fig. 11 is a sectional view along the BB' direction of the word line lead-out region in the structure of the flash memory according to an embodiment of the present invention.

detailed description

As mentioned in the background, word lines of memory cells for controlling erasing and programming are formed in the flash memory, so that the problem of over-erasing can be avoided. When forming a contact word line in the word line lead-out region to lead out a memory cell word line located on one side of the memory cell, the contact word line is usually formed between two insulating layers, that is, through the two insulating layers. support, so that the subsequently formed contact word line has a certain height and surface flatness, thereby ensuring that the signal transmission between the conductive plug formed on the contact word line and the contact word line is normal. However, among the two insulating layers used to support the contact word line, one of the insulating layers is usually an isolated structure, and the contact area between the isolated structure and the substrate is small, so when forming the insulating layer, The isolated insulating layer is very easy to fall off, which leads to the failure of the subsequently formed contact word line to meet the process requirements.

Therefore, the present invention provides a method for forming a flash memory. FIG. 2 is a flow chart of a method for forming a flash memory according to an embodiment of the present invention. As shown in FIG. 2 , the method for forming a flash memory includes:

S11. A substrate is provided, the substrate includes at least one device region and at least one word line lead-out region, and a first dielectric layer is covered on the device region and the word line lead-out region, and a first dielectric layer is formed on the device region There is at least one storage unit, and the first dielectric layer has an opening exposing the storage unit;

S12, forming a first groove and a second groove in the lead-out region of the word line, one end of the first groove and the second groove both communicate with the opening;

S13, filling the opening, the first groove and the second groove with a second dielectric layer;

S14, removing the first dielectric layer, forming an isolation structure covering the memory cell and forming a first insulating layer and a second insulating layer located in the word line lead-out region, the first insulating layer and the second insulating layer One end of each is connected to the isolation structure;

S15, deposit a conductive material on the substrate, and etch the conductive material to form a memory cell word line located on one side of the isolation structure and a contact word line located in the word line lead-out area, the memory cell word line and the contact word line The lines are connected to form a word line strip.

In the forming method of the flash memory memory provided by the present invention, one end of the first groove formed in the first dielectric layer and one end of the second groove are connected with the opening in the device region, so that when the second dielectric layer is subsequently filled , making the second dielectric layer in the first groove, the second groove and the opening an interconnected whole, improving the adhesion between the second dielectric layer and the substrate in the first groove and the second groove Furthermore, when the first dielectric layer around the second dielectric layer is removed to form the first insulating layer and the second insulating layer, the peeling phenomenon of the first insulating layer or the second insulating layer can be effectively avoided.

The method for forming the flash memory proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

3A to 7A are top views of the structure during the formation of the flash memory according to an embodiment of the present invention, and FIGS. 3B to 7B are the structures during the formation of the flash memory according to one embodiment of the present invention shown in FIGS. 3A to 7A Sectional view. Referring to FIG. 3A-FIG. 7A and FIG. 3B-FIG. 7B, and in combination with FIG. 2 , the method for forming the flash memory storage device provided by the present invention will be further described in detail.

Step S11, providing a substrate, as shown in FIG. 3A and FIG. 3B, wherein, the area 100 in FIG. 3B is a cross-sectional view along the BB' direction in FIG. 3A, and the area 200 in FIG. 3B is a cross-sectional view along AA' in FIG. 3A Orientation cutaway. As shown in FIGS. 3A and 3B , the substrate has at least one device region 200 and at least one word line lead-out region 100, the device region 200 is an area for forming memory cells, and the word line lead-out region 100 Used to define where contact word lines are formed. In this embodiment, there are multiple devices 200 and multiple word line lead-out regions 100 on the substrate, and the device regions 200 and word line lead-out regions 100 are arranged in a rectangular array.

Wherein, both the device region 200 and the word line lead-out region 100 are covered with a first dielectric layer 400, and the material of the first dielectric layer 400 may be silicon nitride. Further, at least one storage unit 210 is formed on the device region 200, and an opening 221 exposing the storage unit 210 is provided in the first dielectric layer. In this embodiment, two storage units 210 are formed on the device region 200, and a common source line 240 is also formed, and the two storage units 210 are formed on both sides of the common source line 240, and, in An opening 221 exposing the storage unit 210 is provided above the two storage units 210 . Further, the two openings 221 communicate with each other to form an annular opening surrounding the common source line 240 .

Step S12, specifically referring to FIG. 4A and FIG. 4B , forming a first groove 111 and a second groove 121 in the word line lead-out region 100, the first groove 111 and the second groove 121 Both ends communicate with the opening 221. Since the annular opening in the device region 200 and the first groove 111 and the second groove 121 in the word line lead-out region 100 form an interconnected structure, so that the subsequent formation in the first groove 111 and the second groove The insulating layer in the groove 121 is connected with the isolation structure formed in the annular opening to form a large-area connecting body, thereby avoiding the formation of the first insulating layer or the second insulating layer as an independent structure with a small area. Preferably, both ends of the second groove 121 communicate with the opening 221 .

Wherein, in order to make the annular opening communicate with one end of the first groove 111 and the second groove 121, in this embodiment, by using the first layout and the second layout to define the annular opening and the The first groove 111 and the second groove 121, that is, use the first layout to perform a photolithography process to define the shape and position of the annular opening, and use the second layout to perform a photolithography process to define the second groove. The shapes and positions of the first groove 111 and the second groove 121. FIG. 4C is a projection pattern of the first layout and the second layout on the substrate used in the method for forming the flash memory in an embodiment of the present invention. Referring to FIG. 4C for details, the first layout 30 is included in the bright area The ring-shaped dark pattern 32 set in 31, the second layout 40 includes a first bar-shaped dark pattern 42 and a second bar-shaped dark pattern 43 set in the bright area 41. When the first layout 30 and the second layout are projected on the substrate, one end of the projection of the first dark strip 42 and the second dark strip 43 is connected to the projection of the annular dark pattern 32 connection, in this embodiment, both ends of the second strip-shaped dark pattern 43 are connected to the projections of two adjacent ring-shaped dark patterns 32 .

Specifically, the method for forming the annular opening, the first groove 111 and the second groove 121 may refer to the following steps: first, spin-coat photoresist on the first dielectric layer 400; then, use the Perform a photolithography process on the first layout 30 to remove the photoresist at the position where the annular opening needs to be formed; then, use an etching process to etch the first dielectric layer 400 to form the annular opening; secondly, similar to the above steps , using the second layout 40 to perform photolithography and etching processes, so that the first groove 111 and the second groove 121 are formed in the first dielectric layer 400 after etching.

Step S13 , specifically referring to FIG. 5A and FIG. 5B , filling the second dielectric layer 500 in the opening 221 , the first groove 111 and the second groove 121 . Preferably, the material of the second dielectric layer 500 may be silicon oxide. Further, the second dielectric layer 500 is formed by a high density plasma chemical vapor deposition process (High Density Plasma, HDP). Since the high-density plasma vapor deposition process can simultaneously deposit and etch the insulating medium in the reaction chamber, it realizes the excellent filling of the high depth ratio gap at a lower temperature, and the deposited insulating dielectric film has high density, low impurity defects, etc. Advantages, while having excellent adhesion to the substrate. Preferably, after the second dielectric layer 500 is formed, chemical mechanical polishing of the substrate is also included, so that the heights of the first dielectric layer 400 and the second dielectric layer 500 are consistent. On the other hand, it is also beneficial to Subsequent etching of the second dielectric layer 500 . Specifically, after the chemical mechanical polishing is performed, etching the second dielectric layer 500 is also included to remove the remaining second dielectric layer 500 on the common source line 240 and on the first dielectric layer 400 .

Step S14, specifically referring to FIGS. 6A and 6B , removes the first dielectric layer 400, forms the isolation structure 220 covering the memory cell 210, and forms the first insulating layer 110 and the second insulating layer 110 located in the word line lead-out region 100. layer 120 , one end of the first insulating layer 110 and the second insulating layer 120 are both connected to the isolation structure 220 . In this embodiment, both ends of the second insulating layer 120 in the word line lead-out region 100 are connected to the isolation structure 220 .

In this step, the first insulating layer 110 and the second insulating layer 120 can only be formed after the first dielectric layer 400 surrounding the second dielectric layer 500 is removed. However, in a conventional flash memory, the first insulating layer 110 or the second insulating layer 120 located in the word line lead-out region 100 is an isolated structure with a small area, and its adhesion to the substrate is weak, so after removal During the process of the first dielectric layer 400 or the subsequent process, the second dielectric layer 500 is prone to fall off, so that the complete first insulating layer 110 or the second insulating layer 120 cannot be formed finally. In the method for forming the flash memory provided by the present invention, the first insulating layer 110 and the second insulating layer 120 are formed to be connected to the isolation structure 220, and the first insulating layer 110 and the second insulating layer 120 are formed with the isolation structure 220. Integral, so that the adhesion of the first insulating layer 110 and the second insulating layer 120 on the substrate can be strengthened, and the phenomenon of detachment can be avoided.

Step S15, specifically referring to FIGS. 7A and 7B , depositing a conductive material on the substrate, and etching the conductive material, specifically, the conductive material may be polysilicon, and then forming the conductive material on the side of the isolation structure 220. The memory cell word line 230 and the contact word line 130 located in the word line lead-out area 100 are connected to form a word line strip 300 . In this embodiment, in the direction of the Y axis, two word line strips 300 formed by connecting the two memory cell word lines 230 in the device area in the same column to the contact word lines 130 in the two word line lead-out areas respectively, The two word line stripes 300 are combined to form a word line stripe pair. FIG. 8 is a schematic structural diagram of a word line band pair in a flash memory formed in an embodiment of the present invention. As shown in FIG. The belt pairs are parallel to each other. In addition, when the two word line straps 300 in the pair of word line straps are respectively located on both sides of the second insulating layer 120, since both ends of the second insulating layer 120 are connected to the isolation structure 220, therefore On the other hand, the second insulating layer 120 can be used to isolate two word line straps 300 in the pair of word line straps.

In addition, the present invention also provides a flash memory manufactured and formed according to the method for forming the flash memory described above, the layout structure of the flash memory includes at least one device area and at least one word line lead-out area; the device area includes At least one memory cell, an isolation structure covering the memory cell, and a memory cell word line formed on one side of the isolation structure; the word line lead-out region includes a first insulating layer, a second insulating layer, and a contact word line, so The contact word line is formed between the first insulating layer and the second insulating layer; at least one of the memory cell word lines is connected to at least one of the contact word lines to form a word line strip, and the first insulating One end of both the layer and the second insulating layer are connected to the isolation structure. In this way, neither the first insulating layer nor the second insulating layer is an isolated structure that exists independently, so that during the formation of the first insulating layer and the second insulating layer, or even in subsequent processes, it is possible to avoid The peeling off of the first insulating layer and the second insulating layer.

The structure of the flash memory proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Figure 9 is a top view of the structure of the flash memory in an embodiment of the present invention, Figure 10 is a cross-sectional view of the device region along the AA' direction in the structure of the flash memory in an embodiment of the present invention, and Figure 11 is a cross-sectional view of the flash memory in an embodiment of the present invention A cross-sectional view of the word line lead-out region along the BB' direction in the structure of the memory.

As shown in FIG. 9 and FIG. 10 , the flash memory includes at least one device area 200 and at least one word line lead-out area 100 . The device region 200 includes at least one memory cell 210 , an isolation structure 220 covering the memory cell 210 , and a memory cell word line 230 formed on one side of the isolation structure 220 . Further, the storage unit 210 includes a floating gate 211 and a control gate 212, and the floating gate 211 and the control gate 212 are isolated from each other. In this embodiment, the device region 200 has two memory cells 210 , and the device region 200 further includes a common source line 240 . The two storage units 210 are formed on both sides of the common source line 240, the two storage units 210 are covered with the isolation structure 220, and the two isolation structures 220 are far away from the common source One side of the line 240 is formed with the memory cell word line 230 . Further, as shown in FIG. 9 , the two isolation structures 220 are connected to each other to form a ring structure surrounding the common source line 240 , thereby effectively isolating the memory cell 210 and the memory cell word line 230 .

Referring to FIG. 11 and shown in FIG. 9 , the word line lead-out region 100 includes a first insulating layer 110 , a second insulating layer 120 and a contact word line 130 , and the contact word line 130 is formed on the first insulating layer 110 and the second insulating layer 120 , and one end of the first insulating layer 110 and the second insulating layer 120 are both connected to the isolation structure 220 . Wherein, the structure formed by the combination of the first insulating layer 110 and the second insulating layer 120 has an exit 140 through which the contact word line 130 is connected to the memory cell word line 230 . That is, in the structure of the flash memory provided by the present invention, on the basis of not affecting the lead-out of the word line of the memory cell and ensuring the normal storage function of the memory, by connecting one end of the first insulating layer 110 and one end of the second insulating layer 120 to the The isolation structure 220 is connected to increase the adhesion between the first insulating layer 110 and the second insulating layer 120 and the substrate, so as to prevent the first insulating layer or the second insulating layer from falling off during the formation of the flash memory. question.

In addition, in the structure of the flash memory memory provided by the present invention, at least one of the memory cell word lines 230 and at least one contact word line 130 are connected to form a word line strip 300, through which the word line strip 300 can then be located in the device region 100 The word line 230 of the memory cell in the memory cell is drawn out through the contact word line 130 located in the word line lead-out area 100 . Preferably, different memory cell word lines 230 located in the same device region 200 are connected to different contact word lines 130 . For example, in this embodiment, one device region 200 has two memory cell word lines 230, and the two memory cell word lines 230 are respectively connected to contact word lines 130 located in different word line lead-out regions 100 to form two memory cell word lines 230. A word line with 300.

Further, two word line stripes 300 in the same device region are connected to form a word line stripe pair. Specifically referring to FIG. 9 , in this embodiment, the word line band pair connects a plurality of device regions 200 and two word line lead-out areas 100, wherein one word line band 300 in the word line band pair is formed by One memory cell word line 230 of each device area in a plurality of device areas is connected with a contact word line 130 in a word lead-out area, and the other word line band 300 in the word line band pair is formed by the multiple Another memory cell word line 230 in each device area in the three device areas is connected to the contact word line 130 in another word line lead-out area. That is, each word line band 300 in the word line band pair is connected with a plurality of device regions 200 and a word line lead-out region 100, so that the memory cell word lines in the plurality of device regions can be realized through one contact word line 130 230 leads out. At the same time, in the plurality of device regions 200, two memory cell word lines 230 in the same device region 200 are respectively connected to two contact word lines 130 located in different word line lead-out regions 100 to form two word line strips 300 , so that the two memory cell word lines 230 in the same device region 200 can be controlled respectively through the two word line strips 300 . In this embodiment, the word line strip pairs are connected to three device regions and two word line lead-out regions, and in the three device regions, two memory cell word lines 230 in the same device region are respectively connected to Contact word lines 130 in different word line lead-out regions 100 are connected.

Continuing to refer to FIG. 9 , among the plurality of device regions in the word line strip pair, some of the device regions have a strip structure, and correspondingly, the common source line 240 and the memory cell word line 230 located in the device region The equalization is formed along the length direction of the device region of the strip structure. Further, a plurality of device regions and two word line lead-out regions are arranged along the length direction of the device regions of the strip structure to form a long strip structure, and the word line lead-out region is located between the two device regions. Specifically, in this embodiment, among the three device regions in the word line stripe pair, there are two device regions with a strip structure and one device region with a block structure, three device regions and two word The line lead-out areas are arranged at intervals, wherein the device area of the block structure is located in the middle of the two word line lead-out areas, and the device areas of the two strip structures are respectively located in the two word line lead-out areas away from the devices of the block structure. side of the area.

In a preferred scheme, the first insulating layer 110 and the second insulating layer 120 in the word line lead-out region 100 are both strip-shaped structures, wherein the first insulating layer 100 and the second insulating layer 120 are vertical to the The length direction of the device regions of the stripe structure is arranged in parallel, and one end of the first insulating layer 110 and the second insulating layer 120 are both connected to the adjacent isolation structure 220 . Further, as shown in FIG. 9 , both ends of the second insulating layer 120 are connected to adjacent isolation structures 220 . In this way, when the two word line strips 300 of the word line strip pair are respectively formed on both sides of the second insulating layer 120, the two word line strips 300 can be isolated by the second insulating layer 120. , meanwhile, since the other end of the first insulating layer 110 is not connected to other structures, the structure formed by the combination of the first insulating layer 110 and the second insulating layer 120 still has an outlet 140 through which the The outlet 140 can still realize the connection between the contact word line 130 and the memory cell word line 230 .

In this embodiment, since the two memory cell word lines 230 in the same device region 200 are respectively formed on the sides of the two isolation structures 220 away from the common source line 240, at the same time, the word lines are connected in pairs The three device regions and the two word line lead-out regions are arranged in a strip structure, so the three memory cell word lines 230 on the same side in the three device regions can be directly connected to one of the contact word lines 130, Further, two separate word line strips 300 are formed, and the two word line strips 300 form a pair of word line strips in a strip structure. Preferably, as shown in FIG. 9 , the flash memory provided by the present invention has multiple pairs of word line stripes, and the multiple pairs of word line stripes are arranged in parallel. In this embodiment, the device region and the word line lead-out region are arranged in a rectangular array, along the length direction of the device region of the strip structure, the memory cell word lines 230 located on both sides of the device region in the same column They are respectively connected to two contact word lines 130 to form a word line strap pair.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (20)

1. A method for forming a flash memory, comprising: S11. A substrate is provided, the substrate includes at least one device region and at least one word line lead-out region, and a first dielectric layer is covered on the device region and the word line lead-out region, and a first dielectric layer is formed on the device region There is at least one storage unit, and the first dielectric layer has an opening exposing the storage unit; S12, forming a first groove and a second groove in the lead-out region of the word line, one end of the first groove and the second groove both communicate with the opening; S13, filling the opening, the first groove and the second groove with a second dielectric layer; S14, removing the first dielectric layer, forming an isolation structure covering the memory cell and forming a first insulating layer and a second insulating layer located in the word line lead-out region, the first insulating layer and the second insulating layer One end of each is connected to the isolation structure; S15, deposit a conductive material on the substrate, and etch the conductive material to form a memory cell word line located on one side of the isolation structure and a contact word line located in the word line lead-out area, the memory cell word line and the contact word line The lines are connected to form a word line strip. 2. The method for forming a flash memory according to claim 1, wherein in S11, two memory cells and a common source line are formed on the device region, and the two memory cells are formed on the Both sides of the common source line have an opening above the two storage units exposing the storage units. 3. The method for forming a flash memory according to claim 2, wherein two of the openings communicate with each other to form an annular opening surrounding the common source line. 4 . The method for forming a flash memory according to claim 3 , wherein in S11 , a first layout is used to define the annular opening, and the first layout includes a ring-shaped dark pattern disposed in a bright area. 5. The method for forming a flash memory memory according to claim 4, wherein in S12, a second layout is used to define the first groove and the second groove of the word line lead-out region, and the second layout is included in The first dark bar pattern and the second dark bar pattern set in the light area. 6. The method for forming a flash memory according to claim 5, wherein when the first layout and the second layout are projected on the substrate, the projection of the first striped dark pattern and the One end of the projection of the second bar-shaped dark figure is connected with the projection of the ring-shaped dark figure. 7 . The method for forming a flash memory according to claim 1 , wherein in S13 , the second dielectric layer is formed by high-density plasma chemical vapor deposition. 8. The forming method of flash memory as claimed in claim 1, characterized in that: after S13, further comprising performing chemical mechanical polishing on the substrate filled with the second dielectric layer, so that the first dielectric layer and the second dielectric layer are The height of the medium layer is consistent. 9. The method for forming a flash memory according to claim 1, wherein the first dielectric layer is made of silicon nitride. 10. The method for forming a flash memory according to claim 1, wherein the second dielectric layer is made of silicon oxide. 11. A flash memory, comprising at least one device area and at least one word line lead-out area; the device area includes at least one storage unit, an isolation structure covering the storage unit and a storage unit formed on one side of the isolation structure word line; the word line lead-out region includes a first insulating layer, a second insulating layer and a contact word line, and the contact word line is formed between the first insulating layer and the second insulating layer; at least one of the storage The unit word line is connected to at least one of the contact word lines to form a word line strip, and it is characterized in that one end of the first insulating layer and the second insulating layer are both connected to the isolation structure. 12. The flash memory memory according to claim 11, wherein there are two storage units in the device area, and a common source line is also included in the device area, and the two storage units are formed on the common source line. On both sides of the source line, the two memory cells are covered with the isolation structure, and the word line of the memory cell is formed on the side of the two isolation structures away from the common source line. 13. The flash memory according to claim 12, wherein the two isolation structures are connected to each other to form a ring structure surrounding the common source line. 14. The flash memory memory according to claim 13, wherein the two memory cell word lines are respectively connected to contact word lines in different word line lead-out areas to form two word line strips, and the two word line The strips form a wordline strip pair. 15. The flash memory memory of claim 14, wherein the second insulating layer isolates two of the word line stripes. 16. The flash memory memory as claimed in claim 14, wherein the word line bands are connected to a plurality of device regions and two word line lead-out areas, wherein one word line band in the word line bands is formed by One memory cell word line of each device area in the plurality of device areas is formed by connecting the contact word line of a word line lead-out area, and the other word line band in the word line band pair is formed by the word line of the plurality of device areas Another memory cell word line in each device area is connected to another word line lead-out area contact word line, two memory cell word lines in the same device area are respectively connected to two word line lead-out areas contact word line connection. 17. The flash memory memory according to claim 16, characterized in that, among the plurality of device regions, some of the device regions have a strip structure, and the plurality of device regions and the two word line lead-out regions are arranged along the strip structure. The device regions of the strip structure are arranged in the length direction to form a long strip structure, and the word line lead-out region is located between two of the device regions. 18. The flash memory memory according to claim 17, wherein the first insulating layer and the second insulating layer are strip-shaped structures, and the first insulating layer and the second insulating layer are vertical to the strips. The length directions of the device regions of the structure are arranged in parallel. 19. The flash memory memory according to claim 18, wherein both ends of the second insulating layer are connected to adjacent isolation structures. 20. The flash memory memory according to claim 14, wherein the flash memory memory comprises a plurality of word line stripe pairs, and the plurality of word line stripe pairs are arranged in parallel.