JP2009253037A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of reducing the manufacturing cost and increasing the capacitance of a capacitance element portion, without increasing the chip size. <P>SOLUTION: The semiconductor device comprises a floating gate and a control gate. In the semiconductor device, the capacitance element portion comprises a gate insulating film 101, formed on a semiconductor substrate; a lower electrode 102c, formed on the gate insulating film 101; a cap insulating film 103, having an opening part formed on the lower electrode 102c which exposes the lower electrode 102c; an inter-gate insulating film 106, formed on the side surface of the cap insulating film 103 and on the lower electrode 102c exposed by the opening part; and a upper electrode 108 formed on the inter-gate insulating film 106. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device including a control gate provided on both sides of a floating gate via an inter-gate insulating film, and a method for manufacturing the semiconductor device.

  Conventional NAND-type nonvolatile semiconductor memory devices employ a structure in which a control gate is formed on a floating gate with an inter-gate insulating film interposed therebetween (hereinafter referred to as a “stacked gate type structure”). .

  In a NAND type nonvolatile semiconductor memory device having a stacked gate type structure, select gates are formed at both ends of a memory cell. In the selection gate, the floating gate and the control gate are connected through a contact formed in a part of the opening of the inter-gate insulating film, and as a result, the selection gate functions as a transistor instead of a stacked gate structure.

  In a NAND type nonvolatile semiconductor memory device having a stacked gate type structure, a contact formed in a part of an opening of an inter-gate insulating film is used in the same manner as a selection gate in order to form a capacitive element portion with high area efficiency. By forming a control gate connected to the floating gate as the first electrode and further forming a contact on the semiconductor substrate as the second electrode, the control gate partially cut off from the control gate used as the first electrode, By using the semiconductor substrate as the third electrode, both the capacitance between the floating gate and the control gate and the capacitance element used as the capacitance between the floating gate and the semiconductor substrate are formed.

  However, in the NAND-type nonvolatile semiconductor memory device having a stacked gate type structure, the process of dividing the control gate is performed separately from the process of forming the memory cell, so that the manufacturing cost increases.

  On the other hand, NAND-type nonvolatile semiconductor memory devices having memory cells having a structure in which a control gate is formed on a side surface of a floating gate are known (Patent Documents 1 and 2).

  In this NAND type nonvolatile semiconductor memory device, the capacitance between the floating gate and the control gate (hereinafter referred to as “coupling capacitance”) can be increased by increasing the height of the floating gate in the memory cell.

However, since the control gate does not exist on the floating gate, a capacitance is formed only between the floating gate and the semiconductor substrate in the capacitive element portion. Therefore, in order to increase the capacitance of the capacitive element portion, it is necessary to increase the area of the capacitive element portion. As a result, the chip size increases when the capacitance of the capacitive element portion is increased.
JP 2002-141469 A JP 2004-319948 A

  An object of the present invention is to reduce the manufacturing cost and increase the capacitance of the capacitive element portion without increasing the chip size.

According to the first aspect of the present invention,
A semiconductor device comprising a floating gate and a control gate,
In the capacitive element portion, a gate insulating film formed on the semiconductor substrate;
A lower electrode formed on the gate insulating film;
A cap insulating film formed on the lower electrode and having an opening exposing the lower electrode;
An inter-gate insulating film formed on a side surface of the cap insulating film and on the lower electrode exposed by the opening;
And a top electrode formed on the inter-gate insulating film. A semiconductor device is provided.

According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising a floating gate and a control gate,
In the capacitive element portion, a gate insulating film is formed on the semiconductor substrate,
Forming a lower electrode on the gate insulating film;
Forming a cap insulating film on the lower electrode;
Forming at least one opening in the cap insulating film;
Forming an inter-gate insulating film on the cap insulating film and in the opening;
A method of manufacturing a semiconductor device is provided, wherein an upper electrode is formed on the inter-gate insulating film.

  According to the present invention, it is possible to reduce the manufacturing cost and increase the capacitance of the capacitive element portion without increasing the chip size.

  Embodiments of the present invention will be described below with reference to the drawings. The following examples are one embodiment of the present invention and do not limit the scope of the present invention.

  First, Example 1 of the present invention will be described. Embodiment 1 of the present invention is an example in which an interlayer insulating film is formed between a lower electrode and an upper electrode of a capacitive element portion.

  Hereinafter, in Example 1 of the present invention, a memory cell region, a select gate region, and a capacitor of a NAND-type nonvolatile semiconductor memory including a floating gate and two control gates provided on both sides of the floating gate to be controlled An example of the element portion will be described.

  FIG. 1 is a circuit diagram showing a memory cell array of a sidewall gate type nonvolatile semiconductor memory and a part of its peripheral circuit.

  As shown in FIG. 1, the sidewall gate type nonvolatile semiconductor memory 11 is arranged in the memory cell array region 12, the selection gate region 13 adjacent to the memory cell array region 12, the memory cell array region 12, and the periphery of the selection gate region 13. Peripheral circuit region 14. In FIG. 1, in order to prevent complication of the drawing, only a part of the peripheral circuit region 14, for example, a part of the transfer gate transistor in the row decoder is shown.

  The peripheral circuit region 14, for example, the row decoder, selects two of the word lines (control gates) WL1 to WL9 and the selection gate lines SGD and SGS according to an address signal (not shown). Signals for selecting these are transmitted to the word lines WL1 to WL9, the selection gate lines SGD, and SGS via transistors TR1 to TR9 and transfer gate transistors TGTD and TGTS provided in the row decoder 13. The transistors TR1 to TR9, TGTD, and TGTS are formed as high-voltage transistors in order to pass the write potential at the time of writing, for example.

  The peripheral circuit region 13 also includes a voltage capacitor element portion used for generating a high voltage necessary for writing.

  The memory cell region 12 includes nine memory cell transistors MT commonly connected to any of the bit lines BL1 to BL6, and the selection gate region 13 includes selection transistors ST1 and ST2. Note that the number of memory cell transistors MT is not limited to 8, and may be, for example, 16 or 32, and both the selection transistors ST1 and ST2 are not necessarily required.

  FIG. 2 is a plan view showing the structure of the memory cell region, the select gate region, and the capacitor element portion of the semiconductor device according to the first embodiment of the present invention. 3A shows a cross section taken along line BB in FIG. 2, and FIG. 3B shows a cross section taken along line BB in FIG.

  First, a plan view of the semiconductor device according to the first embodiment of the present invention will be described.

  In the memory cell region, memory cells MC are arranged in a matrix. A selection gate 109 extending in the vertical direction in the drawing and an element isolation 104 extending in the horizontal direction in the drawing are formed between the memory cells MC.

  In the select gate region, select gate transistors ST are arranged at regular intervals in the vertical direction in the drawing. These selection gate transistors ST are separated by element isolation 104, and a gate electrode 102b of the selection gate transistor ST is connected by a selection gate 109 extending in the vertical direction in the drawing.

  In the capacitive element portion, an upper electrode 108 formed in an opening formed in the cap insulating film 103 is formed, and a contact 111c connected to the upper electrode 108, a contact 111b connected to the lower electrode 102c, and Contacts 111a connected to the semiconductor substrate 1 are formed.

  Next, a cross-sectional view of the semiconductor device according to the first embodiment of the present invention will be described.

  In the memory cell region, a floating gate electrode 102a formed via a gate insulating film 101 formed on the semiconductor substrate 1 and a cap insulating film 103 formed on the floating gate electrode 102a are formed. . A control gate electrode 107 for controlling the memory cell MC is formed between the memory cells via an inter-gate insulating film 106. By applying a voltage to the control gate electrode 107, charges can be accumulated in the memory cells MC, and the state of the charges accumulated in the memory cells MC can be read out. The intergate insulating film 106 is also formed between the control gate electrode 107 and the gate insulating film 101. With this configuration, the breakdown voltage between the control gate electrode 107 and the semiconductor substrate 1 is improved.

  In the selection gate region, the selection gate transistor ST is formed through a gate insulating film 101 formed on the semiconductor substrate 1, and a gate electrode 102b made of the same material as the floating gate electrode 102a is formed on the gate electrode 102b. And a cap insulating film 103 formed. In the cap insulating film 103, a control gate electrode 109 is formed in the trench. An inter-gate insulating film 106 is formed on the side surface of the control gate transistor on the memory cell side, and an interlayer insulating film 105 is formed on the other side surface.

  In the capacitive element portion, a lower gate electrode 102c made of the same material as that of the floating gate electrode 102a is formed via the gate insulating film 101. A cap insulating film 103 having an opening is formed on the lower gate electrode 102c. An upper electrode 108 is formed in the opening via an inter-gate insulating film 106.

  As shown in FIG. 3B, the contact 111b connected to the lower gate electrode 102c is composed of a conductor formed in an opening formed in the cap insulating film 103. The contact 111 a connected to the semiconductor substrate 1 is made of a conductor formed in an opening formed in the interlayer insulating film 105. The contact 111b may be made of the same material as the selection gate 109.

  For example, by applying 0 V to the contacts 111a and 111c and 5V to the contact 111b, a capacitor element using the gate insulating film 101 and the inter-gate insulating film 106 as insulating films can be formed.

  4A and 4B are a plan view and a cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 4B shows a cross section taken along the line AA in FIG.

  First, a gate insulating film (tunnel insulating film) 101 is formed on a semiconductor substrate (not shown). Next, using a chemical vapor deposition method (hereinafter referred to as “CVD (Chemical Vapor Deposition) method”), for example, a doped polysilicon 102 and a cap insulating film (for example, a silicon nitride film) are formed on the gate insulating film 101. ) 103 are sequentially deposited. Next, using a lithography technique, a resist pattern for the element isolation 104 extending in the lateral direction is formed in the memory cell region and the select gate region in FIG. 4A. For example, a cap insulating film is formed using a dry etching method. 103, the doped polysilicon film 102, the gate insulating film 101, and the semiconductor substrate are etched, and the resist pattern is removed using, for example, an ashing method to form a groove pattern for the element isolation 104 that reaches the semiconductor substrate. Form. Next, using a CVD method or a coating method, for example, a silicon oxide film (not shown) is embedded in the groove pattern for the element isolation 104, for example, a chemical mechanical polishing method (hereinafter referred to as “CMP (Chemical Mechanical Polish) method”). The excess silicon oxide film is removed using the cap insulating film 103 as a stopper. After the above steps, the structure of FIG. 4 is formed.

  5A and 5B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 4 of the method for manufacturing a semiconductor device according to the first embodiment of the invention. FIG. 5B shows a cross section taken along line AA in FIG.

  Subsequently to FIG. 4, a resist pattern for processing between the peripheral transistor (not shown), the selection gate region, and the capacitor element portion is formed, and for example, a dry etching method is used to form the cap insulating film 103 and the element isolation 104. The upper portion of the silicon oxide film embedded in the trench and the doped polysilicon film 102 are etched, and the resist pattern is removed using, for example, an ashing method. After the above steps, the structure of FIG. 5 is formed.

  6A and 6B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 5 in the method for manufacturing a semiconductor device according to the first embodiment of the invention. FIG. 6B shows a cross section taken along line AA in FIG.

  5A and 5B, an ion implantation process and an activation process for forming peripheral transistors are performed, and a silicon oxide film, for example, is deposited as the interlayer insulating film 105 by using a CVD method or a coating method, and a CMP method is performed. Then, planarization is performed using the cap insulating film 103 as a stopper. After the above steps, the structure of FIG. 6 is formed.

  7A and 7B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 3 in the method for manufacturing a semiconductor device according to the first embodiment of the invention. FIG. 7B shows a cross section taken along line AA in FIG.

  6A and 6B, in order to process the memory cell, a resist pattern extending in the vertical direction is formed in the memory cell region of FIG. 7A. For example, the cap insulating film 103 and the element isolation 104 are formed by using a dry etching method. The upper portion of the interlayer insulating film 105 and the doped polysilicon film 102 embedded in the trench for etching are etched, and the resist pattern is removed using an ashing method. After the above steps, the structure of FIG. 7 is formed.

  8A and 8B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 7 in the semiconductor device manufacturing method according to the first embodiment of the invention. FIG. 8B shows a cross section taken along line AA in FIG.

  Following FIG. 7, a resist pattern for processing the cap insulating film 103 on the upper part of the capacitor element portion is formed, the cap insulating film 103 is etched using a dry etching method, and the resist pattern is etched using an ashing method. Remove. After the above steps, a cap insulating film 103 (structure shown in FIG. 8) having an opening exposing the upper surface of doped polysilicon film 102 is formed.

  9A and 9B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 8 of the method for manufacturing a semiconductor device according to the first embodiment of the invention. FIG. 9B shows a cross section taken along line AA in FIG.

  Following the deposition of the inter-gate insulating film 106 on the entire surface by using, for example, the CVD method, the floating gate electrode 102a of the memory cell, the gate electrode 102b of the selection gate, and the lower electrode 102c of the capacitive element portion are formed. Then, an inter-gate insulating film 106 (structure of FIG. 9) made of, for example, an ONO film (a laminated film of silicon oxide film-silicon nitride film-silicon oxide film) is formed so as to cover the inside of the opening of the capacitive element portion. The

  10A and 10B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 9 in the method for manufacturing a semiconductor device according to Example 1 of the invention. FIG. 10B shows a cross section taken along line AA in FIG.

  Subsequent to FIG. 9, for example, a doped polysilicon film is deposited using a CVD method, and unnecessary portions of the doped polysilicon film are removed using a CMP method or a dry etching method. The control gate electrode 107 in the region is formed, and at the same time, the upper electrode 108 is formed through the inter-gate insulating film 106 in the opening above the capacitor element portion. After the above steps, the structure of FIG. 10 is formed.

  11A and 11B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 10 in the method for manufacturing the semiconductor device according to the first embodiment of the invention.

  Subsequently to FIG. 10, a resist pattern for forming the selection gate 109 is formed. For example, after the cap insulating film 103 is etched using a dry etching method to form a groove exposing the doped polysilicon film 102 (FIG. 10), the resist pattern is removed using, for example, an ashing method. Then, for example, by depositing doped polysilicon using a CVD method, and using a CMP method or a dry etching method, leaving the doped polysilicon inside the trench and removing the excess portion, thereby selecting the gate. A selection gate 109 for connecting the gate electrode 102b in the region with a doped polysilicon wiring is formed. In this step, the lower portion of the contact 111b can be formed at the same time by removing a part of the cap insulating film 103 in the capacitor element portion at the same time.

  In Example 1 of the present invention, it is preferable to remove the inter-gate insulating film 106 on the cap insulating film 103. This is to reduce the leakage current between adjacent memory cell transistors MT. After the above steps, the structure of FIG. 11 is formed.

  12A and 12B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 11 in the method for manufacturing a semiconductor device according to the first embodiment of the invention.

  Subsequently to FIG. 11, a silicon oxide film is deposited as an interlayer insulating film by using the CVD method, and reaches the silicon substrate 1, the doped polysilicon 102, the not-shown doped polysilicon wiring, and the upper electrode 108. Contacts 111a-c are formed. After the above steps, the structure of FIG. 12 is formed. When the selection gate 109 and the lower part of the contact 111b are formed at the same time, the upper part of the contact 111b connected to the upper surface of the lower part of the contact 111b is formed.

  Continuing to FIG. 12, an NAND type nonvolatile semiconductor memory is formed by forming an upper wiring layer.

  According to the first embodiment of the present invention, in the memory cell region, the floating gate electrode 102a is controlled by the control gate electrodes 107 formed on both side surfaces thereof, so that the floating gate electrode 102a is made thick by increasing its thickness. The area of the inter-gate insulating film 106 sandwiched between the gate electrode 102a and the control gate electrode 107 can be increased. As a result, the coupling capacity can be increased.

  Further, according to the first embodiment of the present invention, in the capacitor element portion, in addition to the gate insulating film 101 sandwiched between the lower electrode 102c and the semiconductor substrate 1 serving as a capacitor, the lower electrode 102c and the upper electrode 108 are used. Since the inter-gate insulating film 106 sandwiched between the electrodes can also be used as a capacitor, the area necessary for securing the capacitance of the capacitor element portion can be reduced, thereby reducing the chip size and reducing the cost. be able to.

  In the first embodiment of the present invention, an example in which all the upper electrodes 108 are formed on the floating gate electrode 102a has been described. However, a part of the upper electrode 108 is drawn on the element isolation 104 and contacted with the upper electrode 108. 111 may be taken. In this case, it is possible to prevent the processing damage from affecting the inter-gate insulating film 106 and the gate insulating film 101 when the contact 111 to the upper electrode 108 is formed.

  Next, a second embodiment of the present invention will be described. The first embodiment of the present invention is an example in which an interlayer insulating film is formed between the lower electrode and the upper electrode of the capacitive element portion. However, the second embodiment of the present invention is the upper electrode and the lower electrode of the repeating pattern connected to each other. In this example, an interlayer insulating film is formed between electrodes. In addition, the description about the content similar to Example 1 of this invention is abbreviate | omitted.

  First, in Example 2 of the present invention, the same processes as in FIGS.

  13A and 13B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 7 in the method for manufacturing a semiconductor device according to Example 2 of the invention. FIG. 13B shows a cross section taken along line AA in FIG.

  Subsequently to FIG. 7, a resist pattern for processing the cap insulating film 103 on the upper part of the capacitive element portion is formed. The resist pattern is, for example, a repeated pattern in which resist lines and resist spaces are alternately formed at predetermined intervals in the horizontal direction in FIG. The resist spaces are connected to each other by a connection space. As a result, this resist pattern has a shape having at least five corners.

  Thereafter, similarly to Example 1 of the present invention, the cap insulating film 103, the upper portion of the interlayer insulating film 105 buried in the trench for element isolation 104 (not shown), and the doped polysilicon film 102 are formed by using a dry etching method. Etching and removing the resist pattern using an ashing method. After the above steps, the structure of FIG. 13 is formed.

  Subsequent to FIG. 13, the same processes (FIGS. 8 to 12) as in the first embodiment of the present invention are performed to form a NAND-type nonvolatile semiconductor memory as shown in FIG.

  According to the second embodiment of the present invention, the upper electrode 108 having a repetitive pattern narrower than that of the first embodiment of the present invention is formed on the upper portion of the capacitive element portion. Therefore, the upper electrode 108 can be easily formed. it can. Specifically, when the pattern width of the upper electrode 108 is wide, dishing occurs when the doped polysilicon film deposited to form the upper electrode 108 is polished by CMP. Although there is a problem that the doped polysilicon of the upper electrode 108 is lost, in the second embodiment of the present invention, since the width of the upper electrode 108 is narrow, the influence of dishing can be reduced. In addition, when the doped polysilicon is etched by using a dry etching method instead of the CMP method, if the upper electrode 108 is wide, the deposited doped polysilicon film thickness is flattened. Since the film must be formed thick, there is a problem that the cost of film formation and etching increases and the control of etching becomes difficult. However, in the second embodiment of the present invention, the width of the upper electrode 108 is narrow. There is no problem.

  Further, according to the second embodiment of the present invention, since the upper electrode 108 has a narrow repeated pattern, it is possible to compensate for the reduced capacitance by reducing the electrode width in order to solve the above problem.

  That is, according to the second embodiment of the present invention, the capacitance between the floating gate electrode 102a and the control gate electrode 107 is formed by forming the interlayer insulating film 105 between the upper electrode 108 and the lower electrode 102c having a repetitive pattern. The above problem can be solved.

  Further, according to the second embodiment of the present invention, by having the connection electrode, it is possible to supply a potential to the plurality of upper electrodes 108 with a small number of contacts.

  In the second embodiment of the present invention, the lithographic imaging can be improved by making the pattern of the upper electrode 108 a simple pattern of lines and spaces. In this case, a contact 111 is disposed on each upper electrode 108 and they are connected by an upper wiring (not shown).

  Next, Embodiment 3 of the present invention will be described. The second embodiment of the present invention is an example of etching up to the boundary between the silicon nitride film and the doped polysilicon, but the third embodiment of the present invention is an example of etching to the middle of the floating gate of the capacitive element portion. In addition, the description about the content similar to Example 1, 2 of this invention is abbreviate | omitted.

  First, in Example 3 of the present invention, the same processes as in FIGS.

  15A and 15B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 7 in the method for manufacturing a semiconductor device according to Example 3 of the invention. FIG. 15B shows a cross section taken along line AA in FIG.

  Subsequent to FIG. 7, a resist pattern for processing the cap insulating film 103 on the upper part of the capacitive element portion is formed in the same manner as in the second embodiment of the present invention. The resist pattern is a repeated pattern and a connection space in which resist lines and resist spaces are alternately formed. Thereafter, the cap insulating film 103, the upper part of the interlayer insulating film 105 buried in the trench for element isolation 104, and the doped polysilicon film 102 are etched using the dry etching method, as in the first embodiment of the present invention. Then, the resist pattern is removed using an ashing method. At this time, it is dug down partway through the doped polysilicon film 102 of the floating gate of the capacitive element portion. After the above steps, the structure of FIG. 15 is formed.

  Subsequent to FIG. 15, the same processes (FIGS. 8 to 12) as in the first embodiment of the present invention are performed to form a NAND-type nonvolatile semiconductor memory as shown in FIG.

  According to the third embodiment of the present invention, the upper electrode 108 is formed by digging partway through the doped polysilicon film 102 of the floating gate of the capacitive element portion (that is, deeper than the lower surface of the cap insulating film 103). The inter-gate insulating film 106 formed on the side surface 102c can also be used as an insulating film of a capacitor element using the lower electrode 102c and the upper electrode 108 as electrodes. As a result, the capacitance of the capacitive element can be made larger than that of the second embodiment of the present invention.

  Next, a fourth embodiment of the present invention will be described. The third embodiment of the present invention is an example of etching halfway through the floating gate of the capacitive element portion, but the fourth embodiment of the present invention is the boundary between the tunnel insulating film and the doped polysilicon film of the floating gate of the capacitive element portion. This is an example of etching. In addition, the description about the content similar to Examples 1-3 of this invention is abbreviate | omitted.

  First, in Example 4 of the present invention, the same processes as in FIGS.

  17A and 17B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 7 in the semiconductor device manufacturing method according to the fourth embodiment of the invention. FIG. 17B shows a cross section taken along line AA in FIG.

  Subsequent to FIG. 4, a resist pattern for processing the cap insulating film 103 on the upper part of the capacitive element portion is formed as in the second embodiment of the present invention. The resist pattern is a repeated pattern and a connection space in which resist lines and resist spaces are alternately formed. Thereafter, the cap insulating film 103, the upper part of the interlayer insulating film 105 buried in the trench for element isolation 104, and the doped polysilicon film 102 are etched using the dry etching method, as in the first embodiment of the present invention. Then, the resist pattern is removed using an ashing method. At this time, the upper surface of the gate insulating film 101 of the floating gate of the capacitive element portion is dug down. After the above steps, the structure of FIG. 17 is formed.

  Subsequent to FIG. 17, the same processes (FIGS. 8 to 12) as in the first embodiment of the present invention are performed to form a NAND-type nonvolatile semiconductor memory as shown in FIG.

  According to the fourth embodiment of the present invention, the upper electrode 108 is formed by digging down to the upper surfaces of the gate insulating film 101 and the floating gate of the capacitive element portion (that is, deeper than the third embodiment of the present invention). The inter-gate insulating film 106 formed on the side surface and having a width equal to the film thickness of the lower electrode 102c can also be used as an insulating film of a capacitor element using the lower electrode 102c and the upper electrode 108 as electrodes. As a result, it can be made larger than that of the third embodiment of the present invention.

  Further, according to the fourth embodiment of the present invention, the upper electrode 108 is formed by digging down to the upper surfaces of the gate insulating film 101 and the floating gate of the capacitive element portion, that is, the lower electrode 102c in the opening of the cap insulating film 103 is entirely Since the etching is performed, the variation in the capacitance value can be reduced as compared with the third embodiment of the present invention.

  Next, a fifth embodiment of the present invention will be described. Embodiments 1 to 4 of the present invention are examples in which a resist pattern for processing a memory and a resist pattern for processing a silicon nitride film on the upper part of the capacitive element portion are separately formed. 5 is an example of forming these simultaneously. In addition, the description about the content similar to Examples 1-4 of this invention is abbreviate | omitted.

  First, in Example 5 of the present invention, the same steps as in FIGS.

  FIG. 19 is a plan view and a cross-sectional view showing a step following the step of FIG. 6 of the method for manufacturing a semiconductor device according to Example 5 of the present invention. FIG. 19B shows a cross section taken along line AA in FIG.

  Subsequently to FIG. 6, a resist pattern for processing the memory cell and a resist pattern for processing the cap insulating film 103 above the capacitor element portion are formed simultaneously. The resist pattern for processing the cap insulating film 103 is a repeated pattern in which resist lines and resist spaces are alternately formed, as in the second embodiment of the present invention. Thereafter, the cap insulating film 103, the upper part of the interlayer insulating film 105 buried in the trench for element isolation 104, and the doped polysilicon film 102 are etched using the dry etching method, as in the first embodiment of the present invention. Then, the resist pattern is removed using an ashing method. At this time, it is dug down to the upper surface of the floating gate of the capacitive element portion. After the above steps, the structure of FIG. 19 is formed.

  20 is a plan view and a cross-sectional view showing a step following the step of FIG. 19 of the method for manufacturing a semiconductor device according to Example 5 of the present invention. FIG. 20B shows a cross section taken along line AA in FIG.

  Subsequently to FIG. 19, an inter-gate insulating film 106 is deposited by CVD. After the above steps, the structure of FIG. 20 is formed.

  21 is a plan view and a cross-sectional view showing a step following the step of FIG. 20 of the method for manufacturing the semiconductor device according to Example 5 of the present invention. FIG. 21B shows a cross section taken along line AA in FIG.

  Following FIG. 20, a doped polysilicon film is deposited using a CVD method, and unnecessary portions of the doped polysilicon film are removed using a CMP method or a dry etching method. The control gate electrode 107 is formed, and at the same time, the upper electrode 108 is formed on the side surface of the capacitive element portion via the inter-gate insulating film 106. After the above steps, the structure of FIG. 21 is formed.

  Subsequent to FIG. 21, the same process (FIGS. 11 and 12) as in the first embodiment of the present invention is performed to form a NAND type nonvolatile semiconductor memory.

  According to the fifth embodiment of the present invention, the resist pattern for processing the memory and the resist pattern for processing the silicon nitride film on the upper portion of the capacitive element portion are simultaneously formed (that is, the upper electrode 108 of the capacitive element portion). Is formed at the same time as the control gate electrode 107 in the memory cell region), the lithography process for forming the capacitive element portion can be omitted, and the manufacturing cost is reduced as compared with the first to fourth embodiments of the present invention. be able to. In particular, by setting the pitch of the upper electrodes 108 of the capacitive element portion to be the same as the pitch of the memory cell region, it is not necessary to form two types of wiring pitches at the time of lithography, so that it becomes easy to ensure a lithography process margin.

It is a circuit diagram showing a memory cell array of a sidewall gate type nonvolatile semiconductor memory and a part of its peripheral circuit. 3 is a plan view showing structures of a memory cell region, a select gate region, and a capacitor element portion of the semiconductor device according to Example 1 of the invention. FIG. FIG. 3 is a sectional view showing a section of the semiconductor device of FIG. It is the top view and sectional drawing which show 1 process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. 5A and 5B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 4 in the method for manufacturing a semiconductor device according to the first embodiment of the invention. 6A and 6B are a plan view and a cross-sectional view illustrating a process following the process shown in FIG. FIG. 7 is a plan view and a cross-sectional view showing a step following the step of FIG. 6 of the method for manufacturing a semiconductor device according to Example 1 of the present invention. 8A and 9B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 7 in the method for manufacturing a semiconductor device according to Example 1 of the invention. FIG. 9 is a plan view and a cross-sectional view showing a step following the step of FIG. 8 of the method for manufacturing a semiconductor device according to Example 1 of the present invention. FIG. 10 is a plan view and a cross-sectional view showing a step following the step of FIG. 9 of the method for manufacturing a semiconductor device according to Example 1 of the present invention. FIG. 11 is a plan view and a cross-sectional view showing a step following the step of FIG. 10 of the method for manufacturing the semiconductor device according to the first embodiment of the invention. It is the top view and sectional drawing which show the process following FIG. 11 of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. 8A and 8B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 7 in the method for manufacturing a semiconductor device according to Example 2 of the invention. It is the top view and sectional drawing which show the process following FIG. 13 of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. 8A and 8B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 7 in the method for manufacturing a semiconductor device according to Example 3 of the invention. 16A and 16B are a plan view and a cross-sectional view showing a process following the process shown in FIG. 15 in the method for manufacturing a semiconductor device according to Example 3 of the invention. FIG. 9 is a plan view and a cross-sectional view showing a step following the step of FIG. 7 of the method for manufacturing a semiconductor device according to Example 4 of the present invention. FIG. 18 is a plan view and a cross-sectional view showing a step following the step of FIG. 17 of the method for manufacturing a semiconductor device according to Example 4 of the present invention. FIG. 9 is a plan view and a cross-sectional view showing a step following the step of FIG. 6 of the method for manufacturing a semiconductor device according to Example 5 of the present invention. FIG. 20 is a plan view and a cross-sectional view showing a step following the step of FIG. 19 of the method for manufacturing a semiconductor device according to Example 5 of the present invention. FIG. 21 is a plan view and a cross-sectional view showing a step following the step of FIG. 20 in the method for manufacturing a semiconductor device according to Example 5 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 101 Gate insulating film 102 Doped polysilicon 102a Floating gate electrode 102b Gate electrode 102c Lower electrode 103 Cap insulating film 104 Element isolation 105 Interlayer insulating film 106 Intergate insulating film 107 Control gate electrode 108 Upper electrode 109 Select gate 111a c Contact ST Select gate transistor MC Memory cell

Claims (5)

A semiconductor device comprising a floating gate and a control gate,
In the capacitive element portion, a gate insulating film formed on the semiconductor substrate;
A lower electrode formed on the gate insulating film;
A cap insulating film formed on the lower electrode and having an opening exposing the lower electrode;
An inter-gate insulating film formed on a side surface of the cap insulating film and on the lower electrode exposed by the opening;
And a top electrode formed on the inter-gate insulating film.   The semiconductor device according to claim 1, wherein the opening of the cap insulating film has a shape having at least five corners.   3. The semiconductor device according to claim 1, wherein an upper surface of the lower electrode exposed by the opening is lower than a lower surface of the cap insulating film. A floating gate formed on the gate insulating film and disposed at a predetermined interval;
4. The semiconductor device according to claim 1, further comprising a control gate formed between the floating gates through the inter-gate insulating film. 5. A method of manufacturing a semiconductor device including a floating gate and a control gate,
In the capacitive element portion, a gate insulating film is formed on the semiconductor substrate,
Forming a lower electrode on the gate insulating film;
Forming a cap insulating film on the lower electrode;
Forming at least one opening in the cap insulating film;
Forming an intergate insulating film on the cap insulating film and in the opening;
A method of manufacturing a semiconductor device, comprising forming an upper electrode on the inter-gate insulating film.

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