CN106159030B - The preparation method of solar cell - Google Patents

Abstract

The invention discloses a manufacturing method of a solar cell, which includes the following steps: providing a semiconductor substrate, the semiconductor substrate has a side surface, a first surface and a second surface opposite to each other, and a release layer is formed on the side surface. A first semiconductor layer and a first doped semiconductor layer are sequentially formed on the first surface, and a second semiconductor layer and a second doped semiconductor layer are sequentially formed on the second surface. A transparent conductive layer is formed on the first doped semiconductor layer and the second doped semiconductor layer, and the transparent conductive layer at least partially covers the release layer. The release layer is separated from the semiconductor substrate to remove the release layer and the transparent conductive layer covering the release layer.

Description

How to make a solar cell

technical field

The invention relates to a method for manufacturing a solar cell, in particular to a method for manufacturing a solar cell that increases the coverage of a transparent conductive layer on a semiconductor substrate.

Background technique

Due to the limited oil resources on earth, the demand for alternative energy has been increasing in recent years. Among all kinds of alternative energy sources, solar energy has become the green energy with the most development potential because it can rely on the cycle of nature and has an endless supply. However, due to problems such as high production cost, complex production process and poor photoelectric conversion efficiency, the development of solar energy still needs further breakthroughs.

At present, the solar cell technologies mainly developed can be roughly divided into silicon crystal solar cells, thin film solar cells, concentrator (HCPV) solar cells, dye sensitized Soloar Cell (DSSC) solar cells and other types. Among them, silicon solar cells have the highest market share in the current market due to their high efficiency and large production capacity. In recent years, high-efficiency heterojunction silicon solar cells are the focus of everyone's development. In general heterojunction silicon solar cells, the transparent electrodes on the upper and lower surfaces of the silicon substrate are coated to avoid interconnection. For direct conduction, it is generally necessary to keep a safe distance between the formed transparent conductive layer and the edge of the silicon substrate. Under this design, the silicon substrate and other semiconductor materials formed thereon cannot be fully utilized for photoelectric conversion, and thus the photoelectric conversion efficiency of the solar cell cannot be effectively improved.

Contents of the invention

One of the main purposes of the present invention is to provide a method for manufacturing a heterojunction solar cell, which is used to form a release layer on the side of the semiconductor substrate, so that the transparent conductive layer can be fully formed on the upper and lower surfaces of the semiconductor substrate and the release layer On top of that, the transparent conductive layer on the upper and lower surfaces is electrically isolated by separating the release layer from the semiconductor substrate, so that the coverage of the transparent conductive layer on the semiconductor substrate can be increased, thereby achieving the purpose of improving the photoelectric conversion effect of the solar cell.

In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing a solar cell, comprising the following steps: firstly, a semiconductor substrate is provided, the semiconductor substrate has a side surface and a first surface and a second surface opposite to each other, and on the side surface A release layer is formed. Then, a first semiconductor layer and a first doped semiconductor layer are sequentially formed on the first surface, and a second semiconductor layer and a second doped semiconductor layer are sequentially formed on the second surface. Then, a transparent conductive layer is formed on the first doped semiconductor layer and the second doped semiconductor layer, and the transparent conductive layer at least partially covers the release layer. After that, the release layer is separated from the semiconductor substrate to remove the release layer and the transparent conductive layer covering the release layer.

To achieve the above object, another embodiment of the present invention provides a method for fabricating a solar cell, including the following steps: firstly, a semiconductor substrate is provided, and the semiconductor substrate has a side surface and a first surface and a second surface opposite to each other. Then, a first semiconductor layer and a first doped semiconductor layer are sequentially formed on the first surface, and a second semiconductor layer and a second doped semiconductor layer are sequentially formed on the second surface. Then, a release layer is formed on the side of the semiconductor substrate. Next, a transparent conductive layer is formed on the first doped semiconductor layer and the second doped semiconductor layer, and the transparent conductive layer at least partially covers the release layer. After that, the release layer is separated from the semiconductor substrate to remove the release layer and the transparent conductive layer covering the release layer.

Description of drawings

1 to 8 are schematic diagrams illustrating a method for fabricating a solar cell according to a first embodiment of the present invention.

FIG. 9 and FIG. 10 are schematic diagrams illustrating the manufacturing method of the solar cell according to the second embodiment of the present invention.

FIG. 11 to FIG. 14 are schematic diagrams illustrating the manufacturing method of the solar cell according to the third embodiment of the present invention.

FIG. 15 is a schematic diagram of a method for fabricating a solar cell according to a fourth embodiment of the present invention.

[Description of Reference Signs]

1 Silicon Pillar

1S surface

10 Semiconductor substrate

10A First side

10B Second side

10S side

11 release layer

21 First semiconductor layer

22 The first doped semiconductor layer

31 Second semiconductor layer

32 Second doped semiconductor layer

40 transparent conductive layer

41 First electrode

42 Second electrode

51 First conductive pattern

52 Second conductive pattern

101 solar cells

102 solar cells

H horizontal direction

Z vertical projection direction

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

Please refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are schematic diagrams illustrating a method of manufacturing a solar cell according to a first embodiment of the present invention, wherein FIG. sectional schematic diagram. For the convenience of description, the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. This embodiment provides a method for manufacturing a solar cell, which includes the following steps: first, as shown in FIG. 1 and FIG. 2 , a semiconductor substrate 10 is provided. The face 10B, the side 10S surround the semiconductor substrate 10 . The first surface 10A and the second surface 10B are two opposite surfaces in a vertical projection direction Z, and the side surface 10S can be regarded as facing a horizontal direction H, which is substantially perpendicular to the vertical projection direction Z, but not This is the limit. A release layer 11 is formed on the side 10S, and the release layer 11 may include photoresist, glue or other suitable release materials. The semiconductor substrate 10 of the present embodiment may include a crystalline silicon semiconductor substrate such as single crystal silicon or polycrystalline silicon semiconductor substrate, but is not limited thereto. When the semiconductor substrate 10 is a crystalline silicon semiconductor substrate, it can be formed by cutting a silicon crystal pillar (ingot). According to different requirements, the cross section of the silicon crystal pillar can be circle, pseudo square, Shapes such as square and hexagon. Therefore, the release layer 11 can be formed on the side surface 10S of the semiconductor substrate 10 after the semiconductor substrate 10 is cut and shaped. Alternatively, as shown in FIGS. 3 and 2 , the release layer 11 can be formed on the surface 1S of the silicon column 1 first, and then the semiconductor substrate 10 with the release layer 11 on the side 10S is formed by cutting the silicon column 1 .

Then, as shown in FIG. 4, the semiconductor substrate 10 can be selectively roughened (texturing), so that the first surface 10A and the second surface 10B of the semiconductor substrate 10 can be transformed into a roughened surface, thereby reducing the reflected light ratio. , but not limited to this. The roughening process may include an etching process using an etchant (eg, potassium hydroxide) or other suitable roughening processes.

Next, as shown in FIG. 5, the first semiconductor layer 21 and the first doped semiconductor layer 22 are sequentially formed on the first surface 10A of the semiconductor substrate 10, and are sequentially formed on the second surface 10B as shown in FIG. The second semiconductor layer 31 and the second doped semiconductor layer 32 . In this embodiment, the first doped semiconductor layer 22 and the second doped semiconductor layer 32 preferably have different doping types, for example, the first doped semiconductor layer 22 can be n-type doped amorphous For the silicon layer, the second doped semiconductor layer 32 can be a p-type doped amorphous silicon layer, and the first semiconductor layer 21 and the second semiconductor layer 31 can be respectively amorphous silicon intrinsic semiconductor layers, but not limited thereto. In addition, under the above conditions, the semiconductor substrate 10 is preferably an n-type single crystal silicon substrate, thereby forming a heterojunction (heterojunction, HJT) silicon solar cell structure, but not limited thereto. The first semiconductor layer 21, the first doped semiconductor layer 22, the second semiconductor layer 31, and the second doped semiconductor layer 32 can be formed by chemical vapor deposition (chemical vapor deposition, CVD), such as plasma-assisted chemical deposition. Vapor phase deposition (PECVD), but not limited thereto. In other words, the above roughening treatment is performed before the formation of the first semiconductor layer 21 , the first doped semiconductor layer 22 , the second semiconductor layer 31 and the second doped semiconductor layer 32 .

In addition, it is worth noting that in order to increase the area of the first semiconductor layer 21 and the first doped semiconductor layer 22 covering the first surface 10A of the semiconductor substrate 10 as much as possible, the first semiconductor layer 21 and the first doped semiconductor layer 22 can fully cover the first surface 10A of the semiconductor substrate 10 and can extend to partially cover the release layer 11 . Similarly, in order to increase the area covered by the second semiconductor layer 31 and the second doped semiconductor layer 32 on the second surface 10B of the semiconductor substrate 10 as much as possible, the second semiconductor layer 31 and the second doped semiconductor layer 32 can fully cover The second surface 10B of the semiconductor substrate 10 can also extend to partially cover the release layer 11 . Therefore, the first semiconductor layer 21 and the first doped semiconductor layer 22 can partially overlap with the second semiconductor layer 31 and the second doped semiconductor layer 32 on the release layer 11 , but it is not limited thereto.

Then, as shown in FIG. 7 , a transparent conductive layer 40 is formed on the first doped semiconductor layer 22 and the second doped semiconductor layer 32 , and the transparent conductive layer 40 at least partially covers the release layer 11 . The transparent conductive layer 40 may include indium tin oxide (ITO), indium tungsten oxide (IWO), indium cerium oxide (ICO), indium zinc oxide (IZO) and oxide Aluminum zinc oxide (AZO) or other suitable transparent conductive materials. In order to increase the electrical and optical properties of transparent conductive materials, hydrogen atoms can be added to the above materials. The transparent conductive layer 40 may be formed by a coating method such as sputtering or reactive plasma deposition (RPD), but not limited thereto. It is worth noting that, in other embodiments of the present invention, the transparent conductive layers formed on the first doped semiconductor layer 22 and the second doped semiconductor layer 32 may also use different materials as required and are not limited to Use the same transparent conductive material. In addition, in order to increase the area of the transparent conductive layer 40 covering the first doped semiconductor layer 22 and the second doped semiconductor layer 32 as much as possible, the transparent conductive layer 40 at least partially covers the release layer 11, or even the transparent conductive layer 40 completely covers the release layer 11 in the vertical projection direction Z and the horizontal direction H, thereby ensuring the coverage of the transparent conductive layer 40 , but not limited thereto.

Afterwards, as shown in FIG. 8 , the release layer 11 is separated from the semiconductor substrate 10 to remove the release layer 11 and the transparent conductive layer 40 covering the release layer 11, thereby making the first doped semiconductor layer 22 The transparent conductive layer 40 is electrically separated from the transparent conductive layer 40 on the second doped semiconductor layer 32, and a first electrode 41 and a second electrode are respectively formed on the first doped semiconductor layer 22 and the second doped semiconductor layer 32. 42. In other words, the first electrode 41 and the second electrode 42 are formed by the transparent conductive layer 40, and through the manufacturing method of this embodiment, the first electrode 41 and the second electrode 42 can be respectively covered to the outermost edge of the semiconductor substrate 10 , thereby increasing the effective application area of the solar cell and thus improving the photoelectric conversion effect of the solar cell. In addition, if the first semiconductor layer 21, the first doped semiconductor layer 22, the second semiconductor layer 31 and the second doped semiconductor layer 32 also partially cover the release layer 11, the release layer 11 can be separated from the semiconductor substrate 10 at the same time. Remove the first semiconductor layer 21 covering the release layer 11, the first doped semiconductor layer 22, the second semiconductor layer 31 and the second doped semiconductor layer 32, thereby also ensuring that the first semiconductor layer 21, the first doped semiconductor layer The hetero-semiconductor layer 22 , the second semiconductor layer 31 and the second doped semiconductor layer 32 cover to the edge of the semiconductor substrate 10 . The method of removing the release layer 11 and other material layers covering it in this embodiment can be different according to different types of release layer 11, for example, physical methods, heating methods or chemical methods can be used to directly apply external force , but not limited to this.

As shown in FIG. 8 , the manufacturing method of this embodiment may further include forming a first conductive pattern 51 on the transparent conductive layer 40 on the first surface 10A, and forming a second conductive pattern on the transparent conductive layer 40 on the second surface 10B. 52. The first conductive pattern 51 and the second conductive pattern 52 can be formed of conductive material with relatively low resistivity, such as screen printing silver glue or electroplated copper wire, so as to achieve the effect of reducing impedance. In addition, the desired combination of electrical impedance and light transmittance can also be obtained by changing the pattern design of the first conductive pattern 51 and the second conductive pattern 52 . It should be noted that, the release layer 11 of this embodiment can be separated from the semiconductor substrate 10 after the first conductive pattern 51 and the second conductive pattern 52 are formed, but it is not limited thereto.

The solar cell 101 shown in FIG. 8 can be completed in the above manner. In the solar cell 101, since the first electrode 41, the second electrode 42, the first semiconductor layer 21, the first doped semiconductor layer 22, the second semiconductor layer 31 and the second doped semiconductor layer 32 all extend to cover the semiconductor substrate 10, so that the effective area for photoelectric conversion on the solar cell 101 can be increased, thereby achieving the purpose of improving the photoelectric conversion efficiency.

Different embodiments of the present invention will be described below, and to simplify the description, the following description mainly focuses on the differences of the embodiments, and the similarities will not be repeated. In addition, the same components in the various embodiments of the present invention are marked with the same reference numerals to facilitate mutual comparison among the various embodiments.

Please refer to Figure 9 and Figure 10. FIG. 9 and FIG. 10 are schematic diagrams illustrating the manufacturing method of the solar cell according to the second embodiment of the present invention. The difference from the above-mentioned first embodiment is that, as shown in FIG. 9 and FIG. 10 , in the manufacturing method of this embodiment, the release layer 11 and the semiconductor substrate 10 are formed before the first conductive pattern 51 and the second conductive pattern 52 are formed. Separation, to remove the release layer 11 and the transparent conductive layer 40 covering the release layer 11, the first semiconductor layer 21, the first doped semiconductor layer 22, the second semiconductor layer 31 and the second doped semiconductor layer 32, and Thus, the first electrode 41 and the second electrode 42 are formed. In other words, the first conductive pattern 51 and the second conductive pattern 52 are formed after the release layer 11 is separated from the semiconductor substrate 10, and the first conductive pattern 51 and the second conductive pattern 52 are respectively formed on the first electrode 41 and the second electrode 41. on electrode 42.

Please refer to Figure 11 to Figure 14. FIG. 11 to FIG. 14 are schematic diagrams illustrating the manufacturing method of the solar cell according to the third embodiment of the present invention. This embodiment provides a method for fabricating a solar cell, including the following steps: First, as shown in FIG. 11 , a semiconductor substrate 10 is provided. The semiconductor substrate 10 has a side surface 10S and a first surface 10A and a second surface 10B opposite to each other. Next, the first semiconductor layer 21 and the first doped semiconductor layer 22 are sequentially formed on the first surface 10A, and the second semiconductor layer 31 and the second doped semiconductor layer 32 are sequentially formed on the second surface 10B. In order to increase the area of the first semiconductor layer 21 and the first doped semiconductor layer 22 covering the first surface 10A of the semiconductor substrate 10 as much as possible, the first semiconductor layer 21 and the first doped semiconductor layer 22 can completely cover the semiconductor substrate 10 The first surface 10A of the semiconductor substrate 10 may partially extend to cover the side surface 10S of the semiconductor substrate 10 . Similarly, in order to increase the area covered by the second semiconductor layer 31 and the second doped semiconductor layer 32 on the second surface 10B of the semiconductor substrate 10 as much as possible, the second semiconductor layer 31 and the second doped semiconductor layer 32 can fully cover The second surface 10B of the semiconductor substrate 10 may also partially extend to cover the side surface 10S of the semiconductor substrate 10 . Therefore, the first semiconductor layer 21 and the first doped semiconductor layer 22 may partially overlap with the second semiconductor layer 31 and the second doped semiconductor layer 32 on the side surface 10S, but it is not limited thereto.

Then, as shown in FIG. 12 , a release layer 11 is formed on the side surface 10S of the semiconductor substrate 10 . Since the first semiconductor layer 21 and the first doped semiconductor layer 22 partially cover the side surface 10S of the semiconductor substrate 10, and the second semiconductor layer 31 and the second doped semiconductor layer 32 partially cover the side surface 10S of the semiconductor substrate 10, the release layer 11 is formed on the first doped semiconductor layer 22 or/and the second doped semiconductor layer 32 on the side surface 10S. Next, a transparent conductive layer 40 is formed on the first doped semiconductor layer 22 and the second doped semiconductor layer 32 , the transparent conductive layer 40 at least partially covers the release layer 11 . Similar to the above-mentioned first embodiment, in order to increase the area of the transparent conductive layer 40 covering the first doped semiconductor layer 22 and the second doped semiconductor layer 32 as much as possible, the transparent conductive layer 40 is preferably formed in the vertical projection direction Z. And the release layer 11 is completely covered in the horizontal direction H, thereby ensuring the coverage of the transparent conductive layer 40 , but not limited thereto.

Afterwards, as shown in FIG. 13 , the release layer 11 is separated from the semiconductor substrate 10 to remove the release layer 11 and the transparent conductive layer 40 covering the release layer 11, thereby making the first doped semiconductor layer 22 The transparent conductive layer 40 is electrically separated from the transparent conductive layer 40 on the second doped semiconductor layer 32, and a first electrode 41 and a second electrode are respectively formed on the first doped semiconductor layer 22 and the second doped semiconductor layer 32. 42. Next, as shown in FIG. 14, a first conductive pattern 51 is formed on the transparent conductive layer 40 (that is, the first electrode 41) on the first surface 10A, and a first conductive pattern 51 is formed on the transparent conductive layer 40 (that is, the second electrode 41) on the second surface 10B. The second conductive pattern 52 is formed on the electrode 42) to form a solar cell 102 as shown in FIG. 14 . In this embodiment, the first conductive pattern 51 and the second conductive pattern 52 are formed after the release layer is separated from the semiconductor substrate 10 , but it is not limited thereto. It should be noted that since the release layer of this embodiment is formed after the first semiconductor layer 21, the first doped semiconductor layer 22, the second semiconductor layer 31 and the second doped semiconductor layer 32, when the release layer is removed layer will not affect the coverage of the first semiconductor layer 21, the first doped semiconductor layer 22, the second semiconductor layer 31 and the second doped semiconductor layer 32, thus avoiding the removal of the release layer manufacturing process Negative effects of bad conditions.

Please refer to Figure 15. FIG. 15 is a schematic diagram of a method for fabricating a solar cell according to a fourth embodiment of the present invention. As shown in FIG. 15 , the difference from the above-mentioned third embodiment is that the release layer 11 of this embodiment is separated from the semiconductor substrate 10 after the first conductive pattern 51 and the second conductive pattern 52 are formed.

In summary, the manufacturing method of the solar cell of the present invention utilizes the formation of a release layer on the side of the semiconductor substrate, so that the transparent conductive layer can be fully formed on the upper and lower surfaces of the semiconductor substrate and on the release layer, and then by making the release layer The layer is separated from the semiconductor substrate to electrically isolate the transparent conductive layer on the upper and lower surfaces. Through the manufacturing method of the present invention, the material layers such as the first electrode, the second electrode, the first semiconductor layer, the first doped semiconductor layer, the second semiconductor layer and the second doped semiconductor layer on the semiconductor substrate can be extended to cover To the edge of the semiconductor substrate, the effective area for photoelectric conversion on the solar cell is increased, thereby achieving the purpose of improving the photoelectric conversion efficiency.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (17)

1. A method for manufacturing a solar cell, comprising: A semiconductor substrate is provided, wherein the semiconductor substrate has a side surface and a first surface and a second surface opposite to each other, and a release layer is formed on the side surface; sequentially forming a first semiconductor layer and a first doped semiconductor layer on the first surface; sequentially forming a second semiconductor layer and a second doped semiconductor layer on the second surface; forming a transparent conductive layer on the first doped semiconductor layer and the second doped semiconductor layer, wherein the transparent conductive layer at least partially covers the release layer; and separating the release layer from the semiconductor substrate to remove the release layer and the transparent conductive layer covering the release layer. 2. The method for manufacturing a solar cell according to claim 1, further comprising forming the first semiconductor layer, the first doped semiconductor layer, the second semiconductor layer, and the second doped semiconductor layer on the semiconductor The substrate is subjected to texturing treatment, so that the first surface and the second surface of the semiconductor substrate are transformed into roughened surfaces. 3. The method for fabricating a solar cell as claimed in claim 1, wherein the semiconductor substrate comprises a crystalline silicon semiconductor substrate. 4. The manufacturing method of a solar cell as claimed in claim 3, wherein the release layer is first formed on the surface of a silicon crystal column (ingot), and then formed on the side surface by cutting the silicon crystal column to have the release layer layer of the semiconductor substrate. 5. The method for manufacturing a solar cell according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are respectively amorphous silicon intrinsic semiconductor layers, and the first doped semiconductor layer is n-type doped amorphous a silicon layer, and the second doped semiconductor layer is a p-type doped amorphous silicon layer. 6. The method for manufacturing a solar cell according to claim 1, wherein before the release layer is separated from the semiconductor substrate, the first semiconductor layer and the first doped semiconductor layer partially cover the release layer, and the The second semiconductor layer and the second doped semiconductor layer partially cover the release layer, and when the release layer is separated from the semiconductor substrate, the first semiconductor layer and the first doped layer covering the release layer are removed at the same time. the semiconductor layer, the second semiconductor layer and the second doped semiconductor layer. 7. The method for manufacturing a solar cell according to claim 1, further comprising forming a first conductive pattern on the transparent conductive layer on the first surface, and forming a second conductive pattern on the transparent conductive layer on the second surface. pattern. 8 . The method for manufacturing a solar cell according to claim 7 , wherein the release layer is separated from the semiconductor substrate after the first conductive pattern and the second conductive pattern are formed. 9. The method for manufacturing a solar cell as claimed in claim 7, wherein the first conductive pattern and the second conductive pattern are formed after the release layer is separated from the semiconductor substrate. 10 . The method for manufacturing a solar cell according to claim 1 , wherein the transparent conductive layer completely covers the release layer before the release layer is separated from the semiconductor substrate. 11 . 11. A method for manufacturing a solar cell, comprising: providing a semiconductor substrate, wherein the semiconductor substrate has a side surface and a first surface and a second surface facing away from each other; sequentially forming a first semiconductor layer and a first doped semiconductor layer on the first surface; sequentially forming a second semiconductor layer and a second doped semiconductor layer on the second surface; forming a release layer on the side surface of the semiconductor substrate, wherein the release layer is formed after the first semiconductor layer, the first doped semiconductor layer, the second semiconductor layer and the second doped semiconductor layer; forming a transparent conductive layer on the first doped semiconductor layer and the second doped semiconductor layer, wherein the transparent conductive layer at least partially covers the release layer; and separating the release layer from the semiconductor substrate to remove the release layer and the transparent conductive layer covering the release layer. 12. The method for manufacturing a solar cell according to claim 11, wherein the semiconductor substrate is a crystalline silicon semiconductor substrate, the first semiconductor layer and the second semiconductor layer are respectively amorphous silicon intrinsic semiconductor layers, and the first doped The semiconductor layer is an n-type doped amorphous silicon layer, and the second doped semiconductor layer is a p-type doped amorphous silicon layer. 13. The method of manufacturing a solar cell according to claim 11, wherein the first semiconductor layer and the first doped semiconductor layer partially cover the side surface of the semiconductor substrate, and the second semiconductor layer and the second doped semiconductor layer A layer partially covers the side surface of the semiconductor substrate, and the release layer is formed on the first doped semiconductor layer or/and the second doped semiconductor layer on the side surface. 14. The method of manufacturing a solar cell according to claim 11, further comprising forming a first conductive pattern on the transparent conductive layer on the first surface, and forming a second conductive pattern on the transparent conductive layer on the second surface. pattern. 15. The method for manufacturing a solar cell as claimed in claim 14, wherein the release layer is separated from the semiconductor substrate after the first conductive pattern and the second conductive pattern are formed. 16. The method of manufacturing a solar cell as claimed in claim 14, wherein the first conductive pattern and the second conductive pattern are formed after the release layer is separated from the semiconductor substrate. 17. The method for manufacturing a solar cell as claimed in claim 11, wherein the transparent conductive layer completely covers the release layer before the release layer is separated from the semiconductor substrate.