CN104112789B - Solar cell and manufacturing method thereof - Google Patents

Abstract

The invention provides a solar cell and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: forming a protective layer on the first surface of the substrate; forming a passivation layer on the second surface of the substrate; forming at least one first type semiconductor pattern and at least one second type semiconductor pattern on the passivation layer, wherein the first type semiconductor pattern and the second type semiconductor pattern are coplanar and adjacent to each other; forming a trench at a boundary between the first type semiconductor pattern and the second type semiconductor pattern to electrically insulate the first type semiconductor pattern and the second type semiconductor pattern from each other; forming a seed layer on the first type semiconductor pattern and the second type semiconductor pattern, wherein the seed layer has a conductivity of more than 9 × 10⁵S/m; an electrode layer is formed on the seed layer.

Description

Solar cell and manufacturing method thereof

technical field

The present invention relates to semiconductor technology, and in particular to a solar cell and a manufacturing method thereof.

Background technique

In recent years, with the rising awareness of environmental protection and the global energy crisis, pollution and shortage of petrochemical energy, how to develop energy-saving, environmentally friendly and sustainable alternative energy has become the primary goal of scientific and technological research and development in various advanced countries. Among the many alternative energy solutions, solar cells account for more than 23% of the renewable energy emerging market. It is the most important alternative energy at this stage, and it is also a very promising energy technology.

At present, among various types of solar cells, silicon-based solar cells are the mainstream technology. However, the development of silicon-based solar cells is still limited by the photoelectric conversion efficiency. In addition to the anti-reflection layer (anti-reflection layer) and passivation layer, the quality of the window layer (window layer) also determines the film layer that affects the photoelectric conversion efficiency. One of the important keys of photoelectric conversion efficiency.

FIG. 1 is a schematic diagram of a silicon-based solar cell in the prior art. 1, a silicon-based solar cell 100 includes a silicon substrate 110, passivation layers 120a, 120b, a first-type semiconductor layer 130, a second-type semiconductor layer 140, window layers 150a, 150b and electrodes 160a, 160b. The first-type semiconductor layer 130 and the second-type semiconductor layer 140 are arranged on opposite sides of the silicon substrate 110, and the passivation layer 120a is arranged between the first-type semiconductor layer 130 and the silicon substrate 110, and the passivation layer 120b It is disposed between the second-type semiconductor layer 140 and the silicon substrate 110 . The window layers 150a, 150b cover the first-type semiconductor layer 130 and the second-type semiconductor layer 140 respectively, and the electrodes 160a, 160b are respectively located on the window layers 150a, 150b.

Since the window layer 150a is disposed on the light-receiving surface of the silicon-based solar cell 100 (that is, facing the external light), in consideration of the light transmittance, the silicon-based solar cell 100 mainly uses transparent metal oxide as the material of the window layer 150a, Among them, indium tin oxide (ITO) is the mainstream of transparent metal oxides. However, indium is expensive and indium tin oxide requires a vacuum process, which increases the cost and time of the process and reduces the competitiveness of the product. In addition, during the ITO deposition process, the plasma in the physical vapor deposition (PVD) process is likely to damage the film layers in the silicon-based solar cell 100 , thereby affecting the device characteristics of the silicon-based solar cell 100 .

Contents of the invention

The invention provides a method for manufacturing a solar cell, which has relatively low process cost and time.

The present invention provides a solar cell having good device characteristics.

A method for manufacturing a solar cell of the present invention includes the following steps. Form a protective layer on the first surface of the substrate; form a passivation layer on the second surface of the substrate; form at least one first-type semiconductor pattern and at least one second-type semiconductor pattern on the passivation layer, wherein the first-type semiconductor The pattern and the second-type semiconductor pattern are coplanar and adjacent to each other; a trench is formed at the junction of the first-type semiconductor pattern and the second-type semiconductor pattern, so that the first-type semiconductor pattern and the second-type semiconductor pattern are electrically insulated from each other; A seed layer is formed on the first-type semiconductor pattern and the second-type semiconductor pattern, and the conductivity of the seed layer is greater than 9×10 ⁵ S/m; an electrode layer is formed on the seed layer.

In an embodiment of the present invention, the above-mentioned first surface is opposite to the second surface.

In an embodiment of the present invention, before forming the protective layer, further includes performing a surface texturing process on the first surface.

In an embodiment of the present invention, the material of the protective layer includes at least one of silicon nitride, silicon oxide and aluminum oxide.

In an embodiment of the present invention, the above-mentioned method for forming the protective layer includes plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), atmospheric pressure chemical vapor deposition (atmospheric pressure chemical vapor deposition, APCVD) or atomic layer deposition (atomic layer deposition, ALD).

In an embodiment of the present invention, the method for forming the first-type semiconductor pattern and the second-type semiconductor pattern on the passivation layer includes the following steps. setting a first mask on the passivation layer, and the first mask exposes a first region of the passivation layer; forming a first-type semiconductor pattern on the first region; setting a second mask on the passivation layer, and The second mask covers the first-type semiconductor pattern and exposes a second area other than the first-type semiconductor pattern; the second-type semiconductor pattern is formed on the second area.

In an embodiment of the present invention, one of the above-mentioned first-type semiconductor pattern and the second-type semiconductor pattern is an N-type semiconductor pattern, and the other of the first-type semiconductor pattern and the second-type semiconductor pattern is a P-type semiconductor pattern .

In an embodiment of the present invention, the method for manufacturing the trench includes removing the first-type semiconductor pattern and the second-type semiconductor pattern at the junction of the first-type semiconductor pattern and the second-type semiconductor pattern by laser drilling or wet etching. At least one of the semiconductor patterns, and the trench exposes a part of the passivation layer.

In an embodiment of the present invention, the above-mentioned trench is formed before the seed layer and the electrode layer, and the depth of the trench is equal to the thickness of the first-type semiconductor pattern or the thickness of the second-type semiconductor pattern, and the trench exposes a part of the passivation layer .

In an embodiment of the present invention, the method for forming the seed layer or the method for forming the electrode layer includes screen printing or electroplating, and the seed layer and the electrode layer expose the portion of the passivation layer.

In an embodiment of the present invention, the above-mentioned ditch is formed after the electrode layer, and the depth of the ditch is equal to the sum of the thicknesses of the first-type semiconductor pattern, the seed layer and the electrode layer, or equal to the thickness of the second-type semiconductor pattern, the seed layer And the sum of the thickness of the electrode layer, trenches and expose a part of the passivation layer.

In an embodiment of the present invention, the method for forming the seed layer includes covering the material of the seed layer on the first-type semiconductor pattern and the second-type semiconductor pattern in a manner of screen printing, electroplating or thermal evaporation, The method for forming the electrode layer includes completely covering the seed layer with the material of the electrode layer by means of screen printing, electroplating, thermal evaporation, electrolysis or chemical vapor deposition.

In an embodiment of the present invention, the material of the seed layer includes nickel, titanium, silver, aluminum or cobalt.

In an embodiment of the present invention, the thickness of the aforementioned seed layer is less than 20 nanometers.

In an embodiment of the present invention, the material of the above-mentioned electrode layer includes silver, aluminum or copper.

A solar cell of the present invention includes a substrate, a protective layer, a passivation layer, at least one first-type semiconductor pattern, at least one second-type semiconductor pattern, a seed layer, and an electrode layer; the substrate has an opposite first surface and a second surface The protective layer is configured on the first surface; the passivation layer is configured on the second surface; the first type semiconductor pattern and the second type semiconductor pattern are configured on the passivation layer, wherein the first type semiconductor pattern and the second type semiconductor pattern Coplanar and electrically insulated from each other; the seed layer is arranged on the first-type semiconductor pattern and the second-type semiconductor pattern, and the conductivity of the seed layer is greater than 9×10 ⁵ S/m; the electrode layer is arranged on the seed layer.

In an embodiment of the present invention, the above-mentioned first surface is a textured surface.

In an embodiment of the present invention, the material of the protective layer includes at least one of silicon nitride, silicon oxide and aluminum oxide.

In an embodiment of the present invention, one of the above-mentioned first-type semiconductor pattern and the second-type semiconductor pattern is an N-type semiconductor pattern, and the other of the first-type semiconductor pattern and the second-type semiconductor pattern is a P-type semiconductor pattern .

In an embodiment of the present invention, the above-mentioned part of the passivation layer is not covered by the first-type semiconductor pattern and the second-type semiconductor pattern, and the seed layer and the electrode located on the first-type semiconductor pattern and the second-type semiconductor pattern layer also exposes said portion of the passivation layer.

In an embodiment of the present invention, the material of the seed layer includes nickel, titanium, silver, aluminum or cobalt.

In an embodiment of the present invention, the thickness of the aforementioned seed layer is less than 20 nanometers.

In an embodiment of the present invention, the material of the above-mentioned electrode layer includes silver, aluminum or copper.

Based on the above, in the present invention, the first-type semiconductor pattern and the second-type semiconductor pattern are jointly disposed on the non-light-receiving surface of the substrate (ie, the second surface facing away from external light). In this way, in addition to making the light-shielding electrode layer on the non-light-receiving surface of the substrate, it is also possible to avoid forming a window layer on the light-receiving surface, thereby effectively increasing the light transmittance of the light-receiving surface. In addition, the present invention replaces the window layer made of transparent metal oxide in the prior art with a seed layer with relatively high conductivity. Therefore, in addition to effectively improving the photoelectric conversion efficiency and fillfactor of the solar cell, it can also avoid The production of indium tin oxide is eliminated, thereby effectively reducing the process cost and time, and avoiding damage to other film layers in the solar cell due to the production of transparent metal oxide, so that the solar cell of the present invention has good device characteristics.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

Fig. 1 is the schematic diagram of a kind of silicon-based solar cell of prior art;

2A to 2I are cross-sectional schematic diagrams of a manufacturing process of a solar cell according to an embodiment of the present invention;

3A to 3C are schematic cross-sectional views of a fabrication process of a solar cell according to another embodiment of the present invention.

Explanation of reference signs:

100: silicon-based solar cells;

110: silicon substrate;

120a, 120b, 230: passivation layer;

130: a first-type semiconductor layer;

140: the second type semiconductor layer;

150a, 150b: window layer;

160a, 160b: electrodes;

200, 300: solar cells;

210: substrate;

220: protective layer;

230: passivation layer;

240A: first mask;

240B: second mask;

250a, 250b: first-type semiconductor patterns;

260a, 260b: second-type semiconductor patterns;

270a, 270b: seed layer;

280a, 280b: electrode layers;

A1: the first area;

A2: the second area;

S1a, S1b: first surface;

S2: second surface;

D1, D2: Depth;

T: thickness;

WA, WB: opening;

TC1, TC2: ditch;

I1, I2: island structure;

S100, S200: plasma enhanced chemical vapor deposition process.

detailed description

2A to 2I are cross-sectional schematic diagrams of a manufacturing process of a solar cell according to an embodiment of the present invention. Referring to FIG. 2A , a substrate 210 is provided, wherein the substrate 210 has a first surface S1a and a second surface S2 opposite to each other. The first surface S1a is, for example, a light-receiving surface, that is, a surface facing external light (not shown, such as sunlight) to absorb photons, and the second surface S2 is, for example, a non-light-receiving surface, that is, a surface facing away from external light . The material of the substrate 210 includes silicon. For example, the substrate 210 is a P-type silicon substrate or an N-type silicon substrate.

Please refer to FIG. 2B. In order to improve the ability to absorb photons and reduce the reflection of external light, in this embodiment, a surface texturing process can be selectively performed on the first surface S1a (ie, the light-receiving surface) to form a textured surface ( That is, the textured first surface S1b), as shown by the jagged surface in Fig. 2B. The surface texturing process is performed, for example, but not limited to, using potassium hydroxide (KOH) solution.

Referring to FIG. 2C, a protection layer 220 is formed on the first surface S1b. In this embodiment, the protective layer 220 can be a passivation layer with a high energy gap to reduce the probability of carrier recombination on the surface, and its material is, for example, amorphous silicon (amorphous-silicon), and it is deposited by plasma-enhanced chemical vapor deposition, for example. method made. On the other hand, the protection layer 220 can also be an anti-reflection layer for reducing the reflection of external light, and its material is, for example, at least one of silicon nitride, silicon oxide, and aluminum oxide. made by pressure chemical vapor deposition or atomic layer deposition. In this way, the protective layer 220 can not only protect the solar cell (for example, to prevent the solar cell from being scratched or damp), but also reduce the probability of carrier recombination on the surface and/or reduce the reflection of external light effect.

Referring to FIG. 2D , a passivation layer 230 is formed on the second surface S2 of the substrate 210 . The material of the passivation layer 230 is, for example, amorphous silicon, and the passivation layer 230 is formed by, for example, plasma enhanced chemical vapor deposition.

Referring to FIG. 2E , a first mask 240A is provided on the passivation layer 230, wherein the first mask 240A has an opening WA exposing the first area A1 of the passivation layer 230, and shields areas other than the first area A1 (ie Second area A2).

Next, a first-type semiconductor pattern 250a is formed on the first region A1, wherein the material of the first-type semiconductor pattern 250a is, for example, amorphous silicon, and the plasma-enhanced chemical vapor deposition process S100 is performed to form the first-type semiconductor pattern 250a.

Referring to FIG. 2F, a second mask 240B is provided on the passivation layer 230, wherein the second mask 240B shields the first region A1 where the first-type semiconductor pattern 250a is located, and the second mask 240B has an opening WB exposing the first region A1. The second region A2 other than the type-one semiconductor pattern 250a.

Next, a second-type semiconductor pattern 260a is formed on the second region A2, wherein the material of the second-type semiconductor pattern 260a is, for example, amorphous silicon, and the method for forming the second-type semiconductor pattern 260a includes performing a plasma-enhanced chemical vapor deposition process. S200.

The first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a are coplanar and adjacent to each other. In addition, one of the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a is an N-type semiconductor pattern, and the other of the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a is a P-type semiconductor pattern.

What needs to be explained here is that, although the present embodiment takes two first-type semiconductor patterns 250a and two second-type semiconductor patterns 260a alternately arranged as an example for illustration, the first-type semiconductor patterns 250a and the second-type semiconductor patterns The number or arrangement relationship of 260a may depend on actual applications, so the present invention is not limited thereto.

Referring to FIG. 2G , a trench TC1 is formed at the junction of the first-type semiconductor pattern and the second-type semiconductor pattern (ie, the junction of the first region A1 and the second region A2 ). Specifically, the trench TC1 is manufactured by, for example, laser drilling or wet etching to remove the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a located at the junction of the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a. 260a to form a first-type semiconductor pattern 250b and a second-type semiconductor pattern 260b separated from each other, wherein the trench TC1 exposes a part of the passivation layer 230 . In addition, after the trench TC1 is formed, the first-type semiconductor pattern 250b and the second-type semiconductor pattern 260b are electrically insulated from each other.

Further, the depth D1 of the trench TC1 in this embodiment is, for example, approximately equal to the thickness T of the first-type semiconductor pattern 250 b or the second-type semiconductor pattern 260 b. That is, in this embodiment, the depth of the first-type semiconductor pattern 250a and/or the second-type semiconductor pattern 260a removed by laser drilling or wet etching is approximately equal to their respective thicknesses.

Referring to FIG. 2H , a seed layer 270 a is formed on the first-type semiconductor pattern 250 b and the second-type semiconductor pattern 260 . In this embodiment, the seed layer 270a is, for example, a plurality of island-shaped conductive structures separated from each other and disposed corresponding to the first-type semiconductor pattern 250b and the second-type semiconductor pattern 260b, and the seed layer 270a also exposes the trench TC1. part of the passivation layer 230 .

In addition, the material of the seed layer 270a is, for example, nickel, titanium, silver, aluminum, cobalt or a laminate thereof, and the method of forming the seed layer 270a may be screen printing or electroplating. In this embodiment, the thickness of the seed layer 270a is less than 20 nm, and the conductivity is greater than 9×10 ⁵ S/m, and the conductivity is preferably between 10 ⁶ and 10 ⁸ S/m.

In this embodiment, the window layer made of transparent metal oxide (conductivity less than 5×10 ⁵ S/m) in the prior art is replaced by the seed layer 270a with relatively high conductivity. In addition to the photoelectric conversion efficiency and fill factor, it can also avoid the production of indium tin oxide, thereby effectively reducing the process cost and time, and avoiding damage to other layers in the solar cell due to the production of transparent metal oxide, thereby enabling The solar cell of this example has good device characteristics.

Referring to FIG. 2I, an electrode layer 280a is formed on the seed layer 270a. Here, the fabrication of the solar cell 200 of this embodiment is preliminarily completed. In this embodiment, the electrode layer 280a is, for example, a plurality of island-shaped conductive structures separated from each other and disposed corresponding to the first-type semiconductor pattern 250b and the second-type semiconductor pattern 260b, and the electrode layer 280a also exposes the trench TC1. part of the passivation layer 230 .

In addition, the electrode layer 280a is made of silver, aluminum, copper or a laminate thereof, and the method of forming the electrode layer 280a may be screen printing or electroplating.

In this embodiment, the first-type semiconductor pattern 250b and the second-type semiconductor pattern 260b are jointly disposed on the non-light-receiving surface of the substrate 210 (ie, the second surface S2 facing away from external light). Therefore, in this embodiment, in addition to fabricating the light-shielding electrode layer 280a on the non-light-receiving surface of the substrate 210 (ie, the second surface S2 facing away from external light), it is also possible to dispense with the light-receiving surface (ie, the first surface S1b). A window layer in the prior art (disposed between the substrate and the first-type semiconductor pattern or between the second-type semiconductor pattern) is formed to effectively increase the light transmittance of the light-receiving surface (ie, the first surface S1b).

In the foregoing embodiments, the trench TC1 (used to electrically insulate the first-type semiconductor pattern 250 b from the second-type semiconductor pattern 260 b ) is formed before the seed layer 270 a and the electrode layer 280 a, but the invention is not limited thereto.

In another embodiment of the present invention, the trench can also be formed after the electrode layer. 3A to 3C are schematic cross-sectional views of a fabrication process of a solar cell according to another embodiment of the present invention. The solar cell 300 of this embodiment (refer to FIG. 3C ) has a similar structure and a similar manufacturing process to the solar cell 200 in FIG. 2I (refer to FIG. 2A to FIG. 2F for the previous stage of the manufacturing process of the solar cell 300 ). The difference between the two lies in that in the solar cell 300 of this embodiment, after the aforementioned steps in FIG. 2F , a seed layer 270b (as shown in FIG. 3A ) and The electrode layer 280b (as shown in FIG. 3B ) instead of forming the trench TC1 (refer to FIG. 2G ).

In addition, the method of forming the seed layer 270b in this embodiment is to completely cover the material of the seed layer 270b on the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a by screen printing, electroplating or thermal evaporation. In addition, the method of forming the electrode layer 280b is to fully cover the material of the electrode layer 280b on the seed layer 270b by means of screen printing, electroplating, thermal evaporation, electrolysis or chemical vapor deposition.

After the seed layer 270b and the electrode layer 280b are formed, the trench TC2 is formed at the junction of the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a, so that the first-type semiconductor pattern 250b and the second-type semiconductor pattern 260b are connected to each other. separated and electrically insulated.

Since the seed layer 270b and the electrode layer 280b have completely covered the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a before forming the trench TC2, in this embodiment, laser drilling or wet etching is used to remove the first-type semiconductor pattern 250a. When the first-type semiconductor pattern 250a and/or the second-type semiconductor pattern 260a at the junction of the first-type semiconductor pattern 250a and the second-type semiconductor pattern 260a, the seed layer 270b and the electrode layer 280b located thereon will be removed at the same time, and A plurality of seed layers 270a and electrode layers 280a having an island structure are formed, wherein the seed layers 270a and the electrode layers 280a have similar profiles to the first-type semiconductor pattern 250a or the second-type semiconductor pattern 260a.

In addition, the island structure I1 formed by the first type semiconductor pattern 250b, the seed layer 270a and the electrode layer 280a and the island structure I2 formed by the second type semiconductor pattern 260b, the seed layer 270a and the electrode layer 280a will be exposed. part of the passivation layer 230 . In other words, the depth D2 of the trench TC2 is approximately equal to the sum of the thicknesses of the first-type semiconductor pattern 250b, the seed layer 270a, and the electrode layer 280a (that is, the thickness of the island structure I1) or equal to the second-type semiconductor pattern 260b, the seed layer 270a, and the electrode layer. The sum of the thicknesses of the layer 280a (ie the thickness of the island structure I2).

Similar to the solar cell 200, the solar cell 300 of this embodiment configures the first-type semiconductor pattern 250b and the second-type semiconductor pattern 260b on the non-light-receiving surface of the substrate 210 (ie, the second surface S2 facing away from external light). . In this way, in addition to avoiding the need to form the light-shielding electrode layer 280a on the light-receiving surface of the substrate 210 (that is, the first surface S1b facing the external light), it is also possible to avoid forming a window layer in the prior art on the light-receiving surface. , thereby effectively improving the light transmittance of the light-receiving surface. In addition, the solar cell 300 of this embodiment also uses the relatively high conductivity seed layer 270a to replace the window layer made of transparent metal oxide in the prior art. Therefore, in addition to effectively improving the photoelectric conversion efficiency and fill factor of the solar cell 300 In addition, the production of indium tin oxide can also be avoided, thereby effectively reducing the process cost and time, and avoiding damage to other film layers in the solar cell due to the production of transparent metal oxide, so that the solar cell 300 of this embodiment Has good component properties.

To sum up, in the present invention, the first-type semiconductor pattern and the second-type semiconductor pattern are jointly disposed on the non-light-receiving surface of the substrate (ie, the second surface facing away from external light). In this way, in addition to making the light-shielding electrode layer on the non-light-receiving surface of the substrate, it is also possible to avoid forming a window layer on the light-receiving surface, thereby effectively increasing the light transmittance of the light-receiving surface. In addition, the present invention replaces the window layer made of transparent metal oxide in the prior art with a seed layer with relatively high conductivity. Therefore, in addition to effectively improving the photoelectric conversion efficiency and fillfactor of the solar cell, it can also avoid The production of indium tin oxide is eliminated, thereby effectively reducing the process cost and time, and avoiding damage to other film layers in the solar cell due to the production of transparent metal oxide, so that the solar cell of the present invention has good device characteristics.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (23)

1. a manufacture method for solar cell, is characterized in that, comprising:

A first surface of a substrate forms a protective layer;

A second surface of this substrate forms a passivation layer;

This passivation layer forms at least one first type semiconductor pattern and at least one Second-Type semiconductor pattern, wherein this first type semiconductor pattern and this Second-Type semiconductor pattern copline and adjacent to each other;

Form irrigation canals and ditches at the intersection of this first type semiconductor pattern and this Second-Type semiconductor pattern, be electrically insulated each other to make this first type semiconductor pattern and this Second-Type semiconductor pattern;

This first type semiconductor pattern and this Second-Type semiconductor pattern form a Seed Layer, and the conductance of this Seed Layer is greater than 9 × 10 ⁵s/m; And

This Seed Layer is formed an electrode layer.

2. the manufacture method of solar cell according to claim 1, is characterized in that, this first surface is relative to this second surface.

3. the manufacture method of solar cell according to claim 1, is characterized in that, before this protective layer of formation, also comprises:

One surface-texturing processing procedure is carried out to this first surface.

4. the manufacture method of solar cell according to claim 1, is characterized in that, the material of this protective layer comprise silicon nitride, silica and aluminium oxide wherein at least one.

5. the manufacture method of solar cell according to claim 1, is characterized in that, the method forming this protective layer comprises plasma enhanced chemical vapor deposition, aumospheric pressure cvd or ald.

6. the manufacture method of solar cell according to claim 1, is characterized in that, the method that this passivation layer is formed this first type semiconductor pattern and this Second-Type semiconductor pattern comprises:

This passivation layer arranges one first shade, and this first shade exposes a first area of this passivation layer;

This first area is formed this first type semiconductor pattern;

This passivation layer arranges one second shade, and this second shade covers this first type semiconductor pattern and exposes the second area beyond this first type semiconductor pattern; And

Form this Second-Type semiconductor pattern on the first region.

7. the manufacture method of solar cell according to claim 1, it is characterized in that, this the first type semiconductor pattern and this Second-Type semiconductor pattern one of them be N type semiconductor pattern, and this first type semiconductor pattern and this Second-Type semiconductor pattern wherein another is P type semiconductor pattern.

8. the manufacture method of solar cell according to claim 1, is characterized in that, the manufacture method of these irrigation canals and ditches comprises:

Remove with laser drill or Wet-type etching this first type semiconductor pattern of the intersection being positioned at this first type semiconductor pattern and this Second-Type semiconductor pattern and this Second-Type semiconductor pattern wherein at least one, and these irrigation canals and ditches expose this passivation layer of a part.

9. the manufacture method of solar cell according to claim 1, it is characterized in that, these irrigation canals and ditches were formed before this Seed Layer and this electrode layer, and the degree of depth of these irrigation canals and ditches equals the thickness of this first type semiconductor pattern or this Second-Type semiconductor pattern, these irrigation canals and ditches also expose this part of passivation layer.

10. the manufacture method of solar cell according to claim 9, is characterized in that, the method forming this Seed Layer or the method forming this electrode layer comprise screen painting or plating, and this Seed Layer and this electrode layer expose this passivation layer of this part.

The manufacture method of 11. solar cells according to claim 1, it is characterized in that, these irrigation canals and ditches are formed after this electrode layer, and the degree of depth of these irrigation canals and ditches equals the summation of the thickness of this first type semiconductor pattern, this Seed Layer and this electrode layer, or equaling the summation of thickness of this Second-Type semiconductor pattern, this Seed Layer and this electrode layer, these irrigation canals and ditches also expose this passivation layer of a part.

The manufacture method of 12. solar cells according to claim 11, it is characterized in that, the method forming this Seed Layer comprises and being covered in all sidedly on this first type semiconductor pattern and this Second-Type semiconductor pattern by the material of this Seed Layer in the mode of screen painting, plating or hot evaporation, and the method forming this electrode layer comprises and being covered in all sidedly in this Seed Layer by the material of this electrode layer in the mode of screen painting, plating, hot evaporation, electrolysis or chemical vapour deposition (CVD).

The manufacture method of 13. solar cells according to claim 1, is characterized in that, the material of this Seed Layer comprises nickel, titanium, silver, aluminium or cobalt.

The manufacture method of 14. solar cells according to claim 1, is characterized in that, the thickness of this Seed Layer is less than 20 nanometers.

The manufacture method of 15. solar cells according to claim 1, is characterized in that, the material of this electrode layer comprises silver, aluminium or copper.

16. 1 kinds of solar cells, is characterized in that, comprising:

One substrate, has a relative first surface and a second surface;

One protective layer, is configured on this first surface;

One passivation layer, is configured on this second surface;

At least one first type semiconductor pattern and at least one Second-Type semiconductor pattern are configured on this passivation layer, wherein this first type semiconductor pattern and this Second-Type semiconductor pattern copline and be electrically insulated each other;

One Seed Layer, be configured on this first type semiconductor pattern and this Second-Type semiconductor pattern, and the conductance of this Seed Layer is greater than 9 × 10 ⁵s/m; And

One electrode layer, is configured in this Seed Layer.

17. solar cells according to claim 16, is characterized in that, this first surface is a textured first surface.

18. solar cells according to claim 16, is characterized in that, the material of this protective layer comprise silicon nitride, silica and aluminium oxide wherein at least one.

19. solar cells according to claim 16, it is characterized in that, this the first type semiconductor pattern and this Second-Type semiconductor pattern one of them be N type semiconductor pattern, and this first type semiconductor pattern and this Second-Type semiconductor pattern wherein another is P type semiconductor pattern.

20. solar cells according to claim 16, it is characterized in that, this passivation layer of a part is not covered by this first type semiconductor pattern and this Second-Type semiconductor pattern, and this Seed Layer be positioned on this first type semiconductor pattern and this Second-Type semiconductor pattern and this electrode layer also expose this passivation layer of this part.

21. solar cells according to claim 16, is characterized in that, the material of this Seed Layer comprises nickel, titanium, silver, aluminium or cobalt.

22. solar cells according to claim 16, is characterized in that, the thickness of this Seed Layer is less than 20 nanometers.

23. solar cells according to claim 16, is characterized in that, the material of this electrode layer comprises silver, aluminium or copper.