[go: up one dir, main page]

CN106129015A - A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof - Google Patents

A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof Download PDF

Info

Publication number
CN106129015A
CN106129015A CN201610541089.1A CN201610541089A CN106129015A CN 106129015 A CN106129015 A CN 106129015A CN 201610541089 A CN201610541089 A CN 201610541089A CN 106129015 A CN106129015 A CN 106129015A
Authority
CN
China
Prior art keywords
chip
flip
embedment
plane
encapsulating structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610541089.1A
Other languages
Chinese (zh)
Inventor
邹益朝
于大全
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Kunshan Electronics Co Ltd
Original Assignee
Huatian Technology Kunshan Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Kunshan Electronics Co Ltd filed Critical Huatian Technology Kunshan Electronics Co Ltd
Priority to CN201610541089.1A priority Critical patent/CN106129015A/en
Publication of CN106129015A publication Critical patent/CN106129015A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The invention discloses a kind of encapsulating structure imbedding chip and flip-chip interconnection and preparation method thereof.Encapsulating structure comprises a substrate, at least one chip one.At least one groove it is formed with on substrate.The functional surfaces of chip one is imbedded in groove upward.Embedment chip one constitutes close plane with surface, substrate place, is formed with insulating barrier on the plane, described insulating barrier is formed with at least one of which reroutes layer, at least one chip two upside-down mounting is interconnected in described plane.The first conductive structure it is also formed with in described plane.The present invention is by least one chip buried base plate, at least one flip-chip is electrically interconnected to imbed chip and substrate place plane, multiple chips electrically can be interconnected, reduce chip package volume, technique is simple, utilizing ripe processing technology to achieve that, product yield is high simultaneously, good reliability.Invention additionally discloses the manufacture method of described encapsulating structure.

Description

A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof
Technical field
The present invention relates to a kind of encapsulating structure in semiconductor die package field, particularly relate to a kind of containing embedment chip and Encapsulating structure of flip-chip interconnection and preparation method thereof.
Background technology
Chip is wrapped up by chip encapsulation technology exactly, to avoid chip and extraneous contact, prevents outer bound pair chip A kind of Technology of infringement.Impurity in air and bad air, so steam all can corrode the precision circuit on chip, In turn result in electric property to decline.Different encapsulation technologies is widely different in manufacturing process and process aspect, to internal memory after encapsulation The performance of chip self performance also functions to vital effect.Along with photoelectricity, micro-electricity the developing rapidly of manufacturing process technology, electricity Sub-product is developing towards less, lighter, less expensive direction all the time, and therefore the packing forms of chip component is also continuously available and changes Enter.
Chinese patent 200410015872.4, a kind of multi-chip IC package and structure thereof, disclose one Multi-chip package technique, the chip-packaging structure mentioned in this technique can be effectively increased the encapsulation quantity of chip, and have good Heat dispersion, but its encapsulated space is utilized the most completely, due to the restriction of encapsulating structure, the encapsulation number of its chip Measure limited.
Summary of the invention
For solving above-mentioned technical problem, the present invention provides a kind of encapsulating structure interconnected containing embedment chip and flip-chip And preparation method thereof, it is integrated that it realizes optimized multi-chip.
The solution of the present invention is: a kind of encapsulating structure interconnected containing embedment chip and flip-chip, comprises one Silicon substrate, at least one chip one；At least one groove it is formed with on silicon substrate；The functional surfaces of chip one imbeds groove upward In；Embedment chip one constitutes close plane with surface, silicon substrate place, is formed with insulating barrier, described insulation on the plane Be formed with at least one of which rewiring layer on Ceng, at least one chip two upside-down mounting is interconnected in described plane；Shape is gone back in described plane Become to have the first conductive structure.
As the further improvement of such scheme, the size of flip-chip two is more than the size or little of groove chips one Size in groove chips one or the size equal to groove chips one.
As the further improvement of such scheme, when the quantity of the chip two of upside-down mounting is multiple, the function of each chip two and It is identical or different with the function of the chip one of embedment.
As the further improvement of such scheme, after chip two upside-down mounting, relative to described plane, the height of the first conductive structure Degree is not less than the height of the peak of chip two.
As the further improvement of such scheme, chip two is electrically interconnected to described plane by heat-conductivity conducting glue.
As the further improvement of such scheme, chip two is electrically interconnected to described plane by conductive structure.
The present invention also provides for a kind of containing embedment chip with the manufacture method of encapsulating structure of flip-chip interconnection, comprise with Lower step:
A., one silicon substrate with at least one groove is provided；
By the functional surfaces of at least one chip one upward, and be bonded in groove b.；
C. contain on the surface of functional chip one at described silicon substrate, on the functional surfaces of chip one and chip one and groove Gap in all lay insulating barrier；
D. on partial insulative layer, form at least one of which reroute；
E. on described insulating barrier with described rewiring layer, form protective layer；
F. on described protective layer, form opening, make part reroute and come out；
H. flip-chip two and be electrically interconnected to imbed the plane that chip one is constituted with silicon substrate；
G. constituted at embedment chip one and silicon substrate and in close plane, formed the first conductive structure.
As the further improvement of such scheme, the step forming the first conductive structure is electrically interconnected at flip-chip two Before the plane that embedment chip one and silicon substrate are constituted, and form first by printing, plant at least one mode in ball, plating Conductive structure.
As the further improvement of such scheme, flip-chip two is electrically interconnected to imbeds chip one and constitutes with silicon substrate Plane after, then by plant ball, plating at least one mode form the first conductive structure.
As the further improvement of such scheme, form the material of the first conductive structure and the bonding material of flip-chip two Material is same or like.
A kind of encapsulating structure interconnected containing embedment chip and flip-chip that the present invention proposes, from silicon substrate first surface To second surface extend formed at least one groove, at least one chip functions is faced up embedment groove in, described embedment chip and Surface, silicon substrate place constitutes close plane, forms insulating barrier on the plane, is formed with at least one of which on the insulating layer Rerouting layer, described flip-chip is electrically interconnected to imbed chip and substrate place plane, and forms first on the plane Conductive structure.Advantage of this is that: at least one chip buried silicon substrate, at least one flip-chip is electrically interconnected to embedment Multiple chips can electrically be interconnected by chip and silicon substrate place plane, reduce chip package volume, and technique is simple, profit Achieving that by ripe processing technology, product yield is high simultaneously, good reliability.
Accompanying drawing explanation
Fig. 1 show in the present invention structural representation of fan-out silicon substrate used；
Fig. 2 show the structural representation forming groove on described silicon substrate；
Fig. 3 show the present invention structural representation by chip buried groove；
Fig. 4 show the structural representation of the fan-out plane formation insulating barrier constituted at silicon substrate and embedment chip；
Fig. 5 show structural representation chip pad come out；
On described insulating barrier, the structural representation that at least one of which reroutes is formed shown in Fig. 6；
In described rewiring, the structural representation of protective layer is formed shown in Fig. 7；
The structural representation of opening is formed on the protection layer shown in Fig. 8；
Shown in Fig. 9, flip-chip is electrically interconnected to the structural representation imbedding chip with substrate composition plane；
Form the schematic diagram of the first conductive structure at described opening part shown in Figure 10；
Figure 11 show the structural representation of the embodiment of the present invention 2；
Figure 12 show the structural representation of the embodiment of the present invention 3；
Figure 13 show the structural representation of the embodiment of the present invention 4.
Primary symbols explanation
100 silicon substrate 101 grooves
200 chip 1 weld pads
3 polymer 103 insulating barriers
202 opening 500 chips four
204 reroute 205 protective layers
206 first conductive structure 207 second conductive structures
300 chip 2 400 chips three
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise Embodiment, broadly falls into the scope of protection of the invention.
Embodiment 1:
As Fig. 1 is to shown in 10, and it contains the making side of the encapsulating structure imbedding chip and flip-chip interconnection for the present invention Method flow process.As shown in Figure 10, a kind of encapsulating structure schematic diagram interconnected containing embedment chip and flip-chip of the present invention, described envelope Assembling structure comprises a silicon substrate 100, and described silicon substrate 100 is formed at least one groove 101, the merit of at least one chip 1 Can face up in embedment groove 101.The chip 1 of embedment constitutes close plane with surface, silicon substrate 100 place, described It is formed with insulating barrier 103 in plane, described insulating barrier 103 is formed an at least one rewiring layer 204 at least chip 2 300 and falls Dress interconnection on the plane, described plane is also formed with the first conductive structure 206.Advantage of this is that: encapsulation volume Little, integrated level is high, and is all ripe technique, and product reliability is good, and yield is high.
Encapsulating structure that a kind of multi-chip of the present invention is integrated and preparation method thereof, it comprises the following steps that Fig. 19 institute Show, below in conjunction with accompanying drawing, specific make step illustrated:
As it is shown in figure 1, the fan-out silicon substrate 100 used by the present invention, described silicon substrate is silicon substrate in the present embodiment；
As in figure 2 it is shown, be the structural representation forming groove 101 on a silicon substrate, the shape wherein forming groove 101 can Be rectangle, trapezoidal in one or both combine, it is also possible to be other geometry.Consideration based on Technology, this Invention uses trapezoidal groove.Described groove 101 extends to relative surface from the one side of silicon substrate 100, and distance is relatively Surface certain distance.
As it is shown on figure 3, the functional surfaces of chip 1 to be imbedded upward the structural representation of groove 101.Bonding pattern is permissible The polymer such as adhesive glue or dry film 3 is used to be mounted by the functional surfaces of chip 1 in the groove 101 of silicon substrate upward, viscous Gum deposit water or dry film can be coated in groove 101, it is also possible to be coated in the bottom of chip 1, or both of which has.
As shown in Figure 4, the chip 1 of embedment and surface, silicon substrate 100 place constitute close plane, and described flat Insulating barrier 103 is laid in face.
The material of described insulating barrier 103 can be inorganic insulating material such as silicon dioxide or organic dielectric insulation material, The preparation of insulating barrier 103 can use low temperature chemical vapor deposition or polymer spraying or the method for polymer spin coating.
As it is shown in figure 5, the structural representation that the weld pad 201 on described insulating barrier 103 is come out.
The mode that weld pad 201 comes out can be by exposure, develop by the present embodiment, and etch away on weld pad Oxide layer.
As shown in Figure 6, described insulating barrier 103 is formed the structural representation of at least one rewiring 204, lays at least one Layer the first metal reroutes, and makes described first metal rewiring electrically connect with the weld pad of chip 1, described first metal weight Pad it is formed with in wiring.When being embodied as, the metal material of every layer of metal rewiring 204 can be copper, nickel, target, Jin Dengzhong One or more, formed metal reroute 204 method can be plating, chemical plating, vacuum vapour deposition, chemical gaseous phase deposit One in method.
Preferably, the formation process that described first metal reroutes and described second metal reroutes is included in insulating barrier Deposit on 103 seed metal layer, gluing, photoetching, expose, develop, electroplate, remove photoresist, Seed Layer etching；Or, at insulating barrier 103 Upper whole deposition seed metal layer, in seed metal layer, photoetching exposes metal rewiring figure, at the metal weight exposed Electroplate/change plating mode on wiring pattern and form metallic circuit, finally, go seed metal layer in addition to graphics, form metal weight cloth Line 204.
As it is shown in fig. 7, rerouting the structural representation forming protective layer 205 on 204, the material of protective layer 205 is permissible It is dry film or other polymer.
As shown in Figure 8, on protective layer 205 formed opening 202 structural representation, described opening 202 can by exposure, Development is formed.
As it is shown in figure 9, flip-chip 2 300 to be electrically interconnected to what the chip 1 of embedment and silicon substrate 100 were constituted Structural representation after plane, electrically the mode of interconnection can use between the opening 202 of chip 2 300 and protective layer 205 Coating electric-conductivity heat-conductivity high colloid is attached, it would however also be possible to employ the mode of gold gold bonding or the mode of gold stannum bonding, in this enforcement In example, utilizing the second conductive structure 207 to realize electrically interconnecting, conductive structure can be soldered ball or conducting resinl.Form conduction knot The mode of structure can be to plant ball or plating soldered ball.
As shown in Figure 10, the first conductive structure 206 is formed at the opening 202 of packaging body protective layer 205 after bonding.
Embodiment 2
The structural representation of another kind embodiment as of the present invention in Figure 11, as different from Example 1, with embedment chip and The flip-chip that the plane that silicon substrate is constituted electrically interconnects is two chips: chip 3 400 and chip 4 500.
Preferably, carrying out these chips being bonded, its function can be the same or different, or incomplete same.
Embodiment 3
Such as the structural representation of Figure 12 one embodiment of the invention, unlike the embodiments above is to imbed the groove of chip not It it is rectangle.
Embodiment 4
Such as the structural representation of Figure 13 further embodiment of this invention, this embodiment is different from the groove shapes of embodiment 1.
Preferably, the shape of described groove can be rectangle, trapezoidal or other geometry.Groove in the present embodiment It is shaped as trapezoidal.
It should be added that, in the present invention, the chip size with embedment chip bonding can be less than described chip, also Described chip can be more than, be less than embedment chip size described in the present embodiment, identical with embedment chip size at other Or in the case of relatively big, all fall within protection scope of the present invention.

Claims (10)

1. the encapsulating structure interconnected containing embedment chip and flip-chip, it is characterised in that: comprise at least one silicon substrate (100), at least one chip one (200)；At least one groove (101) it is formed with on described silicon substrate (100)；Chip one (200) functional surfaces imbeds groove (101) upward；Bondd by polymer (3) between chip 200 and silicon substrate 100；Embedment chip One (200) constitutes close plane with silicon substrate (100) surface, place, is formed with insulating barrier (103) on the plane, described Being formed with at least one of which on insulating barrier (103) and reroute layer (204), at least one chip two (300) flip-chip interconnection is described flat On face；The first conductive structure (206) it is also formed with in described plane.
A kind of encapsulating structure interconnected containing embedment chip and flip-chip, it is characterised in that: fall The size of cartridge chip two (300) is more than the size of groove (101) chips one (200) or less than groove (101) chips one (200) size or the size equal to groove (101) chips one (200).
A kind of encapsulating structure interconnected containing embedment chip and flip-chip, it is characterised in that: fall When the quantity of the chip two (300) of dress is multiple, the function of each chip two (300) and the merit of the chip one (200) with embedment thereof Can be identical or different.
A kind of encapsulating structure interconnected containing embedment chip and flip-chip, it is characterised in that: core After sheet two (300) upside-down mounting, relative to described plane, the height of the first conductive structure (206) is not less than the highest of chip two (300) The height of point.
A kind of encapsulating structure interconnected containing embedment chip and flip-chip, it is characterised in that: core Sheet two (300) is electrically interconnected to described plane by heat-conductivity conducting glue.
A kind of encapsulating structure interconnected containing embedment chip and flip-chip, it is characterised in that: core Sheet two (300) is electrically interconnected to described plane by conductive structure.
7. the manufacture method of the encapsulating structure interconnected containing embedment chip and flip-chip, it is characterised in that: comprise following Step:
A., one substrate with at least one groove is provided；
By the functional surfaces of at least one chip one upward, and be bonded in groove b.；
C. contain on the surface of functional chip one at described substrate, on the functional surfaces of the chip one and gap of chip one and groove In all lay insulating barrier；
D. on partial insulative layer, form at least one of which reroute；
E. on described insulating barrier with described rewiring layer, form protective layer；
F. on described protective layer, form opening, make part reroute and come out；
H. flip-chip two is electrically interconnected to imbed the plane that chip one is constituted with substrate；
G. constituted at embedment chip one and substrate and in close plane, formed the first conductive structure.
8. the manufacture method of the encapsulating structure interconnected containing embedment chip and flip-chip as claimed in claim 7, its feature Be: formed the step of the first conductive structure the plane that flip-chip two is electrically interconnected to imbed chip one and substrate is constituted it Before, form the first conductive structure by printing, plant at least one mode in ball, plating.
A kind of manufacture method of the encapsulating structure interconnected containing embedment chip and flip-chip, its It is characterised by: after flip-chip two is electrically interconnected to imbed the plane of chip one and substrate composition, then by planting in ball, plating At least one mode form the first conductive structure.
A kind of manufacture method of the encapsulating structure interconnected containing embedment chip and flip-chip, its It is characterised by: the material forming the first conductive structure is same or like with the bonding material material of flip-chip two.
CN201610541089.1A 2016-07-11 2016-07-11 A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof Pending CN106129015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610541089.1A CN106129015A (en) 2016-07-11 2016-07-11 A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610541089.1A CN106129015A (en) 2016-07-11 2016-07-11 A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof

Publications (1)

Publication Number Publication Date
CN106129015A true CN106129015A (en) 2016-11-16

Family

ID=57282764

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610541089.1A Pending CN106129015A (en) 2016-07-11 2016-07-11 A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof

Country Status (1)

Country Link
CN (1) CN106129015A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449555A (en) * 2016-12-09 2017-02-22 华进半导体封装先导技术研发中心有限公司 Chip packaging process and chip packaging structure
CN109326580A (en) * 2018-11-20 2019-02-12 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 A kind of multi-chip package interconnection structure and multi-chip package interconnection method
CN110491792A (en) * 2019-09-16 2019-11-22 中国电子科技集团公司第五十八研究所 A kind of resin type three-dimensional is fanned out to integrated encapsulation method and structure
CN110931477A (en) * 2019-11-28 2020-03-27 徐州顺意半导体科技有限公司 A kind of intelligent power module and preparation method thereof
CN114334944A (en) * 2021-12-01 2022-04-12 长电科技管理有限公司 A kind of packaging structure and manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2765329Y (en) * 2005-02-04 2006-03-15 胜开科技股份有限公司 Image sensor
CN104795380A (en) * 2015-03-27 2015-07-22 江阴长电先进封装有限公司 Three-dimensional packaging structure
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2765329Y (en) * 2005-02-04 2006-03-15 胜开科技股份有限公司 Image sensor
CN104795380A (en) * 2015-03-27 2015-07-22 江阴长电先进封装有限公司 Three-dimensional packaging structure
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449555A (en) * 2016-12-09 2017-02-22 华进半导体封装先导技术研发中心有限公司 Chip packaging process and chip packaging structure
CN109326580A (en) * 2018-11-20 2019-02-12 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 A kind of multi-chip package interconnection structure and multi-chip package interconnection method
CN110491792A (en) * 2019-09-16 2019-11-22 中国电子科技集团公司第五十八研究所 A kind of resin type three-dimensional is fanned out to integrated encapsulation method and structure
CN110931477A (en) * 2019-11-28 2020-03-27 徐州顺意半导体科技有限公司 A kind of intelligent power module and preparation method thereof
CN110931477B (en) * 2019-11-28 2021-12-07 国网江苏省电力有限公司常州供电分公司 Intelligent power module and preparation method thereof
CN114334944A (en) * 2021-12-01 2022-04-12 长电科技管理有限公司 A kind of packaging structure and manufacturing method

Similar Documents

Publication Publication Date Title
US20230223365A1 (en) Semiconductor device and manufacturing method thereof
US10224272B2 (en) Semiconductor package including a rewiring layer with an embedded chip
US10559525B2 (en) Embedded silicon substrate fan-out type 3D packaging structure
CN103681607B (en) Semiconductor devices and preparation method thereof
CN102194717B (en) Semiconductor device and form the method for insulating barrier around semiconductor element
CN102420180B (en) Semiconductor device and its manufacture method
CN101989558B (en) Semiconductor device and method of producing the same
CN102598258B (en) For multiple surface treatments of microelectronic package substrate
CN110197793A (en) A kind of chip and packaging method
CN102024716B (en) The method of semiconductor device and manufacture semiconductor device
US9230901B2 (en) Semiconductor device having chip embedded in heat spreader and electrically connected to interposer and method of manufacturing the same
US9847284B2 (en) Stacked wafer DDR package
CN106129015A (en) A kind of encapsulating structure containing embedment chip and flip-chip interconnection and preparation method thereof
CN102376595A (en) Method and semiconductor device of forming FO-WLCSP having conductive layers and conductive vias
CN102163561A (en) Semiconductor device and method of forming tmv and tsv in wlcsp using same carrier
CN102931173A (en) Multi-chip wafer level package
CN207852651U (en) Semiconductor package with antenna module
US8847412B2 (en) Microelectronic assembly with thermally and electrically conductive underfill
US7498199B2 (en) Method for fabricating semiconductor package
CN116314109A (en) Semiconductor device
CN113990815B (en) Silicon-based micromodule plastic packaging structure and preparation method thereof
US20120286398A1 (en) Semiconductor chip module and planar stack package having the same
US7518211B2 (en) Chip and package structure
CN105428327B (en) Fan-out type wafer level package structure
CN115394768B (en) A multi-layer high bandwidth memory and a manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20161116