CN106101585B - Low-noise CCD camera circuit - Google Patents

Abstract

The invention is a low-noise CCD camera circuit, which includes an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology; RC low-pass filter switch KG; preamplifier circuit QF includes operational amplifier U; resistor R connected to the same phase input terminal of operational amplifier U; resistor R1 and resistor R2 connected to the reverse input terminal of operational amplifier U; resistor R2 and A Schottky diode D connected in parallel to the reverse input terminal of the operational amplifier U; resistors RS1 and RS2 connected to the output terminal of the operational amplifier U; a switch Ks and a capacitor Cs form a bandwidth-adjustable switch KG; the invention provides a small, A low-noise CCD camera circuit with light weight, low power consumption, strong anti-interference ability, high safety and reliability, and flexible design and strong scalability can effectively reduce noise and improve the dynamic range of the CCD camera.

Description

A Low Noise CCD Camera Circuit

technical field

The invention belongs to the field of optoelectronics, and relates to a method and system for realizing a low-noise CCD camera circuit, in particular to a CCD remote-sensing camera circuit aimed at the fields of astronomical observation and deep-space detection with low-noise requirements.

Background technique

Because CCD has the characteristics of high quantum efficiency, good linearity and low noise, it has been widely used in aerospace and other fields, especially in low-illumination, low-light target astronomical observation and other fields. However, noise has become the main obstacle to the completion of weak light observation tasks. With the continuous development of CCD devices towards miniaturization and integration, the increase in the number of CCD photosensitive elements will inevitably reduce the area of photosensitive elements, thereby reducing the output saturation signal of CCD. . In order to expand the dynamic range of the CCD, it is necessary to reduce the noise of the CCD camera, otherwise it cannot be applied to astronomical observation tasks of high-precision, low-light targets.

The noise of the CCD camera system can be summed up mainly including photon noise, reset noise, dark current noise, thermal noise, off-chip amplifier noise, 1/f noise and quantization noise. The photon noise is the inherent noise of the CCD, which represents the limit of the highest signal-to-noise ratio of the CCD camera system. CCD thermal noise and dark current can be effectively reduced by cooling the CCD. The remaining reset noise, 1/f noise and AD quantization noise can be minimized by low-noise circuit design.

Contents of the invention

In order to solve the above-mentioned technical problems in the background technology, the present invention provides a low-noise CCD camera circuit with small size, light weight, low power consumption, strong anti-interference ability, high safety and reliability, and strong design flexibility and expansion capability. It can effectively reduce the noise and improve the dynamic range of the CCD camera.

The technical solution of the present invention is: a low-noise CCD camera circuit, characterized in that: the CCD camera circuit includes an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology;

The analog front-end circuit includes a DC blocking capacitor C, a front-stage in-phase amplifier circuit QF and an adjustable bandwidth RC low-pass filter switch KG; the front-stage amplifier circuit QF includes an op-amp U; the resistor connected to the in-phase input of the op-amp U R; Resistor R1 and resistor R2 connected to the reverse input terminal of the operational amplifier U; Schottky diode D connected in parallel with the resistor R2 and the reverse input terminal of the operational amplifier U; resistor RS1, resistor RS2 are connected to the output terminal of the operational amplifier U The switch Ks and the capacitor Cs form a bandwidth adjustable switch KG; the opening and closing of the Ks analog switch is switched according to the phase relationship of the current CCD video signal output voltage waveform, thereby changing the bandwidth of the analog front end;

The digital sampling circuit of the CCD camera includes high-speed ADC and FPGA; the high-speed ADC samples and converts the CCD signal reference level and pixel level, and the FPGA realizes the control of high-speed sampling of the ADC, digital low-pass filtering and digital CDS.

The above-mentioned high-speed ADC is correlated double sampling. If the pixel clock frequency of the CCD is f _CcD , then the sampling frequency f _SAMPLE =2f _CCD , which is twice the pixel clock frequency.

It also includes a digital low-pass filter LP, which uses multiple sampling points for averaging and is implemented in FPGA. Under the condition of timing relationship, 2n sampling points are collected, and then averaged to remove high-frequency noise and Reduce quantization noise.

It also includes digital CDS, which is the difference between the reference level and the pixel level sampling point, and suppresses the reset noise and low-frequency noise of the _CCD video signal. Carry out subtraction operation with the pixel level conversion value _Spix to obtain the required digital image.

The invention has the advantages of small size, light weight, low power consumption, strong anti-interference ability, high safety and reliability, strong design flexibility and expansion ability; it can effectively reduce noise and improve the dynamic range of the CCD camera. Using FPGA to realize high-speed sampling, digital low-pass filtering and digital CDS can not only further remove high-frequency noise introduced by the analog front-end, reduce quantization noise, but also effectively remove correlation noise between pixels. At the same time, it is implemented by FPGA, which has the advantages of simple structure and convenient implementation.

Description of drawings

Fig. 1 is a schematic diagram of an analog front-end circuit with adjustable bandwidth of the present invention;

Fig. 2 is a CCD video signal output voltage waveform diagram of the present invention;

Fig. 3 is the low-noise digital sampling circuit schematic diagram based on CDS technology of the present invention;

Fig. 4 is the digital sampling time sequence diagram of the present invention;

detailed description

The invention provides a low-noise CCD camera circuit realization method and system thereof, which is composed of two parts: an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology.

1. Analog front-end circuit; as shown in Figure 1. It is composed of three parts: a DC blocking capacitor, a pre-amplifier circuit QF and an RC low-pass filter switch KG with adjustable bandwidth. Since the output signal of the CCD is a negative space discrete analog signal floating on a DC level (usually more than ten volts). If the signal is directly used for post-stage amplification and analog-to-digital conversion, it is easy to saturate the amplifier and ADC, and it is not conducive to the extraction of useful signals. Therefore, the signal must be subjected to pre-processing such as DC blocking and amplification. This patent proposes an analog front-end circuit with adjustable bandwidth, where C is a DC blocking capacitor, U, R, R1, R2 and D form a preamplifier circuit QF, and its purpose is to adjust the signal level to high-speed analog-to-digital conversion within the input range of the device; D: Schottky diode, used to filter out a part of the reset pulse spike. RS1, RS2, Ks and Cs form a bandwidth adjustable switch KG. The opening and closing of the Ks analog switch is switched according to the phase relationship of the current CCD video signal output voltage waveform, thereby changing the bandwidth of the analog front end. The corner frequency of the RC low-pass filter is f0=1/2πRC, and the position of the corner frequency changes with RC. If the capacitance remains the same, the resistance of the low-pass resistor decreases from RS1 to RS2, and the corner frequency shifts to the high frequency end.

The characteristics of the signal output by the CCD: as shown in Figure 2, some high-frequency components (reset peaks) are mixed in the reset pulse A, while the reference level B and the pixel level C are relatively stable. In order to further reduce the noise of the analog front end, the bandwidth switch is switched according to the phase relationship of the CCD output signal. When the reset pulse comes, KS hits RS1, and the corner frequency of the RC low-pass filter is low, which can effectively filter out high-frequency components in the reset pulse; when the reference level and pixel level come, KS hits RS2, The corner frequency of the RC low-pass filter is high, so that the CCD reference level and pixel level can pass through without loss as much as possible.

2. Low-noise digital sampling circuit based on CDS technology:

As shown in Figure 3, it consists of high-speed ADC and FPGA. The purpose of the digital sampling circuit of the CCD camera is to collect accurate CCD signals and reduce the noise of the CCD as much as possible. Since reset noise is the main source of interference in the CCD output signal, and can be suppressed by peripheral sampling processing circuits, correlated double sampling technology can effectively filter out reset noise, so CCD camera sampling circuits generally use analog domain CDS circuits.

The circuit is composed of high-speed ADC and FPGA. The circuit first performs high-speed analog-to-digital conversion, then performs low-pass filtering (LP) of the sampled signal in the digital domain, and finally performs digital subtraction in the digital domain to achieve correlated double adoption. The advantage of doing CDS processing in the digital domain is that the digital subtractor is more accurate. The circuit uses few types of components (two types), which greatly improves the reliability of the circuit. In addition, there are many types of analog-to-digital converters to choose from, which can increase the flexibility of circuit design.

The purpose of the high-speed ADC is to perform sampling and analog-to-digital conversion on the CCD signal reference level and pixel level. Since it is correlated double sampling, if the pixel clock frequency of the CCD is f _CcD , then the sampling frequency f _SAMPLE =2f _CCD , which is twice the pixel clock frequency. Therefore, the highest operating frequency of the selected analog-to-digital converter is at least 2 times the pixel clock frequency. The number of bits of the analog-to-digital converter is selected according to the dynamic range of the CCD signal and application requirements.

可以进一步去除模拟前端引入的高频噪声和降低量化噪声；Digital low-pass filter (LP): the implementation form uses multiple sampling points to calculate the average. Since it is implemented in the FPGA, under the condition that the timing relationship allows, generally 2n sampling points are collected, as shown in Figure 3, and then averaged

It can further remove the high frequency noise introduced by the analog front end and reduce the quantization noise;

Digital CDS: It is actually the difference between the reference level and the pixel level sampling point. It can effectively suppress the reset noise and low frequency noise of the CCD video signal. The implementation is in the form of a digital subtractor. The digital subtractor performs subtraction operation on the CCD signal reference level conversion value S _ref and the pixel level conversion value S _pix to obtain the required digital image S _img =S _pix S _ref . Since S _ref and S _pix perform analog-to-digital conversion successively in chronological order, the digital subtractor only needs to perform subtraction processing on the current conversion value and the conversion value at the previous moment.

Claims (4)

1. a low-noise CCD camera circuit, characterized in that: said CCD camera circuit includes an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology; The analog front-end circuit includes a DC blocking capacitor C, a front-stage in-phase amplifier circuit QF and an adjustable bandwidth RC low-pass filter switch KG; the front-stage amplifier circuit QF includes an operational amplifier U; the resistor connected to the in-phase input terminal of the operational amplifier U R; resistor R1 and resistor R2 connected to the reverse input terminal of op amp U; Schottky diode D connected in parallel with resistor R2 and the reverse input terminal of op amp U; one end of resistor RS1 and resistor RS2 is connected to the output of op amp U The switch Ks and the capacitor Cs form a bandwidth-adjustable switch KG; one end of the switch Ks is connected to the other end of the resistor RS1 or the resistor RS2; the other end of the switch Ks is connected to one end of the capacitor Cs; the resistor R, the resistor R1, and the capacitor Cs The other end of both are grounded; The opening and closing of the switch Ks is switched according to the phase relationship of the current CCD video signal output voltage waveform, changing the bandwidth of the analog front end; when the reset pulse comes, the switch KS hits the resistor RS1, and the corner frequency of the RC low-pass filter is low , to filter out the high-frequency components in the reset pulse; when the reference level and pixel level come, the switch KS hits the resistor RS2, and the corner frequency of the RC low-pass filter is high, so that the CCD reference level and pixel level pass through without loss; The digital sampling circuit of the CCD camera includes high-speed ADC and FPGA; the high-speed ADC samples and converts the CCD signal reference level and pixel level, and the FPGA realizes the control of high-speed sampling of the ADC, digital low-pass filtering and digital CDS. 2. low-noise CCD camera circuit according to claim 1, is characterized in that: described high-speed ADC is correlated double sampling, if the pixel clock frequency of CCD is

, then the sampling frequency

, which is twice the pixel clock frequency. 3. the low-noise CCD camera circuit according to claim 2, is characterized in that: also comprise digital low-pass filter LP, adopts a plurality of sampling points to average, realizes in FPGA, under the condition that timing relation allows, gathers 2n sampling points, and then take the average to remove the high-frequency noise introduced by the analog front end and reduce the quantization noise. 4. the low-noise CCD camera circuit according to claim 3, is characterized in that: also comprise digital CDS, is the difference of reference level and pixel level sampling point, suppresses reset noise and low-frequency noise of CCD video signal, and realization form It is a digital subtractor, which converts the reference level of the CCD signal

and pixel level translation values

Carry out the subtraction operation to get the required digital image.

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