JP2009065278A - Filter circuit, receiver using the same, and filtering method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a filter circuit capable of eliminating disturbing waves with accuracy. <P>SOLUTION: The filter circuit is provided with a sampler 110 for generating a first analog signal by sampling an input signal; an analog-digital converter 121 for converting the first analog signal into the first digital signal; a digital filter 122 for extracting a signal component outside a desired band from the first digital signal to generate a second digital signal; a digital-analog converter 130 for converting the second digital signal into a second analog signal; a delay device 140 for outputting a third analog signal by giving signal delay equal to the delay time of the second analog signal, with respect to the first analog signal; and a subtractor 150 for subtracting the second analog signal from a third analog signal, to generate an output signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a filter circuit that removes an interference wave from a received signal, a receiver using the filter circuit, and a filtering method.

  In a receiver in a radio communication system, a received signal obtained from an antenna that receives a radio signal is amplified by a low noise amplifier, and further down-converted by a frequency converter to generate a received baseband signal. A signal in a desired band is extracted from the received baseband signal by, for example, a low-pass filter, and is converted into a digital received signal by an analog-digital converter. At this time, a filter circuit for removing an interference wave may be provided before the analog-digital converter.

  Here, the interference wave refers to an unnecessary signal outside the desired band. For example, a radio signal transmitted from another transmitter, a radio signal transmitted from the transceiver body, or unnecessary radiation from another IC is assumed. .

  The filter circuit described in Non-Patent Document 1 includes a first automatic gain control circuit, an analog-digital converter, a notch filter, an adaptive filter, a digital-analog converter, an analog delay element, a subtractor, and a second automatic gain. Includes control circuitry. The filter circuit includes a first path constituted by a first automatic gain control circuit, an analog-digital converter, a notch filter, an adaptive filter and a digital-analog converter, and a second constituted by an analog delay element. Branch the input signal to the path.

  An input signal passing through the first path is controlled in signal amplitude by a first automatic gain control circuit and converted into a digital signal by an analog-digital converter. An interference wave component is extracted from the digital signal by a notch filter and an adaptive filter, and the interference wave component is converted into an analog signal by a digital-analog converter. In the second path, the analog delay element gives the input signal a signal delay corresponding to the delay time of the first path.

Signals from the first and second paths are input to a subtracter, and the subtracter subtracts the signal that has passed through the first path from the signal that has passed through the second path, thereby removing the interference wave component. The signal from which the interference wave component has been removed is adjusted in signal amplitude by the second automatic gain control circuit, and is output to the subsequent analog-digital converter.
Danijela et al, "Novel Radio Architectures for UWB, 60GHz, and Cognitive Wireless Systems," EURASIP Journal on Wireless Communications and Networking, Vol. 2006, Article ID 17957, pp. 1-18.

  In the filter circuit described in Non-Patent Document 1, digital signal processing, that is, discrete time signal processing is performed in the first path, and the delay time is accurately determined based on the clock. On the other hand, in the second path, the analog delay element must give the input signal a signal delay equivalent to the delay time. However, the delay time given to the input signal by the analog delay element is not constant because it depends on the frequency of the input signal, and further varies depending on parameters such as temperature and process conditions.

  Therefore, it is difficult to accurately match the delay times of the first and second paths, and a delay time shift occurs. If the delay times of the signals from both paths do not match, the subtractor cannot accurately remove the interference wave component. Tuning is required to compensate for changes in delay time due to temperature and process conditions.

  Accordingly, an object of the present invention is to provide a filter circuit capable of accurately removing interference waves.

  A filter circuit according to an aspect of the present invention includes a sampler that samples an input signal to generate a first analog signal; an analog-to-digital converter that converts the first analog signal into a first digital signal; A digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal; and a digital-analog converter that converts the second digital signal into a second analog signal A delay unit for providing the first analog signal with a signal delay equal to a delay time of the second analog signal with respect to the first analog signal and outputting a third analog signal; and the third analog signal. And a subtractor for subtracting the second analog signal to generate an output signal.

  A filter circuit according to another aspect of the present invention includes a sampler that samples an input signal to generate a first analog signal; an analog-to-digital converter that converts the first analog signal into a first digital signal; A digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal; and ΔΣ-modulates the second digital signal to output a third digital signal; A ΔΣ modulator that converts the third digital signal into a second analog signal; and a signal delay equal to a delay time of the second analog signal relative to the first analog signal. A delayer for supplying a first analog signal and outputting a third analog signal; subtracting the second analog signal from the third analog signal; A subtractor for generating a grayed signal; -; comprising said fourth analog signal the analog filter to produce an output signal by removing quantization noise generated in the digital converter.

  A filter circuit according to another aspect of the present invention includes a sampler that samples an input signal to generate a first analog signal; and a first analog-digital that converts the first analog signal into a first digital signal. A converter; a digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal; and a third filter configured by higher-order bits of the second digital signal A digital-to-analog converter for converting a digital signal into a second analog signal; applying a signal delay to the first analog signal equal to a delay time of the second analog signal relative to the first analog signal; A first delay unit for outputting a second analog signal; a first subtractor for subtracting the second analog signal from the third analog signal to generate a fourth analog signal; A second analog-to-digital converter for converting the fourth analog signal into a fourth digital signal; and a signal delay equal to a delay time of the fourth digital signal with respect to the second digital signal. A second delayer for supplying a fifth digital signal composed of lower bits of the second digital signal and outputting a sixth digital signal; and subtracting the sixth digital signal from the fourth digital signal; And a subtractor for generating an output signal.

  A filter circuit according to another aspect of the present invention includes a first sampler that samples an input signal to generate a first analog signal; a second sampler, and the input signal is sampled by the second sampler. An analog-to-digital converter that converts the generated second analog signal into a first digital signal; and extracts a signal component outside a desired band from the first digital signal to generate a second digital signal. A digital filter; a digital-to-analog converter that converts the second digital signal into a third analog signal; and a signal delay equal to a delay time of the third analog signal relative to the second analog signal. A delay unit for supplying a first analog signal and outputting a fourth analog signal; subtracting the second analog signal from the fourth analog signal; And generate subtractor; comprises a.

  A filter circuit according to another aspect of the present invention includes a sampler that samples an input signal to generate a first analog signal; extracts a low-frequency component from the first analog signal, and outputs a second analog signal A decimator that downsamples the second analog signal and outputs a third analog signal; an analog-to-digital converter that converts the third analog signal into a first digital signal; A digital filter that extracts a signal component outside a desired band from one digital signal to generate a second digital signal; a digital-analog converter that converts the second digital signal to a fourth analog signal; A signal delay equal to the delay time of the fourth analog signal relative to the third analog signal is applied to the third analog signal; A delay unit for outputting a signal; comprises a; subtracting said fourth analog signal from said fifth analog signal, and a subtractor for generating the output signal.

  ADVANTAGE OF THE INVENTION According to this invention, the filter circuit which can remove an interference wave accurately can be provided.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
As shown in FIG. 1, the filter circuit 100 according to the first embodiment of the present invention is inserted between the frequency converter 10 and the analog-digital converter 20, and includes a sampler 110, an analog-digital converter 121, A digital filter 122, a digital-analog converter 130, a delay device 140, and a subtractor 150 are included.

  The frequency converter 10 down-converts a reception signal received by an antenna (not shown) to generate a reception baseband signal. In addition to the desired wave, the baseband signal includes an interference wave component having a larger amplitude than the desired wave, and the filter circuit 100 according to the present embodiment removes the interference wave component. The signal from the filter circuit 100 is converted into a digital signal by the analog-digital converter 20 and demodulated by a digital processing unit (not shown).

  The sampler 110 samples the received baseband signal from the frequency converter 10 at a predetermined sampling frequency and discretizes it in time. The analog discrete time signal from the sampler 110 branches to a first path composed of the analog-to-digital converter 121, the digital filter 122 and the digital-analog converter 130 and a second path composed of the delay unit 140. Is done.

Hereinafter, a charge sampler will be described as an example of the sampler 110 with reference to FIG. Charge sampler shown in FIG. 2 is a trans configuration Dunk chest amplifier gm ₁₁₀ for converting a voltage input to a current, a capacitor C ₁₁₀ to charge sampling an output current of the transconductance amplifier gm _110, controls the charge samples A switch SW _110-1 for resetting, and a switch SW _110-2 for resetting the charge of the capacitor C ₁₁₀ .

The two switches SW _110-1 and SW _110-2 operate in a complementary manner, and when one is on, the other is off. During the switch SW _110-1 is turned on, the output current of the transconductance amplifier gm ₁₁₀ is charged sample by the capacitor C _110, the switch SW _110-2 charges the capacitor C ₁₁₀ between ON is reset. The sampler 110 is not limited to the charge sampler shown in FIG. 2, but may be a voltage sampler, for example.

  The analog-to-digital converter 121 converts the analog discrete time signal from the sampler 110 into a digital signal and passes the digital signal to the digital filter 122.

  The digital filter 122 extracts an interference wave component outside the desired band from the digital signal from the analog-digital converter 121, and generates a digital signal including the interference wave component. The digital-analog converter 130 converts the interference wave component included in the digital signal generated by the digital filter 122 into an analog discrete time signal.

  Further, the digital filter 122 and the digital-analog converter 130 generate quantization noise in the desired wave frequency band. Accordingly, the bit resolution (quantization bit number) required for the digital filter 122 and the digital-analog converter 130 is determined by the signal-to-noise ratio required for the system. Specifically, since the dynamic range corresponding to 1 bit is about 6 dB, at least 1 per 6 dB of the ratio of the input signal outside the desired band to the input signal within the desired band and the sum of the signal-to-noise ratio within the desired band. A bit is required.

  In a normal wireless circuit, the bit resolution of the digital-analog converter 130 is higher than the bit resolution of the analog-digital converter 121. In general, the digital-analog converter is more analog if the bit resolution is the same. -It can be designed to consume less power than a digital converter.

Hereinafter, an example of the digital-analog converter 130 will be described with reference to FIGS. 3A and 3B. The digital-analog converter having a bit resolution N illustrated in FIG. 3A includes N capacitors C _{130-1 to} C _130-N and switches SW _{130-1 to} SW _130-N that switch connection of the capacitors. The capacitors C _{130-1 to} C _130-N correspond to each bit of the digital signal input to the digital-analog converter. That is, the capacitor C _130-1 corresponds to the least significant bit, and the capacitor C _130-N corresponds to the most significant bit. The capacitance of each capacitor C _130-1 to C _130-N are weighted in binary weighted twice the capacitance of the capacitor C _130-2 is a capacitor C _130-1, the capacitance of the capacitor C _130-N is a capacitor C ^2N-1 times _130-1 .

The switches SW _{130-1 to} SW _130-N repeat the switching operation with two phases as one cycle as shown in FIG. 3B. In phase 1, the switches SW _{130-1 to} SW _130-N connect the capacitors C _{130-1 to} C _130-N to the reference voltage Vref + or Vref−. Note that whether the reference voltage Vref + or Vref− is connected in phase 1 depends on whether the output of the digital filter 122 is at the “high (H)” level or the “low (L)” level for the bit corresponding to the capacitor. It depends on which one is. In this phase 1, charges corresponding to the digital input are accumulated in the capacitors C _{130-1 to} C _130-N . On the other hand, in phase 2, the switches SW _{130-1 to} SW _130-N connect the capacitors C _{130-1 to} C _130-N to the output Qout of the digital-analog converter, and the capacitors C _{130-1 to} C ₁₃₀ are connected. _The charge accumulated in _-N is superimposed and output as an analog discrete time signal.

  Note that in order to accurately remove the interference wave in the filter circuit according to the present embodiment, it is necessary to match the gain by the first path and the gain by the second path at the interference wave frequency. In order to make the gains by both paths coincide, for example, when the digital-analog converter of FIG. 3A is used as the digital-analog converter 130, the reference voltages Vref + and Vref- are adjusted, and the output analog discrete-time signal May be controlled to an appropriate value.

  Delay 140 provides the analog discrete time signal from sampler 110 with a signal delay equal to the delay generated in the first path, ie, analog to digital converter 121, digital filter 122 and digital to analog converter 130. Since the analog-to-digital converter 121, the digital filter 122, and the digital-to-analog converter 130 are clock-controlled, the delay time generated in the first path is obtained as a discrete value obtained by multiplying the clock period by a constant. Therefore, by using a simple digital circuit such as a counter that counts the number of clocks, the delay unit 140 can grasp the delay time.

Hereinafter, an example of the delay device 140 will be described with reference to FIGS. 4A and 4B. The delay device shown in FIG. 4A is configured by arranging in parallel K unit circuits each having a capacitor C provided between two switches SW _in and SW _out and between the switches SW _in and SW _out (K Is any integer greater than or equal to 2). The delay device of FIG. 4A can generate a signal delay of an arbitrary clock from 1 to K-1.

The input signal is connected to any one of the capacitors C _{140-1 to} C _140-k by K switches SW _{140-in1 to} SW _140-ink , and the input charge is accumulated. That is, the switches SW _{140-in1 to} SW _140-ink operate exclusively, and all the other switches are off while one switch is on. In the initial state, it is assumed that no charges are accumulated in all the capacitors C _{140-1 to} C _140-k . Thereafter, similarly, the input charge is successively accumulated in the capacitor in which the input charge is not accumulated.

Similarly, SW _{140-out1 to} SW _140-outk operate exclusively and output the input charges stored in the corresponding capacitors when a predetermined delay time has elapsed. For example, FIG. 4 shows the operation of SW _140-inj and SW _140-outj when the delay time is D clock (D is an arbitrary integer less than K, and j is an arbitrary integer between 1 and K). First, the input charge is stored in the capacitor C _140-inj via the SW _140-inj . Similarly, until the (D-1) clock elapses, the input charges are successively accumulated in the capacitor in which the input charge is not accumulated, and when the D clock elapses, the input charges are accumulated in the capacitor C _140-j via the SW _140-outj. The input charge that has been stored is taken out, and then the charge stored in the capacitor C _140-j is reset to zero. Similarly, input charges are taken out from other capacitors in the order in which they are accumulated, and the accumulated charges are reset to zero. Similarly, the input charge input to the delay device at this time is stored in any of the (ND) capacitors in which the input charge is not stored.

  The subtracter 150 subtracts the analog discrete time signal that has passed through the second path from the analog discrete time signal that has passed through the first path, and passes this subtraction result to the analog-to-digital converter 20. Here, the analog discrete time signal that has passed through the first path includes both the desired wave and the disturbing wave, but the analog discrete time signal that has passed through the second path mainly includes only the disturbing wave. Therefore, the interference wave component can be removed by these subtractions.

  Here, in order to demodulate the original signal from the signal component in the desired band of the baseband signal, it is necessary to ensure the desired signal amplitude corresponding to several bits in the analog-digital converter. In general, in a radio communication system, an interference wave having a signal amplitude several tens of dB larger than a desired wave exists in a frequency band close to the desired band. Therefore, since the input amplitude of the analog-digital converter is saturated only by securing the desired signal amplitude, more bit resolution is required. Specifically, when the ratio of the voltage amplitude of the desired wave and the disturbing wave is LdB, at least L / 6 bits are required in addition to the bit resolution for ensuring the desired signal amplitude.

  The current consumption of the analog-digital converter is known to increase in proportion to the power of 2 with the bit resolution N as an index. However, in the filter circuit 100 according to the present embodiment, the analog-digital converter 130 is used. An analog-to-digital converter having a large bit resolution is equivalently provided. Since the bit resolution required for the subsequent analog-digital converter 20 can be reduced by the bit resolution of the analog-digital converter 130, the current consumption of the subsequent analog-digital converter 20 can be reduced.

Hereinafter, the filter circuit 100 according to the present embodiment will be described in comparison with the prior art.
In the prior art, since a sampler is not used, it is necessary to process an analog continuous time signal, and an analog delay element is used as a delay device. Therefore, as described above, delay time varies depending on signal frequency, temperature, process conditions, etc., and it is difficult to generate an accurate signal delay.

  On the other hand, since the filter circuit 100 according to the present embodiment uses the sampler 110, the delay device 140 can generate a signal delay accurately by holding and outputting a discrete time analog signal for a predetermined clock. Accordingly, since the signal delays generated in the first and second paths coincide with each other, the subtracter 150 can accurately remove the interference wave component. Further, since the delay time is determined by the number of clocks, the delay time only needs to be adjusted at the time of design. According to the filter circuit 100 according to the present embodiment, since the accuracy of interference wave cancellation is improved, it is possible to improve the bit resolution of an analog-digital converter that can be equivalently realized.

(Second Embodiment)
As shown in FIG. 5, the filter circuit 200 according to the second embodiment of the present invention is inserted between the frequency converter 10 and the analog-digital converter 20, and includes a sampler 110, an analog-digital converter 121, A digital filter 122, a ΔΣ converter 261, a digital-analog converter 230, a delay unit 240, a subtractor 150, and a filter 262 are included. In the following description, the same parts in FIG. 5 as those in FIG. 1 are denoted by the same reference numerals, and different parts will be mainly described.

  The ΔΣ modulator 261 performs ΔΣ modulation on the digital signal generated by the digital filter 122, and passes the modulated digital signal to the digital-analog converter 230. Since the ΔΣ modulator 261 performs feedback so that the error is reduced with respect to the low-frequency signal, the digital signal after ΔΣ modulation is driven out to the high frequency by the noise shaping effect.

  The digital-analog converter 230 converts the digital signal from the ΔΣ modulator 261 into an analog signal. Here, the bit resolution of the digital-analog converter 230 is determined by the signal-to-noise ratio required in the desired band, but since the quantization noise is noise-shaped by the ΔΣ modulator 261, the signal-to-noise ratio in the desired band can be suppressed. . Therefore, the digital-analog converter 230 can be configured with less bit resolution than the digital-analog converter 130 of FIG.

  The delay unit 240 provides the analog discrete-time signal from the sampler 110 with a delay equal to the delay time generated by the analog-to-digital converter 121, the digital filter 122, the ΔΣ converter 261, and the digital-to-analog converter 230.

  The filter 262 is a moving average filter, for example, and removes a high frequency component of the analog discrete time signal from the subtracter 150. That is, in the filter circuit 200 according to the present embodiment, the noise shaping of the quantization noise is generated by the ΔΣ modulator 261, so that the quantization noise near the Nyquist frequency of the analog-digital converter 20 in the subsequent stage is increased. . Accordingly, the filter 262 prevents saturation of the input amplitude of the analog-to-digital converter 20 by removing the quantization noise component that is noise-shaped by the ΔΣ converter 261 and driven out to the high frequency range.

  As described above, in the filter circuit according to the present embodiment, a ΔΣ modulator is provided before the digital-analog converter, and quantization noise is noise-shaped. Therefore, according to the filter circuit according to the present embodiment, the signal-to-noise ratio within a desired band can be suppressed, so that the bit resolution of the digital-analog converter can be reduced. Further, the noise-shaped quantization noise is removed by the filter before being input to the subsequent analog-digital converter, so that the input amplitude of the subsequent analog-digital converter is not saturated.

(Third embodiment)
As shown in FIG. 6, the filter circuit 300 according to the third embodiment of the present invention is provided in the subsequent stage of the frequency converter 10, and includes a sampler 110, an analog-digital converter 121, a digital filter 122, and a digital-analog conversion. A delay unit 340, a delay unit 340, a subtractor 150, an analog-digital converter 371, a delay unit 372, and a subtractor 373. In the following description, the same parts in FIG. 6 as those in FIG. 1 are denoted by the same reference numerals, and different parts will be mainly described.

  The digital-analog converter 330 receives only the upper bits of the digital signal generated by the digital filter 122 and converts it to generate an analog discrete time signal. The remaining lower bits of the digital signal generated by the digital filter 122 are passed to the delay unit 372. Here, the bit resolution of the digital signal generated by the digital filter 122 is not particularly limited, but is determined based on the bit resolution of the digital-analog converter 330, for example. Further, the digital-analog converter 330 has higher accuracy than the bit resolution.

  The delay unit 340 provides the analog discrete-time signal from the sampler 110 with a delay equal to the delay time generated by the analog-to-digital converter 121, the digital filter 122, and the digital-to-analog converter 330.

  The analog discrete time signals from the digital-analog converter 330 and the delay unit 340 are subtracted by the subtractor 150 and input to the analog-digital converter 371. The analog-to-digital converter 371 has a bit resolution higher than that of the digital-to-analog converter 330, and converts the discrete-time analog signal from the subtractor 150 into the digital signal having the bit resolution. Since the bit resolution is smaller than the bit resolution of the digital filter 122, a large quantization noise is generated in the frequency band of the desired wave of the digital signal output from the analog-digital converter 371, and the signal-to-noise ratio is deteriorated.

  The delay unit 372 receives only the lower bits of the digital signal generated by the digital filter 122 as described above. The delay unit 372 gives the digital signal a signal delay equal to the delay time generated by the digital-analog converter 330, the subtractor 150, and the analog-digital converter 372.

  The subtracter 373 subtracts the digital signal from the delay unit 372 from the digital signal from the analog-digital converter 371. The digital signal from the delay unit 372 is a lower bit of the output digital signal of the digital filter 122, and has the same amplitude and phase as the quantization noise generated by the analog-to-digital converter 371. Therefore, by subtracting these, the quantization noise can be canceled and the signal-to-noise ratio of the desired wave can be improved.

  As described above, in the filter circuit according to the present embodiment, the output of the digital filter is branched into upper bits and lower bits, and the upper bits are subtracted in the analog domain as in the first embodiment, For lower bits, subtraction is performed in the digital domain to remove interference wave components. Therefore, according to the filter circuit of the present embodiment, it is possible to obtain the same interference wave component removal performance as that of the first embodiment while reducing the bit resolution of the digital-analog converter that receives the output of the digital filter. it can.

(Fourth embodiment)
As shown in FIG. 7, the filter circuit 400 according to the fourth embodiment of the present invention is inserted between the frequency converter 10 and the analog-to-digital converter 20, and includes a sampler 410, an analog-to-digital converter 421, A digital filter 122, a digital-analog converter 130, a delay unit 440 and a subtractor 150 are included. In the following description, the same parts in FIG. 7 as those in FIG. 1 are denoted by the same reference numerals, and different parts will be mainly described.

  The analog-to-digital converter 421 has a sampler, and when an analog continuous time signal is input, it can be converted into an analog discrete time signal internally. Therefore, in the filter circuit 400 according to the present embodiment, it is not necessary to provide a sampler before the analog-digital converter 421.

  The sampler 410 operates in the same manner as the sampler in the analog-digital converter 421, and converts the received baseband signal from the frequency converter 10 into an analog discrete time signal.

  The delay unit 440 applies a signal delay equal to the delay time generated by the analog-to-digital converter 421, the digital filter 122, and the output digital-to-analog converter 130 to the analog discrete-time signal from the sampler 410 and passes it to the subtracter 150. .

  As described above, the filter circuit according to this embodiment uses an analog-digital converter having a sampler. Therefore, according to the filter circuit according to the present embodiment, it is not necessary to share the sampler in the first and second paths.

(Fifth embodiment)
As shown in FIG. 8, the filter circuit 500 according to the fifth embodiment of the present invention is inserted between the frequency converter 10 and the analog-to-digital converter 20, and includes a sampler 510, a filter 581, a decimator 582, an analog A digital converter 121, a digital filter 122, a digital-analog converter 130, a delay 140 and a subtractor 150; In the following description, the same parts in FIG. 8 as those in FIG. 1 are denoted by the same reference numerals, and different parts will be mainly described.

  The sampler 510 has a higher sampling frequency than the sampler 110 described above, samples the received baseband signal from the frequency converter 10, and converts it to an analog discrete time signal.

  As described above, since the sampler 510 has a relatively high sampling frequency and performs sampling at a high speed, the analog discrete time signal from the sampler 510 is down-sampled by the decimator 582 before being input to the analog-to-digital converter 121. Is done.

  The filter 581 is, for example, a moving average filter, and removes frequency components that cause aliasing in the desired band after downsampling from the analog discrete time signal from the sampler 510 in order to suppress aliasing due to downsampling performed by the decimator 582.

  The decimator 582 down-samples the analog discrete time signal that has passed through the filter 581 and passes it to the analog-digital converter 121. The filter 581 and the decimator 582 may be configured in combination. For example, the filter 581 and the decimator 582 can be realized by the circuit shown in FIG. 9A.

The circuit shown in FIG. 9A has switches SW _580-in1 , SW _580-in2 , SW _580-out1 , SW _580-out2 , SW _580-re , capacitors C _580-1 and C _580-2 , and is input. An analog discrete time signal is downsampled at a decimation rate of ½. The circuit of FIG. 9A performs downsampling with four phases as one cycle as shown in FIG. 9B.

First, in phase 1, after the switch SW _580-in1 is turned on and the input signal charge is accumulated in the capacitor C _580-1 , the switch SW _580-in1 is turned off and the charge accumulated in the capacitor C580-1 is held. . In phase 2, the switch SW _580-in2 is turned on and the input signal charge is accumulated in the capacitor C _580-2 . Then, the switch SW _580-in2 is turned off and the charge accumulated in the capacitor C _580-2 is held. In phase 3, both the switches SW _580-out1 and SW _580-out2 are turned on, and the charges accumulated in the capacitors C _580-1 and C _580-2 are superimposed and output. In phase 4, after the switch SW _580-re is turned on and the accumulated charges of the capacitors C _580-1 and C _580-2 are reset to 0, the switches SW _580-out1 , SW _580-out2, and SW _580-re Three switches are turned off. The circuit in FIG. 9A repeats the above four phases and performs downsampling on the input analog discrete time signal.

  As described above, in the filter circuit according to the present embodiment, a filter and a decimator are provided after the sampler, and downsampling is performed on the analog discrete-time signal generated by the sampler. Therefore, according to the filter circuit according to the present embodiment, a sampler having a high sampling frequency can be used, and an interference wave higher than the Nyquist frequency of the analog-to-digital converter that receives the analog discrete time signal from the sampler is removed. be able to.

  In the filter circuit 500 shown in FIG. 5, only one set of the filter 581 and the decimator 582 is provided, but two or more sets of these may be provided. Further, the RF signal may be directly sampled by the sampler 510 without providing the frequency converter 10.

(Sixth embodiment)
As shown in FIG. 10, the receiver according to the sixth embodiment of the present invention includes an antenna 601, a low noise amplifier 602, a frequency converter 603, a filter 604, a filter circuit 605, and an analog-digital converter 606.

  The received signal received by the antenna 601 is amplified by the low noise amplifier 602 and down-converted by the frequency converter 603. The filter 604 is a low-pass filter and removes high-frequency interference wave components included in the received baseband signal generated by the frequency converter 603.

  The filter circuit 605 is a filter circuit according to any of the first to fifth embodiments described above, and further removes interference wave components from the received baseband signal from which high-frequency interference wave components have been removed by the filter 604. The output signal of the filter circuit 605 is converted into a digital signal by the analog-digital converter 606 and demodulated by a digital signal processing unit (not shown).

  As described above, in this embodiment, the filter circuit according to any one of the first to fifth embodiments is provided between the low-pass filter and the analog-digital converter. Therefore, according to the receiver according to the present embodiment, it is possible to improve the removal accuracy of the interference wave component and to configure the analog-digital converter with less bit resolution to reduce the power consumption.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. Further, for example, a configuration in which some components are deleted from all the components shown in each embodiment is also conceivable. Furthermore, you may combine suitably the component described in different embodiment.

The block diagram which shows the filter circuit which concerns on 1st Embodiment, and its periphery. The circuit diagram which shows an example of the sampler of FIG. The circuit diagram which shows an example of the digital-analog converter of FIG. The graph which shows operation | movement of the switch of FIG. 3A. FIG. 2 is a circuit diagram illustrating an example of a delay device in FIG. 1. FIG. 4B is a graph showing the operation of the switch of FIG. 4A. The block diagram which shows the filter circuit which concerns on 2nd Embodiment, and its periphery. The block diagram which shows the filter circuit which concerns on 3rd Embodiment, and its periphery. The block diagram which shows the filter circuit which concerns on 4th Embodiment, and its periphery. The block diagram which shows the filter circuit which concerns on 5th Embodiment, and its periphery. FIG. 9 is a circuit diagram showing an example of the filter and decimator of FIG. 8. The graph which shows operation | movement of the switch of FIG. 9A. The block diagram which shows the receiver which concerns on 6th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Frequency converter 20 ... Analog-digital converter 100 ... Filter circuit 110 ... Sampler 121 ... Analog-digital converter 122 ... Digital filter 130 ... Digital-analog Converter 140 ... Delayer 150 ... Subtractor 200 ... Filter circuit 230 ... Digital-to-analog converter 240 ... Delayer 261 ... ΔΣ modulator 262 ... Filter 300 ... Filter circuit 330: digital-analog converter 340: delay circuit 371: analog-digital converter 372: delay circuit 373: subtractor 400: filter circuit 410: sampler 421... Analog-to-digital converter 440. Delay device 500... Filter circuit 510. 81 ... filter 582 · decimator 601 ... antenna 602 ... low-noise amplifier 603 ... frequency converter 604 ... filter 605 ... filter circuit 606 ... analog - digital converter

Claims (10)

A sampler that samples the input signal to generate a first analog signal;
An analog-to-digital converter that converts the first analog signal into a first digital signal;
A digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal;
A digital-to-analog converter for converting the second digital signal into a second analog signal;
A delay unit that applies a signal delay equal to a delay time of the second analog signal to the first analog signal to the first analog signal and outputs a third analog signal;
A filter circuit comprising: a subtractor that subtracts the second analog signal from the third analog signal to generate an output signal.   2. The filter circuit according to claim 1, wherein the analog-to-digital converter has a resolution of at least 1 bit per 6 decibels of attenuation of the output signal with respect to the input signal outside the desired band.   The digital filter and the digital-to-analog converter are 6 decibels of a ratio of the input signal in the desired band to the input signal outside the desired band and a signal-to-noise ratio of the output signal in the desired band. 2. A filter circuit according to claim 1, wherein each filter has a resolution of at least 1 bit.   2. The filter circuit according to claim 1, wherein the delay circuit temporarily accumulates the first analog signal and outputs the first analog signal as the third analog signal when the delay time elapses. A sampler that samples the input signal to generate a first analog signal;
An analog-to-digital converter that converts the first analog signal into a first digital signal;
A digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal;
A ΔΣ modulator that performs ΔΣ modulation on the second digital signal and outputs a third digital signal;
A digital-to-analog converter for converting the third digital signal into a second analog signal;
A delay unit that applies a signal delay equal to a delay time of the second analog signal to the first analog signal to the first analog signal and outputs a third analog signal;
A subtractor for subtracting the second analog signal from the third analog signal to generate a fourth analog signal;
And a filter that removes quantization noise generated by the analog-to-digital converter from the fourth analog signal to generate an output signal. A sampler that samples the input signal to generate a first analog signal;
A first analog-to-digital converter that converts the first analog signal to a first digital signal;
A digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal;
A digital-to-analog converter that converts a third digital signal composed of upper bits of the second digital signal into a second analog signal;
A first delay for providing the first analog signal with a signal delay equal to a delay time of the second analog signal with respect to the first analog signal, and outputting a third analog signal;
A first subtractor for subtracting the second analog signal from the third analog signal to generate a fourth analog signal;
A second analog-to-digital converter that converts the fourth analog signal to a fourth digital signal;
A signal delay equal to the delay time of the fourth digital signal with respect to the second digital signal is given to the fifth digital signal composed of the lower bits of the second digital signal, and the sixth digital signal is output. A second delay device;
A filter circuit comprising: a subtractor that subtracts the sixth digital signal from the fourth digital signal to generate an output signal. A first sampler that samples an input signal to generate a first analog signal;
An analog-to-digital converter that has a second sampler and converts a second analog signal generated by sampling the input signal with the second sampler to a first digital signal;
A digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal;
A digital-to-analog converter for converting the second digital signal into a third analog signal;
A delay unit that applies a signal delay equal to a delay time of the third analog signal with respect to the second analog signal to the first analog signal and outputs a fourth analog signal;
And a subtractor for subtracting the second analog signal from the fourth analog signal to generate an output signal. A sampler that samples the input signal to generate a first analog signal;
A filter for extracting a low frequency component from the first analog signal and outputting a second analog signal;
A decimator for down-sampling the second analog signal and outputting a third analog signal;
An analog-to-digital converter that converts the third analog signal into a first digital signal;
A digital filter that extracts a signal component outside a desired band from the first digital signal to generate a second digital signal;
A digital-analog converter for converting the second digital signal into a fourth analog signal;
A delay unit for providing the third analog signal with a signal delay equal to a delay time of the fourth analog signal with respect to the third analog signal, and outputting a fifth analog signal;
And a subtractor for subtracting the fourth analog signal from the fifth analog signal to generate an output signal. An antenna for receiving a radio signal and obtaining a received signal;
A low noise amplifier that amplifies the received signal and outputs the amplified signal;
A frequency converter that downconverts the amplified signal to generate a baseband signal;
The filter circuit according to claim 1, wherein the baseband signal is received as the input signal, and a filtering signal is obtained as the output signal;
An analog-to-digital converter that converts the filtering signal into a digital signal; and a demodulator that demodulates the digital signal;
A receiver comprising: Sampling the input signal to generate a first analog signal;
Converting the first analog signal to a first digital signal;
Extracting a signal component outside the desired band from the first digital signal to generate a second digital signal;
Converting the second digital signal into a second analog signal;
Providing the first analog signal with a signal delay equal to the delay time of the second analog signal relative to the first analog signal, and outputting a third analog signal;
A filtering method comprising: subtracting the second analog signal from the third analog signal to generate an output signal.

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