CN106098629B - TFT substrate and manufacturing method thereof - Google Patents
TFT substrate and manufacturing method thereof Download PDFInfo
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- CN106098629B CN106098629B CN201610584502.2A CN201610584502A CN106098629B CN 106098629 B CN106098629 B CN 106098629B CN 201610584502 A CN201610584502 A CN 201610584502A CN 106098629 B CN106098629 B CN 106098629B
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- 239000000758 substrate Substances 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 502
- 239000011229 interlayer Substances 0.000 claims abstract description 99
- 238000000137 annealing Methods 0.000 claims abstract description 35
- 150000002500 ions Chemical class 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 238000005984 hydrogenation reaction Methods 0.000 claims description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 239000002131 composite material Substances 0.000 claims description 11
- 230000004913 activation Effects 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims 4
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000012545 processing Methods 0.000 description 15
- 239000012528 membrane Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000010408 film Substances 0.000 description 8
- 238000010348 incorporation Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- -1 boron ion Chemical class 0.000 description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 6
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000002791 soaking Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- Thin Film Transistor (AREA)
Abstract
本发明提供一种TFT基板及其制作方法。本发明的TFT基板的制作方法，通过在层间介电层上形成数个凹槽之后再进行退火处理，可通过数个凹槽释放层间介电层因热膨胀产生的应力，防止层间介电层从基板上脱落，提高TFT基板的电学性能和可靠性。本发明的TFT基板，通过在层间介电层上形成数个凹槽，可防止在TFT基板的制程中层间介电层从基板上脱落，提高TFT基板的电学性能和可靠性。
The present invention provides a TFT substrate and a manufacturing method thereof. In the manufacturing method of the TFT substrate of the present invention, by forming several grooves on the interlayer dielectric layer and then performing annealing treatment, the stress generated by the thermal expansion of the interlayer dielectric layer can be released through the plurality of grooves, and the interlayer dielectric layer can be prevented from being formed. The electrical layer is peeled off from the substrate, improving the electrical performance and reliability of the TFT substrate. In the TFT substrate of the present invention, by forming several grooves on the interlayer dielectric layer, the interlayer dielectric layer can be prevented from falling off the substrate during the manufacturing process of the TFT substrate, and the electrical performance and reliability of the TFT substrate can be improved.
Description
Technical field
The present invention relates to thin-film transistor technologies fields more particularly to a kind of TFT substrate and preparation method thereof.
Background technique
Liquid crystal display device (Liquid Crystal Display, LCD) has thin fuselage, power saving, radiationless etc. numerous
Advantage is widely used, such as: mobile phone, personal digital assistant (PDA), digital camera, computer screen or notes
This computer screen etc..
OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display, also referred to as Organic Electricity
Electroluminescent display is a kind of emerging panel display apparatus, since it is simple with preparation process, at low cost, low in energy consumption, hair
Brightness height, operating temperature wide adaptation range, volume be frivolous, fast response time, and is easily achieved colored display and large screen
It shows, be easily achieved and match with driver ic, be easily achieved the advantages that Flexible Displays, thus there is wide application
Prospect.
OLED according to driving method can be divided into passive matrix OLED (Passive Matrix OLED, PMOLED) and
Active array type OLED (Active Matrix OLED, AMOLED) two major classes, i.e. directly addressing and film transistor matrix are sought
Two class of location.Wherein, AMOLED has the pixel in array arrangement, belongs to active display type, and luminous efficacy is high, is typically used as
Large scale display device high-definition.
Thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) is current liquid crystal display device and active matrix
Main driving element in drive-type organic electroluminescence display device and method of manufacturing same, is directly related to the development of high performance flat display device
Direction.Thin film transistor (TFT) has various structures, and the material for preparing the thin film transistor (TFT) of corresponding construction also has a variety of, low-temperature polysilicon
Silicon (Low Temperature Poly-silicon, abbreviation LTPS) material be it is wherein more preferred a kind of, since low temperature is more
The atomic rule of crystal silicon arranges, and carrier mobility is high, and for the liquid crystal display device of voltage driven type, low temperature polycrystalline silicon is thin
Film transistor due to its mobility with higher, realize to the inclined of liquid crystal molecule by the thin film transistor (TFT) that small volume can be used
Turn driving, largely reduce volume shared by thin film transistor (TFT), increase glazed area, obtains higher brightness reconciliation
Analysis degree；For the active matrix drive type organic electroluminescence display device and method of manufacturing same of current-driven, low-temperature polysilicon film is brilliant
Body pipe can better meet driving current requirement.
The preparation process of low-temperature polysilicon film transistor is usually the deposition of amorphous silicon layers on substrate, then passes through heat treatment
Etc. modes make amorphous silicon fusion-crystallization to form the polysilicon layer with grain structure, next using polysilicon layer as film
The channel layer of transistor, as gate insulation layer, then metal carries out the nitrogen oxides of silicon as grid by exposure mask of metal gates
Self aligned ion implanting forms source-drain electrode contact zone, is finally completed the production of polycrystalline SiTFT.In polysilicon membrane
The lattice damage that will cause polysilicon in the preparation process of transistor, after ion implanting needs subsequent activation technology to injection
Ion activated and repair the lattice damage of polysilicon layer.In addition, the interface of polysilicon membrane and gate insulation layer exists not
The dangling bonds of bonding orbital are the increased critically important factors of interface state density of polysilicon grain boundary, move so as to cause carrier
The decline of shifting rate, the performance degradation problem of the display devices such as threshold voltage raising, subsequent technique will be also passivated more by hydrogenation process
The defect of polycrystal silicon film inside and interface.
Existing ion-activated technique and hydrogenation process are as follows: quick thermal annealing process is carried out after forming interlayer dielectric layer,
Since the thickness of interlayer dielectric layer is larger, it is easy to appear in annealing process and causes to shell since stress caused by thermally expanding is excessive
The phenomenon that falling.
Summary of the invention
The purpose of the present invention is to provide a kind of production methods of TFT substrate, can prevent interlayer dielectric layer in annealing process
It falls off from substrate, improves the electric property and reliability of TFT substrate.
The object of the invention is also to provide a kind of TFT substrates, have good electric property and reliability.
To achieve the above object, present invention firstly provides a kind of production method of TFT substrate, include the following steps:
Step 1 provides a substrate, forms buffer layer on the substrate, forms active layer on the buffer layer；
Step 2 forms gate insulating layer on the active layer and buffer layer；
The grid for corresponding to active layer is formed on the gate insulating layer；
Ion implanting is carried out to the active layer, forms ion heavily doped region；
Step 3 forms interlayer dielectric layer on the grid and gate insulating layer, is formed on the interlayer dielectric layer
Several grooves；Entire substrate is made annealing treatment, to carry out ion-activated and hydrogenation treatment to active layer；
Step 4 forms the ion heavy doping for corresponding to the active layer on the interlayer dielectric layer and gate insulating layer
Source contact openings and drain contact hole above area；
Step 5 forms source electrode and drain electrode on the interlayer dielectric layer, and the source electrode, drain electrode pass through source contact respectively
Hole, drain contact hole are in contact with the ion heavily doped region of the active layer.
In the step 3, described ion-activated and hydrogenation treatment is completed in the same annealing process, the temperature of annealing process
Degree is 490 DEG C~690 DEG C, and soaking time is 20s~60min；
Alternatively, described ion-activated and hydrogenation treatment is completed in two annealing process respectively, described in the step 3
Ion-activated annealing process is first, and the hydrotreated annealing process is in rear, the temperature of the ion-activated annealing process
Degree is 490 DEG C~690 DEG C, and soaking time is 20s~20min；The temperature of the hydrotreated annealing process be 300 DEG C~
500 DEG C, soaking time is 20min~120min.
On source contact openings, drain contact hole and the interlayer dielectric layer on the interlayer dielectric layer and gate insulating layer
Several groove intervals setting.
The interlayer dielectric layer is that silicon oxide layer, silicon nitride layer or be superimposed by silicon oxide layer with silicon nitride layer are constituted
Composite layer；The interlayer dielectric layer with a thickness of
The depth of the groove is less than the thickness of the interlayer dielectric layer, and the size of several grooves is identical or different.
The step 1 specifically includes:
Step 11 provides a substrate, forms buffer layer on the substrate；
Step 12 forms amorphous silicon membrane on the buffer layer, carries out Crystallizing treatment to the amorphous silicon membrane, makes it
It is converted into polysilicon membrane, processing is patterned to the polysilicon membrane, forms spaced first active layer and the
Two active layers；
Step 13 carries out channel doping to first active layer, and the system of channel doping is carried out to first active layer
A kind of journey realization by the following two kinds of programs:
Scheme 1 forms the first photoresist layer on first active layer, the second active layer and buffer layer, to described first
After photoresist layer is patterned processing, the first photoresist layer of reservation covers entire second active layer；
Using first photoresist layer as barrier bed, p-type doping is carried out to entire first active layer；
Scheme 2 is not provided with the first photoresist layer, directly carries out p-type doping to first active layer, the second active layer；
The step 2 specifically includes:
Step 21 forms the second photoresist layer on first active layer, the second active layer and buffer layer, to described
After two photoresist layers are patterned processing, the intermediate region that the second photoresist layer of reservation covers the first active layer has with entire second
Active layer；
Using second photoresist layer as barrier bed, N-type heavy doping is carried out to the two sides of first active layer, described the
The N-type heavily doped region for being located at two sides is formed on one active layer；
Step 22, removal second photoresist layer, form on first active layer, the second active layer and buffer layer
Gate insulating layer；
Step 23 forms the first grid corresponding to first active layer on the gate insulating layer and corresponds to
The second grid of second active layer；
On the direction for being parallel to substrate, the first grid be located at first active layer two N-type heavily doped regions it
Between, and be spaced a distance respectively with two N-type heavily doped regions of first active layer；
On the direction for being parallel to substrate, the both sides of the edge of second active layer are more than the two of the second grid respectively
Side edge a distance；
Step 24, using the first grid, second grid as barrier bed, to first active layer and the second active layer into
Row N-type is lightly doped, and two N-type lightly doped districts being located on the inside of two N-type heavily doped regions are formed on first active layer；?
The N-type lightly doped district for being located at two sides is formed on second active layer；
Step 25 forms third photoresist layer on the first grid, second grid and gate insulating layer, to described the
After three photoresist layers are patterned processing, the third photoresist layer of reservation blocks entire first active layer and covers entire second gate
Pole；
Using the third photoresist layer as barrier bed, p-type heavy doping is carried out to the two sides of second active layer, makes described the
The N-type lightly doped district of two active layer two sides is converted into p-type heavily doped region；
The step 3 specifically includes:
Interlayer dielectric layer is formed on the first grid, second grid and gate insulating layer, in the interlayer dielectric layer
It is upper to form several grooves；Entire substrate is made annealing treatment, it is ion-activated to be carried out to the first active layer with the second active layer
And hydrogenation treatment；
The step 4 specifically includes:
On the interlayer dielectric layer and gate insulating layer formed correspond respectively to first active layer two N-types it is heavily doped
The first source contact openings and the first drain contact hole above miscellaneous area and two p-types for corresponding respectively to second active layer
The second source contact openings and the second drain contact hole above heavily doped region；
The step 5 specifically includes:
The first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed on the interlayer dielectric layer；
First source electrode, the first drain electrode pass through the first source contact openings, the first drain contact hole and described first respectively
Two N-type heavily doped regions of active layer are in contact；
Second source electrode, the second drain electrode pass through the second source contact openings, the second drain contact hole and described second respectively
Two p-type heavily doped regions of active layer are in contact.
The present invention also provides a kind of TFT substrates, including substrate, the buffer layer on the substrate, are set to the buffering
Active layer on layer, the gate insulating layer on the active layer and buffer layer are set on the gate insulating layer and correspond to
In the grid of the active layer, the interlayer dielectric layer on the grid and gate insulating layer and it is set to the interlayer dielectric
Source electrode and drain electrode on layer；
The interlayer dielectric layer is equipped with several grooves；
The active layer is equipped with ion heavily doped region；
The interlayer dielectric layer and gate insulating layer are equipped with above the ion heavily doped region corresponding to the active layer
Source contact openings and drain contact hole；The source electrode, drain electrode pass through source contact openings, drain contact hole and the active layer respectively
Ion heavily doped region be in contact.
On source contact openings, drain contact hole and the interlayer dielectric layer on the interlayer dielectric layer and gate insulating layer
Several groove intervals setting.
The interlayer dielectric layer is that silicon oxide layer, silicon nitride layer or be superimposed by silicon oxide layer with silicon nitride layer are constituted
Composite layer；The interlayer dielectric layer with a thickness of
The depth of the groove is less than the thickness of the interlayer dielectric layer, and the size of several grooves is identical or different.
One specific embodiment of the TFT substrate includes substrate, the buffer layer on the substrate, is set to the buffering
On layer and spaced first active layer and the second active layer, it is set to first active layer, the second active layer and buffer layer
On gate insulating layer, on the gate insulating layer and correspond to the first grid of first active layer, be set to it is described
On gate insulating layer and corresponds to the second grid of second active layer, is set to the first grid, second grid and grid
Interlayer dielectric layer on insulating layer and the first source electrode on the interlayer dielectric layer, the first drain electrode, the second source electrode and
Second drain electrode；
The interlayer dielectric layer is equipped with several grooves；
First active layer includes the two N-type heavily doped regions positioned at both ends, and second active layer includes being located at both ends
Two p-type heavily doped regions；
The interlayer dielectric layer and gate insulating layer are equipped with the two N-type heavy doping for corresponding respectively to first active layer
The first source contact openings and the first drain contact hole above area and the two p-type weights for corresponding respectively to second active layer
The second source contact openings and the second drain contact hole above doped region；
First source electrode, the first drain electrode pass through the first source contact openings, the first drain contact hole and described first respectively
Two N-type heavily doped regions of active layer are in contact；Second source electrode, the second drain electrode pass through the second source contact openings, second respectively
Drain contact hole is in contact with two p-type heavily doped regions of second active layer.
The specific embodiment of the TFT substrate further includes being set between the substrate and the buffer layer and corresponding to described
Light shield layer below first active layer.
Beneficial effects of the present invention: a kind of production method of TFT substrate provided by the invention, by interlayer dielectric layer
It forms several grooves to be made annealing treatment again later, several grooves can be passed through and discharge interlayer dielectric layer because what thermal expansion generated answering
Power prevents interlayer dielectric layer from falling off from substrate, improves the electric property and reliability of TFT substrate.One kind provided by the invention
TFT substrate can prevent in the processing procedure of TFT substrate interlayer dielectric layer from base by forming several grooves on interlayer dielectric layer
It falls off on plate, improves the electric property and reliability of TFT substrate.
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Detailed description of the invention
With reference to the accompanying drawing, by the way that detailed description of specific embodiments of the present invention, technical solution of the present invention will be made
And other beneficial effects are apparent.
In attached drawing,
Fig. 1 is the flow chart of the production method of TFT substrate of the invention；
Fig. 2-3 is the schematic diagram of the specific embodiment of the step 1 of the production method of TFT substrate of the invention；
Fig. 4-6 is the schematic diagram of the specific embodiment of the step 2 of the production method of TFT substrate of the invention；
Fig. 7-8 is the schematic diagram of the specific embodiment of the step 3 of the production method of TFT substrate of the invention；
Fig. 9 is the schematic diagram of the specific embodiment of the step 4 of the production method of TFT substrate of the invention；
Figure 10 is the schematic diagram of specific embodiment of the step 5 of the production method of TFT substrate of the invention and of the invention
The structural schematic diagram of one specific embodiment of TFT substrate.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
Referring to Fig. 1, including the following steps: present invention firstly provides a kind of production method of TFT substrate
Step 1 provides a substrate, forms buffer layer on the substrate, forms active layer on the buffer layer.
The step 1 specifically includes:
Step 11, referring to Fig. 2, provide a substrate 10, on the substrate 10 formed buffer layer 30.
Specifically, the substrate 10 is glass substrate.
Preferably, the step 11 further include: formed before buffer layer 30 on the substrate 10, on the substrate 10
Form the light shield layer 20 for corresponding to 40 lower section of the first active layer that subsequent step is formed.
Specifically, the size of the light shield layer 20 is greater than or equal to the size of first active layer 40, the light shield layer
20 material is metal molybdenum (Mo) or amorphous silicon.
Specifically, the buffer layer 30 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer and nitrogen
The composite layer that the superposition of SiClx layer is constituted.
Step 12, referring to Fig. 3, form amorphous silicon membrane on the buffer layer 30, the amorphous silicon membrane is carried out
Crystallizing treatment makes it be converted into polysilicon membrane, is patterned processing to the polysilicon membrane, forms spaced the
One active layer 40 and the second active layer 50.
Specifically, being carried out using quasi-molecule laser annealing (ELA) technique to the amorphous silicon membrane brilliant in the step 12
Change processing.
Step 13 carries out channel doping to first active layer 40, carries out channel doping to first active layer 40
A kind of processing procedure realization by the following two kinds of programs:
Scheme 1, referring to Fig. 3, forming first on first active layer 40, the second active layer 50 and buffer layer 30
Photoresist layer 91, after being patterned processing to first photoresist layer 91, the first photoresist layer 91 of reservation, which covers entire second, to be had
Active layer 50；
It is barrier bed with first photoresist layer 91, p-type doping is carried out to entire first active layer 40；
Scheme 2 is not provided with the first photoresist layer 91, directly carries out p-type to first active layer 40, the second active layer 50 and mixes
It is miscellaneous.
Specifically, the ion of the p-type doping incorporation is boron ion, the ion concentration of the p-type doping incorporation is 5e11~
3e12ion/cm2。
Step 2 forms gate insulating layer on the active layer and buffer layer；
The grid for corresponding to active layer is formed on the gate insulating layer；
Ion implanting is carried out to the active layer, forms ion heavily doped region.
The step 2 specifically includes:
Step 21, referring to Fig. 4, forming second on first active layer 40, the second active layer 50 and buffer layer 30
Photoresist layer 92, after being patterned processing to second photoresist layer 92, the second photoresist layer 92 of reservation covers the first active layer
40 intermediate region and entire second active layer 50；
It is barrier bed with second photoresist layer 92, N-type heavy doping (N+) is carried out to the two sides of first active layer 40,
The N-type heavily doped region 41 for being located at two sides is formed on first active layer 40.
Specifically, the ion concentration of the N-type heavy doping incorporation is 8e14~5e15ion/cm2。
Specifically, the ion of the N-type heavy doping incorporation is phosphonium ion.
Step 22, referring to Fig. 5, removal second photoresist layer 92, in first active layer 40, the second active layer
50 and buffer layer 30 on formed gate insulating layer 60.
Specifically, the gate insulating layer 60 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Step 23 corresponds to the first of first active layer 40 referring to Fig. 5, being formed on the gate insulating layer 60
Grid 61 and second grid 62 corresponding to second active layer 50；
On the direction for being parallel to substrate 10, two N-types that the first grid 61 is located at first active layer 40 are heavily doped
Between miscellaneous area 41, and it is spaced a distance respectively with two N-type heavily doped regions 41 of first active layer 40；
On the direction for being parallel to substrate 10, the both sides of the edge of second active layer 50 are more than the second grid respectively
62 both sides of the edge a distance.
Specifically, the material of the first grid 61 and second grid 62 includes molybdenum (Mo), aluminium (Al), copper (Cu) and titanium
Or a variety of combinations one of (Ti).
Step 24, referring to Fig. 5, being barrier bed with the first grid 61, second grid 62, to first active layer
40 and second active layer 50 carry out N-type (N-) is lightly doped, on first active layer 40 formed be located at two N-type heavy doping
Two N-type lightly doped districts 42 of 41 inside of area；The N-type lightly doped district 51 for being located at two sides is formed on second active layer 50.
Specifically, the region on first active layer 40 between two N-type lightly doped districts 42 forms channel region 43.
Specifically, the ion that incorporation is lightly doped in the N-type is phosphonium ion, the ion concentration that incorporation is lightly doped in the N-type is
1e13~5e14ion/cm2。
Step 25, referring to Fig. 6, forming third on the first grid 61, second grid 62 and gate insulating layer 60
Photoresist layer 93, after being patterned processing to the third photoresist layer 93, the third photoresist layer 93 of reservation, which blocks entire first, to be had
Active layer 40 simultaneously covers entire second grid 62；
It is barrier bed with the third photoresist layer 93, p-type heavy doping (P+) is carried out to the two sides of second active layer 50,
The N-type lightly doped district 51 of 50 two sides of the second active layer is set to be converted into p-type heavily doped region 52.
Specifically, the region on second active layer 50 between two p-type heavily doped regions 52 forms channel region 53.
Specifically, the ion of the p-type heavy doping incorporation is boron ion, the ion concentration of the p-type heavy doping incorporation is
8e14~5e15ion/cm2。
Step 3 forms interlayer dielectric layer on the grid and gate insulating layer, is formed on the interlayer dielectric layer
Several grooves；Entire substrate is made annealing treatment, to carry out ion-activated and hydrogenation treatment to active layer.
Specifically, the interlayer dielectric layer is silicon oxide layer, silicon nitride layer or is superimposed by silicon oxide layer with silicon nitride layer
The composite layer of composition；The interlayer dielectric layer with a thickness of
Specifically, the depth of the groove is less than the thickness of the interlayer dielectric layer, the size of several grooves is identical
Or it is different.
Specifically, described ion-activated and hydrogenation treatment is completed in the same annealing process in the step 3, or
It is completed in two annealing process respectively.
When described ion-activated and hydrogenation treatment is completed in the same annealing process, the temperature of annealing process is 490
DEG C~690 DEG C, preferably 590 DEG C, soaking time is 20s~60min, preferably 30min.
When described ion-activated and hydrogenation treatment is completed in two annealing process respectively, the ion-activated annealing
Processing procedure is first, and for the hydrotreated annealing process rear, the temperature of the ion-activated annealing process is 490 DEG C~690
DEG C, preferably 590 DEG C, soaking time is 20s~20min, preferably 10min；The temperature of the hydrotreated annealing process
For 300 DEG C~500 DEG C, preferably 500 DEG C, soaking time is 20min~120min, preferably 60min.
The step 3 specifically includes: Fig. 7-8 is please referred to, in the first grid 61, second grid 62 and gate insulator
Interlayer dielectric layer 70 is formed on layer 60, and several grooves 71 are formed on the interlayer dielectric layer 70；It anneals to entire substrate
Processing, to carry out ion-activated and hydrogenation treatment to the first active layer 40 and the second active layer 50.
Specifically, the interlayer dielectric layer 70 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Specifically, the interlayer dielectric layer 70 with a thickness ofPreferably
Specifically, the depth of the groove 71 is less than the thickness of the interlayer dielectric layer 70, the ruler of several grooves 71
It is very little identical or different.
By forming several grooves on interlayer dielectric layer, in annealing, it is situated between several groove releasable layers
The stress that electric layer is generated by thermal expansion, prevents interlayer dielectric layer from falling off from substrate.
In the step 3, carrying out ion-activated purpose to active layer is: activating to the ion injected in active layer
And repair the lattice damage of polysilicon film；Carrying out hydrotreated purpose to active layer is: by the hydrogen atom in interlayer dielectric layer
Polysilicon layer is diffused to, hydrogen atom is made to fill up the defect of polysilicon film, reduces the defect concentration of polysilicon film to improve component spy
Property.
Step 4 forms the ion heavy doping for corresponding to the active layer on the interlayer dielectric layer and gate insulating layer
Source contact openings and drain contact hole above area.
Specifically, source contact openings, drain contact hole and the interlayer on the interlayer dielectric layer and gate insulating layer
Several groove intervals setting on dielectric layer.
The step 4 specifically includes: dividing referring to Fig. 9, being formed on the interlayer dielectric layer 70 and gate insulating layer 60
Not Dui Yingyu first active layer 40 the top of two N-type heavily doped region 41 the first source contact openings 73 and the first drain contact
Hole 74 and correspond respectively to second active layer 50 the top of two p-type heavily doped region 52 the second source contact openings 75 with
Second drain contact hole 76.
Specifically, the first source contact openings 73, first drain electrode on the interlayer dielectric layer 70 and gate insulating layer 60 connects
Between several grooves 71 on contact hole 74, the second source contact openings 75 and the second drain contact hole 76 and the interlayer dielectric layer 70
Every setting.
Step 5 forms source electrode and drain electrode on the interlayer dielectric layer, and the source electrode, drain electrode pass through source contact respectively
Hole, drain contact hole are in contact with the ion heavily doped region of the active layer.
The step 5 specifically includes: referring to Fig. 10, forming the first source electrode 81, first on the interlayer dielectric layer 70
The 82, second source electrode of drain electrode 83 and the second drain electrode 84；
First source electrode 81, first drain electrode 82 respectively by the first source contact openings 73, the first drain contact hole 74 with
Two N-type heavily doped regions 41 of first active layer 40 are in contact；
Second source electrode 83, second drain electrode 84 respectively by the second source contact openings 75, the second drain contact hole 76 with
Two p-type heavily doped regions 52 of second active layer 50 are in contact.
Specifically, first source electrode 81, first drains, the 82, second source electrode 83 and the material of the second drain electrode 84 include molybdenum
(Mo), one of aluminium (Al), copper (Cu), titanium (Ti) or a variety of combinations.
The production method of above-mentioned TFT substrate is carried out at annealing after several grooves again by being formed on interlayer dielectric layer
Reason can discharge the stress that interlayer dielectric layer is generated by thermal expansion by several grooves, prevent interlayer dielectric layer from falling off from substrate,
Improve the electric property and reliability of TFT substrate.
Based on the production method of above-mentioned TFT substrate, the present invention also provides a kind of TFT substrate, including substrate, it is set to the base
Buffer layer on plate, the active layer on the buffer layer, the gate insulating layer on the active layer and buffer layer,
Grid, the layer on the grid and gate insulating layer on the gate insulating layer and corresponding to the active layer
Between dielectric layer and source electrode and drain electrode on the interlayer dielectric layer；
The interlayer dielectric layer is equipped with several grooves；
The active layer is equipped with ion heavily doped region；
The interlayer dielectric layer and gate insulating layer are equipped with above the ion heavily doped region corresponding to the active layer
Source contact openings and drain contact hole；The source electrode, drain electrode pass through source contact openings, drain contact hole and the active layer respectively
Ion heavily doped region be in contact.
Specifically, the interlayer dielectric layer is silicon oxide layer, silicon nitride layer or is superimposed by silicon oxide layer with silicon nitride layer
The composite layer of composition；The interlayer dielectric layer with a thickness of
Specifically, the depth of the groove is less than the thickness of the interlayer dielectric layer, the size of several grooves is identical
Or it is different.
Specifically, source contact openings, drain contact hole and the interlayer on the interlayer dielectric layer and gate insulating layer
Several groove intervals setting on dielectric layer.
Specifically, the material of the active layer is polysilicon.
Specifically, referring to Fig. 10, be a preferred embodiment of TFT substrate of the invention, including substrate 10, be set to it is described
Buffer layer 30 on substrate 10, be set on the buffer layer 30 and spaced first active layer 40 and the second active layer 50,
Gate insulating layer 60 on first active layer 40, the second active layer 50 and buffer layer 30 is set to the gate insulator
On layer 60 and corresponds to the first grid 61 of first active layer 40, is set on the gate insulating layer 60 and correspond to described
The second grid 62 of second active layer 50, the interlayer on the first grid 61, second grid 62 and gate insulating layer 60
Dielectric layer 70 and the first source electrode 81, first the 82, second source electrode 83 and second of drain electrode on the interlayer dielectric layer 70
Drain electrode 84；
The interlayer dielectric layer 70 is equipped with several grooves 71；
First active layer 40 includes the two N-type heavily doped regions 41 positioned at both ends, and second active layer 50 includes position
The two p-type heavily doped regions 52 in both ends；
The interlayer dielectric layer 70 and gate insulating layer 60 are equipped with two N-types for corresponding respectively to first active layer 40
First source contact openings 73 of the top of heavily doped region 41 and the first drain contact hole 74 and to correspond respectively to described second active
The second source contact openings 75 and the second drain contact hole 76 of two p-type heavily doped regions, 52 top of layer 50；
First source electrode 81, first drain electrode 82 respectively by the first source contact openings 73, the first drain contact hole 74 with
Two N-type heavily doped regions 41 of first active layer 40 are in contact；The drain electrode of second source electrode 83, second 84 passes through second respectively
Source contact openings 75, the second drain contact hole 76 are in contact with two p-type heavily doped regions 52 of second active layer 50.
Specifically, first active layer 40 further includes the two N-type lightly doped districts positioned at two N-type heavily doped regions, 41 inside
42 and the channel region 43 between two N-type lightly doped districts 42, second active layer 50 further includes being located at p-type heavy doping
Channel region 53 between area 52.
Specifically, the substrate 10 is glass substrate.
Preferably, the TFT substrate further includes being set between the substrate 10 and the buffer layer 30 and corresponding to described
The light shield layer 20 of first active layer, 40 lower section.
Specifically, the size of the light shield layer 20 is greater than or equal to the size of first active layer 40, the light shield layer
20 material is metal molybdenum (Mo) or amorphous silicon.
Specifically, the buffer layer 30 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer and nitrogen
The composite layer that the superposition of SiClx layer is constituted.
Specifically, the material of first active layer 40 and the second active layer 50 is polysilicon.
Specifically, the gate insulating layer 60 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Specifically, the material of the first grid 61 and second grid 62 includes molybdenum (Mo), aluminium (Al), copper (Cu) and titanium
Or a variety of combinations one of (Ti).
Specifically, the interlayer dielectric layer 70 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Specifically, the interlayer dielectric layer 70 with a thickness ofPreferably
Specifically, the depth of the groove 71 is less than the thickness of the interlayer dielectric layer 70, the ruler of several grooves 71
It is very little identical or different.
Specifically, the first source contact openings 73, first drain electrode on the interlayer dielectric layer 70 and gate insulating layer 60 connects
Between several grooves 71 on contact hole 74, the second source contact openings 75 and the second drain contact hole 76 and the interlayer dielectric layer 70
Every setting.
Specifically, first source electrode 81, first drains, the 82, second source electrode 83 and the material of the second drain electrode 84 include molybdenum
(Mo), one of aluminium (Al), copper (Cu) and titanium (Ti) or a variety of combinations.
Specifically, the ion mixed in the N-type heavily doped region 41 is phosphonium ion, the ion of the N-type heavily doped region 41
Concentration is 8e14~5e15ion/cm2。
Specifically, the ion mixed in the N-type lightly doped district 42 is phosphonium ion, the ion of the N-type lightly doped district 42
Concentration is 1e13~5e14ion/cm2。
Specifically, the ion mixed in the p-type heavily doped region 52 is boron ion, the ion of the p-type heavily doped region 52
Concentration is 8e14~5e15ion/cm2。
Above-mentioned TFT substrate can be prevented by forming several grooves on interlayer dielectric layer in the processing procedure middle layer of TFT substrate
Between dielectric layer fall off from substrate, improve the electric property and reliability of TFT substrate.
In conclusion the present invention provides a kind of TFT substrate and preparation method thereof.The production method of TFT substrate of the invention,
It is made annealing treatment again after several grooves by being formed on interlayer dielectric layer, interlayer dielectric layer can be discharged by several grooves
Because of the stress that thermal expansion generates, prevents interlayer dielectric layer from falling off from substrate, improve the electric property and reliability of TFT substrate.
TFT substrate of the invention can prevent from being situated between the processing procedure middle layer of TFT substrate by forming several grooves on interlayer dielectric layer
Electric layer falls off from substrate, improves the electric property and reliability of TFT substrate.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the claims in the present invention
Protection scope.
Claims (5)
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| CN107275351A (en) * | 2017-08-02 | 2017-10-20 | 京东方科技集团股份有限公司 | Display device structure and the flexible display with the structure |
| CN107623042A (en) * | 2017-09-21 | 2018-01-23 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor structure and fabrication method thereof |
| CN108899326A (en) * | 2018-06-28 | 2018-11-27 | 武汉华星光电技术有限公司 | A kind of array substrate and preparation method thereof, display panel |
| CN115084168A (en) * | 2022-07-21 | 2022-09-20 | 福建华佳彩有限公司 | A kind of high stability oxide thin film transistor array substrate and preparation method |
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| CN105489552A (en) * | 2016-01-28 | 2016-04-13 | 武汉华星光电技术有限公司 | Manufacturing method of LTPS array substrate |
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| JPS57167655A (en) * | 1981-04-08 | 1982-10-15 | Jido Keisoku Gijutsu Kenkiyuukumiai | Manufacture of insulating isolation substrate |
| CN1779985A (en) * | 2004-10-29 | 2006-05-31 | Lg.菲利浦Lcd株式会社 | Active matrix organic light emitting diode device and manufacturing method thereof |
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