CN106095334B - A High-speed Data Acquisition and Storage System Based on FPGA - Google Patents
A High-speed Data Acquisition and Storage System Based on FPGA Download PDFInfo
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- CN106095334B CN106095334B CN201610395244.3A CN201610395244A CN106095334B CN 106095334 B CN106095334 B CN 106095334B CN 201610395244 A CN201610395244 A CN 201610395244A CN 106095334 B CN106095334 B CN 106095334B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
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Abstract
The high-speed data acquisition storage system based on FPGA that the invention discloses a kind of, including FPGA core core, data acquisition module, MPU module, Gigabit Ethernet module, display module, input and output, memory module.The memory module is connect by DDR3 with core devices FPGA, and the interfaces such as display, mouse, keyboard, kilomega network are connect by MPU module with PCI-E Switch, realizes the data interaction with FPGA.2 MINISAS interface modules, which are directly connected with FPGA, carries out data interaction.It can be realized the functions such as importing, export, the analysis of data, the maintenance of data by the software systems of system, and simple data may be implemented and analyze in real time.Message transmission rate of the invention is high, amount of storage is big, can live dilatation and progress Bad Block Management；System interface is more, user experience with higher；Interactivity is good between each modular unit of system, supports remote ethernet control.
Description
Technical field
The present invention relates to a kind of high-speed data acquisition storage systems, adopt more particularly to a kind of high-speed data based on FPGA
Collect storage system.
Background technique
Along with becoming increasingly popular for electronic product, the fast development of data acquisition technology and data storage technology has been driven.
Especially in technical fields such as satellite navigation, electronics, radars, data acquisition and memory system increasingly plays very important work
With.And the technical requirements of data acquisition and memory system are also increasingly improved: high data sample rates, high data rate,
Mass memory capacity, power consumption with it is at low cost.Traditional data acquisition and memory system is difficult to meet such requirement.
FPGA (Field Programmable Gate Array, the field programmable gate array) technology developed in recent years
Good technical support is provided for high-speed data acquisition storage system of new generation.FPGA has very more hardware resources, collection
At utilogic gate circuit on one chip up to ten million rank, very high time-frequency can be obtained by internal phaselocked loop,
Consume small when internal, and efficiency is very high, flexible structure, can integrate multiple controllers, translate coding and various peripheral interfaces electricity
Road, therefore FPGA can be used to come design data acquisition and data storage section.And in terms of signal processing, FPGA is due to rich
Rich kernel resources, convenient for users to calling.Therefore, high-speed data acquisition storage system uses FPGA, can simplify design, mention
The flexibility and processing speed of high system.
Chinese patent 201010623689.5 discloses a kind of high-speed data acquistion system based on FPGA, including receives mould
The differential amplification unit of quasi- signal, the A/D converting unit being connected with the differential amplification unit and the A/D converting unit
The FPGA processing unit being connected, the microprocessor being connected with the FPGA processing unit, the microprocessor pass through communication
Interface is connected with host computer.But the system has the following deficiencies: that the data storage capacity of 1. systems is small, does not support scene
Dilatation, and Bad Block Management can not be carried out.2. the interface of system is less, without software support, user experience is lower.3. system is each
Interactivity is poor between modular unit.4. system does not support remote ethernet to control.
Summary of the invention
It is an object of the invention to propose a kind of high-speed data acquisition based on FPGA in place of overcome the deficiencies in the prior art
Storage system, data storage capacity is big, live dilatation and can carry out Bad Block Management；The interface of the system is more, powerful
User experience under software support is high；Interactivity is good between each modular unit of system；Also, the system supports remote ethernet
Control.
In order to solve the above problem of the prior art, the present invention uses following technical scheme.
A kind of high-speed data acquisition storage system based on FPGA of the invention, including data transmission storage hardware system and
Data transmission storage software systems, it is characterised in that:
The data transmit storage hardware system, are integrated on a circuit board, comprising: FPGA core core, ETP are patched
Part module, PCI-E module, MPU daughter card module, Gigabit Ethernet module, display module, input/output module, MINISAS interface
Module, SSD storage array module, DDR3 cache module；
The Gigabit Ethernet module, display module, input/output module, SSD storage array module pass through MPU subcard
Module is connect with PCI-E module respectively, realizes the data interaction with FPGA core core；
The SSD storage array module is connect by least one level DDR3 cache module with FPGA core core；
The FPGA core core includes GTP module, for transmitting data in the form of differential signal；
MINISAS interface module described in 2 carries out data interaction for being directly connected with FPGA core core；
The MPU daughter card module includes ETX-Express connector, for the south bridge and north with the MPU subcard
The data of bridge are transmitted；
The SSD storage array module, including at least one by Flash flash media and control IC form it is external solid
State hard disk；
The data transmission storage software systems, including operating system, management software, MATLAB, communications protocol, disk battle array
Driving, bottom hardware drive part, importing, export for data, analysis, the maintenance of data, and simple data are real-time
Analysis；User carries out data interaction by display module, the input-output equipment of input/output module and system application.
Further, the FPGA core core use Xilinx Zynq-7000 chip comprising GTP module most
High Data Rate is 6.125Gbps.
Further, the ETP connector module, the EPT103-40064 connector including 2 96 cores；Described
The interface of EPT103-40064 connector includes 4 channels, and each channel can transmit 4 pairs of LVDS digital signals.
Further, the SSD storage array module, including multiple external solid state hard disks constitute multichannel data storage
The electric board battle array in channel.
Further, the PCI-E module can configure port containing 15 tunnels.
Further, the data in the FPGA core core need to carry out following mistake before being stored in SSD storage array
Journey: (1) the parallel-to-serial conversion in phase compensation, (2) 8b/10b coding, (3).
Further, the data in the SSD storage array module are being input to the progress data processing of FPGA core core
Before, need to carry out following procedure: (1) the serial-to-parallel conversion in the recovery of clock, (2), (3) byte of sync, (4) 8b/10b are compiled
Code, and (5) phase compensation.
Further, the data transmit storage hardware system, transmit storage hardware system including data described in 4
Integrated circuit board；The VPX interface, for the phase between each data transmission storage hardware system integrated circuit plate
Mutual communication and data interaction.
Compared with prior art, the advantages of the present invention include:
1. the storage system speed of present system is fast, stability is high, strong security.Support live capacity extensions, it can be straight
Connect replacement hard disk.Moreover, multiple memory channel parallel memorizings, convenient for the backup unloading of data.
2. can be used simultaneously software and hardware using wear-leveling algorithm, ECC check method, to the bad block of storage medium into
Row maintenance.It is effectively prevent the damage of storing data, the service life of FLASH can also be extended.For the data in bad block, when reading
It can be restored by software.It is stored by the way of external solid state hard disk array, the multichannel for forming electronic array formula is high
Speed storage realizes high speed, massive store, playback convenient for the backup unloading of data.Lasting writing speed >=700MB/ of veneer
s。
3. can operate selection by software is the importing for carrying out data or the export of data, and be may be implemented to data
The functions such as analysis, maintenance.Sophisticated software function improves user experience, mitigates data and analyzes difficulty.Using the MPU of standard
Subcard realizes the interfaces such as keyboard, mouse, kilomega network.Support the analysis softwares such as operating system, management software, support MATLAB.
It, can number by it to carry out between data board 4. using VPX interface as the bridge contacted between data board
According to interaction.Improve the efficiency and flexibility of entire system recorder memory.
5. system of the invention uses the EPT103-40064 connector of 2 96 cores, connector is by the difference on backboard
Signal is transferred directly to FPGA, without connecting with MPU module or PCI-E SWITCH.Pass through VPX connector and other numbers
The data transmission for carrying out high speed is interconnected according to acquisition and recording plate, flank speed is up to 1.25GB/S.
6. human-computer interaction function can be shown by gui interface, can show send and receive the control command to equipment,
BIT information, work state information of equipment etc..Support remote ethernet control.
Detailed description of the invention
Fig. 1 is the functional block diagram of one embodiment of the present of invention.
Fig. 2 is the internal logic schematic diagram of the high-speed transceiver (GTP) of one embodiment of the present of invention.
Fig. 3 is the PCI-E Switch functional block diagram of one embodiment of the present of invention.
Fig. 4 is the functional block diagram of the MPU module of one embodiment of the present of invention.
Fig. 5 is the software architecture block diagram of one embodiment of the present of invention.
Specific embodiment
A kind of high-speed data acquisition storage system based on FPGA of the invention, including data transmission storage hardware system and
Data transmission storage software systems, data are transmitted storage hardware system, are integrated on a circuit board, comprising: fpga core
Plate, ETP (European Technology Protocol) connector module, PCI-E module, MPU (Microprocessor
Unit microprocessor unit) daughter card module, Gigabit Ethernet module, display module, input/output module, MINISAS interface mould
Block, SSD storage array module (electric board battle array), DDR3 cache module；
The Gigabit Ethernet module, display module, input/output module, SSD storage array module pass through MPU subcard
Module is connect with PCI-E module respectively, realizes the data interaction with FPGA core core；It can between FPGA module and PCI-E module
To realize the exchange of data, the 1 road channel X4 of PCI-E module is connected with VPX interface, may be implemented on the interface board and backboard
Other backboards realize data interactions, and system is completely independent between these backboards, can be but non-interference with interaction data.
The SSD storage array module is connect by least one level DDR3 cache module with FPGA core core；For adjusting
Save the data difference of GTP module and SSD.
The FPGA core core includes GTP (Gigabit Transceiver with Low Power gigabit transmitting-receiving
Device) module, for data to be transmitted in the form of differential signal；To reduce interference of the external equipment to data.
MINISAS interface module described in 2 carries out data interaction for being directly connected with FPGA core core；Without
It is connect with MPU module or PCI-E SWITCH.
MPU daughter card module described in the embodiment of the present invention include ETX-Express connector, for MPU
The data transmission of the south bridge and north bridge of card；Its north bridge has 1 road 533MHz 64Bit and DDR2 caching to connect, and has 3 tunnels and ETX-
Express connector is connected, and is 1 road VGA analog signal, 1 road LVDS and 1 road PCI 16 respectively.Between the south bridge of MPU module
Pass through 4 road DMI 2.5GB/s connections.Compared to north bridge, the channel that south bridge is connect with ETX-Express connector is more, comprising: 1
Road LPC33MHz 4,1 road USB1.5/12/480MHz 6,2 road DATA 1.5GB/s, 1 road A/C, 4 road PCI-Express
2.5GB/s, 1 road IDE, 1 road GPIO, 1 road PCI 33MHz 32, in addition, there is 1 tunnel between south bridge and ETX-Express connector
It is connected by 10/100B-T Ethernet.ETX-Express not only carries out data interaction with north and south bridge, also provides for
12VDC and SVSBY signal.
The SSD storage array module, including at least one by Flash flash media and control IC (Integrated
Circuit) the external solid state hard disk formed；
The data transmission storage software systems, including operating system, management software, MATLAB, communications protocol, disk battle array
Driving, bottom hardware drive part, importing, export for data, analysis, the maintenance of data, and simple data are real-time
Analysis；User carries out data interaction by display module, the input-output equipment of input/output module and system application.It should
The function of software systems is mainly reflected in three aspects: 1, display function: being realized based on Windows operating system, man-machine friendship
Mutual function can be shown by gui interface, can be shown and be sended and received the control command to equipment, BIT information, the work of equipment
Make status information etc..2, system hardware equipment control function: starting/stopping of record starting/stopping, playback including equipment,
The selection control etc. of the work method control, data input channel of equipment.3, data management function: mainly including to record data
Query function (according to temporal information), the interception of data, data upload/download function.MATLAB can additionally be passed through
Equal softwares simply analyze data.
The FPGA core core use Xilinx Zynq-7000 chip comprising GTP module the maximum data rate
For 6.125Gbps.The FPGA of the product has been internally integrated ARM, and the two carries out high speed connection by AXI4 bus, efficiently solves
Transmission problem between FPAG and ARM.In addition, the power consumption of its high-speed transceiver GTP is very low, 500Mb/s -6.6Gb/s can be supported
Transmission rate.
The ETP connector module, the EPT103-40064 connector including 2 96 cores；The EPT103-
The interface of 40064 connectors includes 4 channels, and each channel can transmit 4 pairs of LVDS digital signals.The ETP connector mould
The EPT103-40064 connector of 2 96 cores of block, being used for transmission to the signal of FPGA core core further includes 1 tunnel clock signal, 1
Road synchronization signal and 4 road space signals.
The SSD storage array module, including multiple external solid state hard disks constitute the electronics of multichannel data memory channel
Disk battle array.The electric board battle array can carry out Bad Block Management, wear-leveling algorithm, ECC check etc..The amount of capacity of one paths is
The storage of 32T vast capacity can be realized in 8T, four paths.And support the dilatation of live capacity, in the case where deposit has been expired
Hard disk can directly be replaced.
The PCI-E module can configure port containing 15 tunnels.By these ports, data and control can be not only transmitted
The bridge that system/management information or FPGA module are connect with gigabit network interface, display, input-output equipment.
Data in the FPGA core core need to carry out following procedure before being stored in storage array: (1) phase is mended
It repays, the conversion that (2) 8b/10b is encoded, (3) are parallel-to-serial.
Data in the SSD storage array module, need to be into before being input to FPGA core core and carrying out data processing
Row following procedure: (1) recovery of clock, (2) serial-to-parallel conversion, (3) byte of sync, (4) 8b/10b coding, and
(5) phase compensation.
The data transmit storage hardware system, transmit storage hardware system integrated circuit including data described in 4
Plate；The VPX interface, between described each data transmission storage hardware system integrated circuit plate being in communication with each other with
Data interaction.
The present invention is described in further details with reference to the accompanying drawing.
Fig. 1 is the functional block diagram of one embodiment of the present of invention.As shown in Figure 1, one kind of one embodiment of the present of invention
High-speed data acquisition storage system based on FPGA, template size is 6U, having a size of 233.35 × 220mm, the thickness of board
No more than 40.3mm.The power consumption of the data acquisition and memory system plate of one monolithic is less than 50W.The data acquisition logging system leads to
The Zynq-7000 Series FPGA of Xilinx is crossed to realize the high speed acquisition of data, quickly transmits and stores.And FPGA and MPU mould
Then by the PCI-E Switch of Integrated Device Technology, Inc., (external component interconnected bus interface is opened for data transmission, control and management between block
Close) chip realization.
LVDS interface, the port PCI-E and 2 MINI SAS (the mini strings on connector are realized by FPGA core core
Row connecting interface) interface (MINISAS interface is only used, to realize the data transmission of LVDS (low-voltage differential signal) signal,
12 data widths, the clock used is 100MHz, i.e., data conversion of total data transfer rate between 150MB/S).Notebook data
Acquisition and recording system uses the EPT103-40064 connector of 2 96 cores.It include 4 transmission channels, Mei Gechuan on the interface
Defeated channel can transmit 2 groups (Rx and Tx) 4 pairs of LVDS signals, data transfer rate 80Mbps；Other transmission signals are believed comprising 1 road clock
Number, 1 tunnel synchronization signal and 4 road space signals.That is 4 channels may be implemented 160MB/S data transmission, for data store with
And playback, so that the data collection system carries out data acquisition independently of other systems.PCI-E Switch device draws one simultaneously
Road PCI-E × 4 carry out high speed by VPX (high-speed serial bus interface) connector and the interconnection of other data acquiring and recording plates
Data transmission, flank speed 1.25GB/S.
This system, as memory, realizes that high speed, large capacity are deposited using the electric board battle array of SSD storage array module composition
Storage, playback.The characteristics of electric board battle array operating rate is fast, stability is high, strong security, therefore it is usually used in special machine and Industry Control
Machine.Electric board battle array is made of Flash flash media and control IC, is a kind of memory that can repeatedly read and write, is installed and using non-
It is often convenient.Since storage medium is flash memory, shake-proof ability is stronger than common hard disc；Moreover, speed faster, it is light-weight, it is very suitable
It is used for mobile.In addition, due to the rotating media of the not no common hard disc of the electric board battle array, thus shock resistance is splendid, while work
Make that temperature range is wide, the electric board battle array of extended temperature can work in -40C-+85C, therefore can be widely applied to network computer
(NC), Industry Control, aerospace is military, the fields such as navigation equipment.
Fig. 2 is the internal logic schematic diagram of the high-speed transceiver (GTP) of one embodiment of the present of invention.As shown in Fig. 2, this
The GTP high-speed transceiver of inventive embodiments is made of PCS (Physical Coding Sublayer) with PMA (physical medium is connect).Sendaisle
The parallel signal that partial PMA is mainly responsible for the input of stringization 8b/10b encoder section is bit stream, and the PMA of receiving portion is responsible for
By the data of SFP optical module part input by serially becoming parallel, but first have to restore clock data from serial data
Out.Because the time-frequency required precision that transceiver uses is high, the PCS of sendaisle part signal to be sent first is defeated
Applying aspect compensates FIFO, and to compensate the PCS phase of transmitting portion and the difference of FPGA kernel phase, external input reference clock will lead to
Special phase-locked loop circuit is crossed to generate, after through phase compensation FIFO, parallel data and serial data can be highly same
Step.
Fig. 3 is the PCI-E Switch functional block diagram of one embodiment of the present of invention.As shown in figure 3, PCI-E Switch
It is a kind of equipment similar to common USB Hub, but it can have up to N number of port, be widely used in biography
In the storage system of system.Switch is new concept, it is compared with the bridge mode of previous generation standard PCI-X, a maximum sheet
Matter difference is exactly to exchange between multiple roles inside the same Bus using Switch, and be no longer Bus, and one
Switch is equivalent to the set of a virtual bridge and virtual Bus.In addition PCI-E Switch can be by affairs between each port
Transmitting.
The 92HD81B1B5NLB of Integrated Device Technology, Inc. is that the PCI Express Gen 2 of 15 port, 48 channel (Lanes) is supported to open
Chip is closed, the number of channels of each port may be configured to x4, and x8 either x16 adds up to the bandwidth of 480GT/S.
The structure of 92HD81B1B5NLB chip is designed that comparison is flexible, and 48 channels are distributed in 3 Station by it, and each
A Station can be connected in Packet RAM by internal bus, greatly improve efficiency.Each channel can also match
It is set to upstream and downstream port.
Specific each wide opening of PCI-E uses: the PCI-E of 5 road X2 is used for interface, and the PCI-E of 1 road X4 is used for X86 module,
The PCI-E of 1 road X1 is used for optical fiber.
Fig. 4 is the functional block diagram of the MPU module of one embodiment of the present of invention.As shown in figure 4, using MPU of standard
Block (using storage section as motherboard) to realize the interfaces such as display, keyboard, mouse, kilomega network.MPU daughter card module includes a piece of master
Centrino processor of the frequency in 1.4G to 2.13G.Bandwidth between the processor and ITP-700 is 133MHz.Pass through 533MHz
FSB*64-Bit is connected with the north bridge of MPU module.Kernel supply voltage is provided by RM-IMVP-IV.
The north bridge of MPU module has 1 road 533MHz 64Bit and DDR2 caching to connect, and has 3 tunnels and ETX-Express connector
It is connected, is 1 road VGA analog signal, 1 road LVDS and 1 road PCI 16 respectively.Pass through 4 road DMI between the south bridge of MPU module
2.5GB/s connection.Compared to north bridge, the channel that south bridge is connect with ETX-Express connector includes: 1 road LPC33MHz 4,1 tunnel
USB1.5/12/480MHz6,2 road DATA 1.5GB/s, 1 road A/C, 4 road PCI-Express 2.5GB/s, 1 road IDE, 1 tunnel
Furthermore GPIO, 1 road PCI 33MHz32 are connected there are also 1 tunnel by 10/100B-T Ethernet between south bridge and connector.
ETX-Express not only carries out data interaction with north and south bridge, also offer 12VDC and SVSBY signal.
Fig. 5 is the software architecture block diagram of one embodiment of the present of invention.As shown in figure 5, the software of high speed acquisition equipment is
It is realized based on Windows operating system, is mainly used to realize human-computer interaction, the control of functions of the equipments module, data management, letter
Forms data analysis, BIT work of system etc..According to shown in software architecture, when operator needs to carry out data interaction with machine,
It can be received by display, keyboard, mouse or be sent to equipment control command.It (1) is control command when equipment receives
When, just communications protocol according to response, control bottom hardware driving, and operating result is shown back to application layer by display
It shows and.(2) when equipment receive be data management instruction, just starting response disk battle array driving, disk battle array drive further
Bottom hardware driving is called, equally shows operating result by display.
Equipment control function includes record starting/stopping, the starting/stopping of playback, the working method control of equipment of equipment
System, selection control of data input channel etc..
Its data management function mainly includes to the record query function of data, the interception of data, upload/downloading of data
Function.
In short, a kind of high-speed data acquisition storage system based on FPGA of the invention, can pass through EPT from terminal device
Connector sampled echo data are transmitted by low voltage difference (LVDS) technology high-speed, are transferred to FPGA and are carried out at real time data
Reason analysis.FPGA treated data are transferred to the high speed storing that storage array carries out data via optical fiber.The design scheme mentions
It for interfaces such as mouse, keyboard, gigabit Ethernets by PCI-E Switch device, is interconnected with fpga core board chip, supports data
Inquiry and interception, recording status monitoring, the file information instruction, remote ethernet control function.
Claims (8)
1. a kind of high-speed data acquisition storage system based on FPGA, including data transmission storage hardware system and data transmission are deposited
Store up software systems, it is characterised in that:
The data transmit storage hardware system, are integrated on a circuit board, comprising: FPGA core core, ETP connector mould
Block, PCI-E module, MPU daughter card module, Gigabit Ethernet module, display module, input/output module, MINISAS interface mould
Block, SSD storage array module, DDR3 cache module；
The Gigabit Ethernet module, display module, input/output module, SSD storage array module pass through MPU daughter card module
It is connect respectively with PCI-E module, realizes the data interaction with FPGA core core；
The SSD storage array module is connect by least one level DDR3 cache module with FPGA core core；
The FPGA core core includes GTP module, for transmitting data in the form of differential signal；
MINISAS interface module described in 2 carries out data interaction for being directly connected with FPGA core core；
The MPU daughter card module includes ETX-Express connector, for the south bridge and north bridge with the MPU subcard
Data transmission；
The SSD storage array module, the external solid-state being made of including at least one Flash flash media and control IC are hard
Disk；
The data transmission storage software systems, including operating system, management software, MATLAB, communications protocol, disk battle array are driven
Dynamic, bottom hardware drive part, importing, export for data, analysis, the maintenance of data, and simple data are divided in real time
Analysis；User carries out data interaction by display module, the input-output equipment of input/output module and system application.
2. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, it is characterized in that: described
FPGA core core use Xilinx Zynq-7000 chip comprising GTP module the maximum data rate be 6.125Gbps.
3. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, it is characterized in that: described
ETP connector module, the EPT103-40064 connector including 2 96 cores；The interface of the EPT103-40064 connector
Including 4 channels, each channel can transmit 4 pairs of LVDS digital signals.
4. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, it is characterized in that: described
SSD storage array module, including multiple external solid state hard disks constitute the electric board battle array of multichannel data memory channel.
5. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, it is characterized in that: described
PCI-E module can configure port containing 15 tunnels.
6. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, it is characterized in that: described
Data in FPGA core core need to carry out following procedure before being stored in SSD storage array:
(1) phase compensation；
(2) 8b/10b is encoded；
(3) parallel-to-serial conversion.
7. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, it is characterized in that: described
Data in SSD storage array module need to carry out following procedure before being input to FPGA core core and carrying out data processing:
(1) recovery of clock；
(2) serial-to-parallel conversion；
(3) byte of sync；
(4) 8b/10b is encoded；
(5) phase compensation.
8. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, it is characterized in that: the number
According to transmission storage hardware system, storage hardware system integrated circuit plate and VPX interface are transmitted including data described in 4；It is described
VPX interface, for being in communication with each other between described each data transmission storage hardware system integrated circuit plate and data are handed over
Mutually.
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| CN106933165A (en) * | 2017-05-05 | 2017-07-07 | 天津市英贝特航天科技有限公司 | Method and equipment for multi-way switching value input and output |
| CN107167773B (en) * | 2017-05-10 | 2019-10-08 | 湖北航天技术研究院总体设计所 | Radar Signal Processing System and Design Internet Applications method based on VPX platform |
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