CN1060279C - Inter-processor asynchronous serial communication transmissoin/reception apparatus using each other's memories - Google Patents
Inter-processor asynchronous serial communication transmissoin/reception apparatus using each other's memories Download PDFInfo
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- CN1060279C CN1060279C CN96104639A CN96104639A CN1060279C CN 1060279 C CN1060279 C CN 1060279C CN 96104639 A CN96104639 A CN 96104639A CN 96104639 A CN96104639 A CN 96104639A CN 1060279 C CN1060279 C CN 1060279C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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Abstract
An inter-processor asynchronous serial communication transmission/reception apparatus can read/write opposite party processor data like in a parallel communication, and allow a few line drivers to be enough like in a serial communication and to attain remote distance transmission. It includes prosessor A, mode register, address register, TXD register, parallel/serial register, line driver, parity generator, wait register, the first and second counter, line receiver, parity verify register, error manner detector, the first and second logic gate.
Description
The invention relates in communication system the invention of employed device when transmitting data, particularly about in the invention of the storer that uses the other side to the device that utilizes waiting mode with two processor asynchronous serial communication methods using the other side's storer.
In the past, between processor, during Data transmission, use serial communication or parallel communications.But, though useful few line just can be data transfer to remote advantage when serial communication, because of the restriction of transmission speed exists it to use restricted shortcoming.On the other hand, though its transmission speed is faster than serial communication when parallel communications, use is also convenient, but there is the shortcoming that needs numerous drivers when needing many transfer cable wires and distant location will be sent to.
In addition, between two processors that use the other side's storer, in the asynchronous serial transmission/receiving trap, the method for the look-at-me utilized is arranged.The problem that invention will solve
Yet the mode that above-mentioned use is interrupted is when carrying out data transfer continually with the other side, because of interruption needs extra processing capacity, so the problem points that exists performance to reduce.
In addition, as the technology of using asynchronous serial communication, though United States Patent (USP) once had motion No. 5388091, it mainly is to be used on the test unit of checking the electronic-controlled installation characteristic, does not propose to use the technology of the other side's storer.
The present invention writes or reads the data that the other side handles desired address the parallel communications for its objective is of solving that above-mentioned traditional problem does provides a kind of can the elephant, and be to resemble to need less transmission line and less driver the serial communication, just can transfer data to two inter-processor asynchronous serial communication transmission/receiving traps that use the other side that larger distance goes stores reservoir.For achieving the above object, the present invention takes following technical scheme:
Asynchronous serial communication R-T unit between two processors of use the other side storer of the present invention is made of following each one:
Processor A, it produces selectively with processor B and carries out required feed signals of data transmission/reception, read signal, write signal, address signal, data-signal and central processing unit clock signal, and receive input reset signal, waiting signal and rub-out signal;
Mode register, address register 10, transmitting data register, these registers receive chip selection signal, read signal and the write signal of input processor A respectively;
Parallel/serial register, this register receives the input mode register, output separately of address register, transmitting data register and the clock that provides by the outside, and export to data being sent to the employed bus driver of processor B;
Bus driver;
Even-odd generator, this generator receive input simultaneously, and parallel/serial register receives the data of input, produces odd even and it is exported to parallel/serial register;
Waiting register, this register receive the above-mentioned data value that is transfused to of input selectively and provide reset signal to time delay and processor A, and its value is outputed to the 1st counter;
The 1st counter;
Bus receiver, this device are used for giving processor A the data transfer of processor B;
Parity checking register, this register receive the data of input bus receiver and it are exported to and receive the 2nd logic gate of having imported from the wrong way detector signal;
The serial register, this register also outputs signal to the parity checking register when selectively signal being exported to waiting register.
Wrong way detecting device, this detecting device receive the output signal of the above-mentioned bus receiver of input and clock and it are exported to the 2nd logic gate;
The 2nd logic gate, this logic array produces rub-out signal according to the value from parity checking register, wrong way detecting device that receives input, and it is exported to processor A;
The 2nd counter, this counter receives the output and the central processing unit clock signal of input mode register, waiting register, and it is exported to the 1st logic gate;
The 1st logic gate, this logic array respectively with the output of the 1st counter, the 2nd counter as input, and waiting signal exported to processor A.
The effect of invention is as follows:
As previously mentioned, the present invention is an asynchronous serial communication mode of utilizing the twoport dynamic RAM, not only have by few several transmission lines constitute and corresponding therewith required driver reduces the economic benefit of being brought, but also have the convenience of physically using.In addition, can also provide can be as Shi Yonging oneself storer use the convenience in logic of the parallel communication method of the other side's twoport dynamic RAM.
Also have, existing problem when using look-at-me in order to solve when using waiting signal frequency ground to carry out data transfer with the other side, does not need the advantage of the extra processing capacity that requires because of interruption in addition.Following with reference to accompanying drawing, embodiments of the invention are elaborated:
Fig. 1 is between two processors as use of the present invention the other side storer
The square frame pie graph of asynchronous serial communication transmission/receiving trap.
Fig. 2 is to use between two processors of the other side's storer asynchronous serial logical
The mode of letter transmission/receiving trap is set address architecture figure.Fig. 3 is the data layout structure between processor B and apparatus of the present invention among Fig. 1
Make figure.
TXD data layout when (A) writing (WRITE)
Structural map.
(B) be the structure of TXD data layout when reading (READ)
Make figure.
(C) be mode (MODE) TXD data layout when utilizing
Structural map.
The structural map of RXD data layout when (D) being normal condition.
The structure of RXD data layout when (E) being the TXD bad parity
Figure.Fig. 4 is when processor A writes processor B to data in Fig. 1, handles
The sequential chart of the signal that constitutes between device A and apparatus of the present invention.When Fig. 5 is the data of processor A read processor B in Fig. 1, handle
The sequential chart of the signal that constitutes between device A and the processor B.
Below, describe the present invention with reference to the accompanying drawings in detail.
Fig. 1 is the square frame pie graph of asynchronous serial communication transmission/receiving trap between two processors of use the other side storer of the present invention, it is made of the following portion that is equipped with: mode register 1, address register 2, transmitting data register 3, waiting register 4, the 1st logic gate 5, the 1st counter 6, the 2 counters 7, even-odd generator 8, the 2nd logic gate 9, parallel/serial register 10, serial register 11, parity checking register 12, wrong way detecting device 13, and bus driver 14 and bus receiver 15.
That is be the formation that comprises following each several part: promptly comprise: be produced as selectively with processor B and carry out the required chip selection signal/CS of data transmission/reception, read signal/RD, write signal/WR, address signal ADDRESS, data-signal DATA, central processing unit clock CPUCLK signal and input reception reset signal/RESET, waiting signal/WAIT, the processor A of rub-out signal ERR; Each having selectively, input receives chip selection signal/CS, the read signal/RD of above-mentioned processor A, the mode register 1 of write signal/WD; Address register 2; Transmitting data register 3; Aforesaid way register 1, address register 2, transmitting data register 3 output separately and the clock CLK that is provided by the outside are provided in input, and it is exported to data transfer being given the parallel/serial register 10 of the employed bus driver of processor B; Bus driver 14; Input simultaneously receive above-mentioned parallel/serial register 10 import the data that receive, the generation odd even is also exported to it even-odd generator 8 of parallel/serial register 10; Input receives the above-mentioned data value that is transfused to selectively, provides reset signal/RESET to time delay and processor A, and its value is exported to the waiting register 4 of the 1st counter 6; The 1st counter 6; For giving the employed bus receiver 15 of processor A the data transfer of processor B; Input receives the data of bus receiver 15, and it is exported to the parity checking register 12 of reception input from the 2nd logic gate of the signal of wrong way detecting device 13; When selectively signal being exported to waiting register 4, also export to the serial register 11 of parity checking register 12; Receive output signal and clock CLK that imports above-mentioned bus receiver 15 and the wrong way detecting device 13 of exporting to the 2nd logic gate 9, and according to from parity checking register 12, the value that 13 inputs of wrong way detecting device receive produces rub-out signal/ERR and it is exported to the 2nd logic gate 9 of processor A; Input receives the output and the central processing unit clock CPUCLK signal of aforesaid way register 1 and waiting register 4 and exports to the 2nd counter 7 of the 1st logic gate 5; Also waiting signal/WAIT is exported to the 1st logic gate 5 of processor A respectively as input with the output of above-mentioned the 1st counter the 6, the 2nd counter 7.
Fig. 2 is to use the mode of asynchronous serial communication transmission/receiving trap between two processors of the other side's storer to set address architecture figure, be one by the address of the mode register 1 that is imported into Fig. 1 with the signal/RD when reading and write the determined mode address of fashionable signal/WR.
That is, be by the data field 21 of transmission/WR=0 and reception/RD=0 and waiting register district 22 and the mode address section that constitutes to the zone of mode n district 23-n by mode 0 district 23-0.
Shown in Figure 3 is the processor B of Fig. 1 and the structural map of the data layout between apparatus of the present invention, A is the structural map of bus driver signal TXD data layout when writing WRITE, B is a bus driver signal TXD data layout structural map when reading READ, C is mode MODE bus driver signal TXD data layout structural map when utilizing, bus receiver RXD data layout structural map during bus driver signal TXD bad parity when D is normal condition.
That is, in above-mentioned each situation, after the input of first start bit, resemble that mode appears in bus driver signal TXD data layout in proper order when writing WRITE the A, the address, data and parity bit, resemble that mode appears in bus driver signal TXD data layout in proper order when reading READ the B, address and parity bit, resemble the good sample loading mode MODE of C when utilizing bus driver signal TXD data layout order be mode and parity bit, bus receiver signal RXD data layout is data in proper order when resembling the D normal condition, parity bit, bus receiver signal RXD data layout then presents wrong way when resembling the E bus driver signal TXD bad parity.
Fig. 4 is that the processor A of Fig. 1 is when writing processor B to data, the sequential chart of some signals that constitute between processor and apparatus of the present invention, provide chip selection signal/CS that the variation owing to central processing unit clock CPUCLK signal causes among the figure, write signal/WR, address signal ADDRESS, data-signal DATA, the level of waiting signal/WAIT changes.Here, represent useful double-address district and useful data field with the rectangle of the sequential chart of ADDRESS and DATA central authorities bottom respectively like the part of performance.
When Fig. 5 was the data of processor A read processor B of Fig. 1, the sequential chart of some signals that constitute between processor A and the processor B was that the variation by CLK causes/CS shown in the figure ,/RD, and ADDRESS, DATA, RXD, the level of/WAIT changes.
Wanting when the processor A of Fig. 1 writes data into processor B, at first on processor A, as the sequential chart of Fig. 4, / CS ,/WR are " low " state, when the address is arranged in the transmission of Fig. 2/reception data area 21, mode register 1 is transfused to WRITE mode value, simultaneously, the value that is positioned on the address wire is transfused to address register 2, and the value that is positioned on the data line is transfused to transmitting data register 3.Suppose when the CPU speed of processor A is faster than the visit access time of apparatus of the present invention, then the CPUCLK number that should wait for is placed the waiting register district 22 of Fig. 2, promptly input to the waiting register 4 of Fig. 1.This reset values of waiting for register 4 is the maximal value of this register.
If only postpone the value of this wait register 4 and input to address register 2, transmitting data register 3, when then resembling the WRITE of Fig. 3 by parallel/serial register 10 form of TXDA with mode register 1, address register 2, the order of data register 3, the parallel value of register become string value TXD and are output away.At this moment, the input data that enter parallel/serial register 10 are input to even-odd generator 8 simultaneously, produce odd even and are imported into the odd even input end of parallel/serial register 10.
This is parallel in order to drive/data that serial register 10 comes out arrive more remote, 14 transmission of use bus driver.
On the other hand, when processor A is thought the data of read processor B, at first at the sequential chart of processor A one side as Fig. 5, / CS, / RD becomes " low " state, and when being arranged in the transmission of Fig. 2/reception data area in the address, the READ value is imported into mode register 1, the value that is positioned at simultaneously on the address wire is imported into address register 2, and the value that is positioned on the data line is imported into transmitting data register 3.
At this moment, no matter the value of waiting register 4 how, waiting signal is in case be " low ", the RXD signal of Fig. 5 just is output out by bus receiver 15, when this RXD is the normal condition of Fig. 3, when promptly having the form of RXDD, the start bit is imported into the 2nd counter 7 of Fig. 1, above-mentioned RXD is imported into serial register 11, when parallel data all disappears ,/WAIT signal is become " height " by " low ".
At this moment, putting the value that is stated from the data line has just been read by processor A.
If when odd even is checked by parity checking register 12 in the parallel data footpath of serial register 11 outputs bad parity takes place, then becomes " low " by the 2nd logic gate handle/ERR signal.
And, when the RXD that exports out from bus receiver 15 has wrong way, check mistake with error detector 13, and become " low " by the 2nd logic gate handle/ERR signal.
When beyond last brown READ becomes WRITE, using other modes, when promptly the mode MODE of Fig. 3 utilizes, carry the TXDC form.This is one and is similar to above-mentioned WRITE mode, and the mode of the expectation of address area in the mode zone of Fig. 2.
Claims (5)
1. use asynchronous R-T unit between two processors of the other side's storer, its characteristic is to comprise: for carrying out data transmission/reception with processor B, and produce selectively chip selection signal (/CS), read signal (/RD), write signal (/WR), address signal, data-signal, central processing unit clock signal, receive simultaneously the input reset signal (/RESET), waiting signal (/WAIT), the processor A of rub-out signal (ERR);
Receive selectively respectively the above-mentioned processor A of input chip selection signal (/CS), read signal (/RD) and write signal (/WR) mode register (1), address register (2) and transmitting data register (3);
Receive output of sending separately by aforesaid way register (1), address register (2), transmitting data register (3) and the clock that provides by the outside are provided, and export to bus driver (14) data are sent to parallel/serial register of processor B;
Bus driver (14);
Receive the data of importing above-mentioned walking abreast/input that serial register receives simultaneously, produce odd even and also this odd even is exported to the even-odd generator (8) of parallel/serial register (10);
Receive selectively the above-mentioned data value that is transfused to of input and reset signal (/RESET) offer time delay and processor A, again this value is exported to the waiting register (4) of the 1st counter (6);
The 1st counter (6);
The data of processor B are sent to the employed bus receiver of processor A (15);
Receive the data of input bus receiver and it is exported to the parity checking register (12) of reception input from the 2nd logic gate of the signal of wrong way detecting device (13);
When signal being exported to waiting register (4) selectively, also export to the serial register (11) of parity checking register (12);
Receive the output signal of the above-mentioned bus receiver of input (15) and clock (CLK) and it is exported to the wrong way detecting device (13) of the 2nd logic gate (9);
According to the value that receives input by odd-even check register (12), wrong way register produce rub-out signal (/ERR) and with it export to the 2nd logic gate (9) of processor A;
The output and central processing unit clock (CPUCLK) signal that receive input aforesaid way register (1), waiting register (4) are exported to the 2nd counter (7) of the 1st logic gate (5) with it;
Respectively the output of above-mentioned the 1st counter the 6, the 2nd counter (7) as input, and waiting signal (/WAIT) export to the 1st logic gate (5) of processor A.
2. asynchronous R-T unit between two processors of use the other side storer according to claim 1, it is characterized in that: will be when above-mentioned processor A writes processor B to data, processor A one side, chip selection signal, write signal is set as " low " state, when (ADDRESS) is arranged in transmission/reception data field in the address, when the WriteMode value is transfused to mode register (1), be transfused to address register (2) by the value that is positioned at address wire, and the value that is positioned at data line is imported into transmitting data register (3), can when the CPU of processor A speed is faster than the access time, judge and wait for, and the number of central processing unit clock (CPUCLK) placed the waiting register district and be input to waiting register (4), the reset values of waiting register (4) is if reach maximal value, the value that then only postpones above-mentioned waiting register (4), and be input to address register (2), transmitting data register (3), then, press mode register (1) by parallel/serial register (10), the order of address register (2) and data register (3), make the parallel value of register become signal (TXD), and export away for the string value bus driver.
3. asynchronous R-T unit between two processors of use the other side storer according to claim 2, it is characterized in that: the input data that enter into above-mentioned walking abreast/serial register (10) also are imported into storer generator (8) and produce odd even simultaneously, be imported into the odd even input end of parallel/serial register (10) again, more remote in order to order about from the data arrival of parallel/serial register (10) output, utilize bus driver (TXD) (14) to send data to processor B.
4. asynchronous R-T unit between two processors of use the other side storer according to claim 1, it is characterized in that: when processor A is wanted the data of read processor B, select signal at processor A one side sheet, reading signal is " low " state, when being arranged in transmission/reception data area in the address, read (READ) mode value and be imported into mode register (1), simultaneously, the value that is positioned at address wire is imported into address register (2), the value that is positioned at data line is imported into data register (3), waiting signal though waiting register (4) value how to put " low ", the signal of bus receiver (RXD) is output out by bus receiver, when the signal (RXD) of bus receiver when being normal condition, the start bit is inputed to counter (7), when above-mentioned RXD is imported into serial register (11) and all exports parallel data, waiting signal (/WAIT) become " height " by " low ", then processor A just reads and puts the value that is stated from the data line.
5. asynchronous R-T unit between two processors of use the other side storer according to claim 4, it is characterized in that: by the parallel data of above-mentioned serial register (11) output during by parity checking register (12) verification odd even, if produce bad parity, then by the 2nd logic gate (9) make (/ERR) signal becomes " low ", when the RXD from bus receiver (RXD) (15) output has wrong way, check mistake with error detector (13), and according to the 2nd logic gate (9) make (/ERR) signal becomes " low " and shows and detect mistake.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR9100/1995 | 1995-04-18 | ||
| KR1019950009100A KR0174853B1 (en) | 1995-04-18 | 1995-04-18 | Asynchronous Serial Communication Transmit / Receive Device Between Two Processors Using Other Memory |
| KR9100/95 | 1995-04-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1142637A CN1142637A (en) | 1997-02-12 |
| CN1060279C true CN1060279C (en) | 2001-01-03 |
Family
ID=19412432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96104639A Expired - Fee Related CN1060279C (en) | 1995-04-18 | 1996-04-18 | Inter-processor asynchronous serial communication transmissoin/reception apparatus using each other's memories |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5748887A (en) |
| JP (1) | JP2763871B2 (en) |
| KR (1) | KR0174853B1 (en) |
| CN (1) | CN1060279C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6332173B2 (en) * | 1998-10-31 | 2001-12-18 | Advanced Micro Devices, Inc. | UART automatic parity support for frames with address bits |
| KR100465157B1 (en) * | 2002-10-16 | 2005-01-13 | (주)씨앤에스 테크놀로지 | Asynchronous interfacing apparatus |
| US20060031596A1 (en) * | 2004-08-05 | 2006-02-09 | International Business Machines Corporation | Method and apparatus for providing an alternate route to system memory |
| US7243173B2 (en) * | 2004-12-14 | 2007-07-10 | Rockwell Automation Technologies, Inc. | Low protocol, high speed serial transfer for intra-board or inter-board data communication |
| US7792196B2 (en) * | 2004-12-28 | 2010-09-07 | Intel Corporation | Single conductor bidirectional communication link |
| US7650561B1 (en) * | 2005-07-12 | 2010-01-19 | Seagate Technology Llc | Method of switching from parallel to serial MAP detector |
| US7831754B1 (en) * | 2006-10-20 | 2010-11-09 | Lattice Semiconductor Corporation | Multiple communication channel configuration systems and methods |
| CN103425611B (en) * | 2013-05-20 | 2016-05-18 | 万高(杭州)科技有限公司 | For the serial port communication method of metering field |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1038363A (en) * | 1988-06-03 | 1989-12-27 | 成都科技大学 | Time-sharing communication interface of multi-microprocessor system |
| CN1046235A (en) * | 1989-04-04 | 1990-10-17 | 横河电机株式会社 | Duplex computer system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4377843A (en) * | 1979-04-19 | 1983-03-22 | Wescom Switching, Inc. | Data distribution interface |
| GB2101859A (en) * | 1981-04-22 | 1983-01-19 | Pitney Bowes Inc | Display processor for use in a word processing system |
| JP3149518B2 (en) * | 1992-04-17 | 2001-03-26 | 住友電気工業株式会社 | Communication mechanism between in-vehicle electronic control unit and test equipment |
| US5349611A (en) * | 1992-11-13 | 1994-09-20 | Ampex Systems Corporation | Recovering synchronization in a data stream |
-
1995
- 1995-04-18 KR KR1019950009100A patent/KR0174853B1/en not_active IP Right Cessation
-
1996
- 1996-04-17 US US08/634,020 patent/US5748887A/en not_active Expired - Fee Related
- 1996-04-18 CN CN96104639A patent/CN1060279C/en not_active Expired - Fee Related
- 1996-04-18 JP JP8096824A patent/JP2763871B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1038363A (en) * | 1988-06-03 | 1989-12-27 | 成都科技大学 | Time-sharing communication interface of multi-microprocessor system |
| CN1046235A (en) * | 1989-04-04 | 1990-10-17 | 横河电机株式会社 | Duplex computer system |
Also Published As
| Publication number | Publication date |
|---|---|
| US5748887A (en) | 1998-05-05 |
| KR0174853B1 (en) | 1999-04-01 |
| JPH09102808A (en) | 1997-04-15 |
| CN1142637A (en) | 1997-02-12 |
| JP2763871B2 (en) | 1998-06-11 |
| KR960038645A (en) | 1996-11-21 |
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