GB2101859A - Display processor for use in a word processing system - Google Patents

Abstract

A display processor for use in a word processing system having a C.R.T. monitor (35) for displaying alpha- numeric data at one of a plurality of sizes. A central processing unit (CPU) (10) for processing data to be displayed has a drive means including a crystal oscillator (40, 42) whereby the CPU (10) can be driven at a plurality of discrete frequencies, dependent upon the oscillator frequency thereby to vary the size of the characters displayed. <IMAGE>

Description

SPECIFICATION Display processor for use in a word processing system The present invention relates to display processors and more particularly to cathode ray tube (CRT) processors for use in a word processing system.

Computer based systems and particularly word processing systems often include a cathode ray tube (CRT) for displaying alphanumeric data and/or graphics. Commercially available displays can be as small as one line or as large as two legal sized pages, side by side on one monitor or screen.

While the size of the display is variable, the information displayed thereon has tended to be of a fixed format. That is, excluding the case of a display adapted for use with graphics (in which every location on the screen is uniquely and directly addressable), only one sized set of characters can be displayed on a screen. This is not to say that displays are limited to one font or type style, but only that all of the characters within the one or more fonts must be displayed as substantially the same size.

A notable exception to this rule is the facility provided by certain manufacturers, including a system described in co-pending U.S. patent application Serial No. 177,322, filed August 12, 1980, for "Circuit for Controlling Information on a Display", to provide exploded sized characters, typically twice the size of normally displayed characters. The assignee of the present invention, for example, refers to this exploded mode of display as ZOOM. Characters in the ZOOM mode are generated by displaying two rows of dots for each original row on the screen. Thus, a duplicate row of dots is displayed below each original row of dots. CRT display, provision is made for 80 characters per line, each of which characters is typically 5x7 dots. In high resolution CRT displays, however, the number of dots forming a matrix for each character can be greater.The format of such high resolution displays can be 8x 12 dots or 8x 15 dots. Of course, if the height of each character is increased, the number of lines on a CRT display must proportionally decrease.

Changing from one dot matrix format to another, however, has proved to be difficult, as witnessed by the fact that no commercial manufacturer has heretofore provided such an option to its customers.

It is desirable to be able to vary the size type which appears on a display of dot matrix characters. In particular, choosing a type format from among two or more sizes is advantageous especially when it can be done easily and inexpensively.

In a partial page CRT display having provision for 80 characters per line, the present invention allows a user to display characters in either of two or more dot matrix formats: 8x 12 or 8x 15, for example. The former dot matrix format allows 24 rows of alphanumeric text to be displayed per page, whereas the latter dot matrix format allows 19 rows of alphanumeric text to be displayed per page. The dot matrix format can be changed from the former to the latter by means of a simple substitution of an oscillating crystal.

In accordance with the present invention, there is provided a display processor having a CRT monitor.

The display processor has a central processing unit (CPU) for controlling data transfer, CRT control means connected to the CPU and to the CRT monitor, and CPU driving means connected to the CPU for operating the CPU at one of a plurality of clock rates.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure lisa schematic block diagram of the display processor in accordance with one embodiment of the present invention; and Figure 2 is a schematic block diagram of the display processor in accordance with another embodiment of the present invention.

The CRT controller edits and formats data from a memory into a video signal suitable for driving a CRT monitor or screen. The structure and operation of the CRT processor of the present invention can best be understood by referring to Figure 1 which contains an Intel Corp. model 8085A-2 microprocessor or central processing unit (CPU) 10 (hereinafter a microprocessor), 64K bytes of dynamic memory 12, supplied, for example, bythe Intel Corp. in a 16Kx1 format as model no.2117-3, and an 8-bit and a 16-bit data address bus 14 and 16, respectively, connected between the microprocessor 10 and the memory 12.

A control bus 18 is also connected to the aforementioned devices 10 and 12 as indicated in the Figure.

To one or more of these internal buses are connected an Intel Corp. 8275 programmable CRT controller 20, a General Instruments Co. model no.

AY-3-1015D serial to parallel universal asynchronous receiver/transmitter (UART) 22, which communicates serially with a keyboard 24 and an interproces sor communication (IPC) interface 26, and a memory controller 28, such as an Intel Corp. model no. 8202 device, which performs a refresh function to the memory 12 and performs an arbitration function between contending devices, as hereinbelow described.

As shown in Figure 2, an Intel Corp. model no.

8237-2 direct memory access (DMA) controller 29 can also be connected to the address buses 14 and 16 and control bus 18. When so connected, the DMA controller 29 refreshes memory 12 once per character line displayed on the screen.

The IPC interface 26 is connected via an IPC bus 30 to other processing units 32 within a word processing system, including a disk processor 34 which in turn can be suitably connected via serial lines to a printing device 36, such as a Ricoh Corp. model RP1600 printer.

The CRT controller 20 is directly connected to a CRT monitor or display screen 38, such as a Motorola Corp. model no. MD3000-140 monitor.

An oscillator 40 is connected to an input port of the microprocessor 10 and is driven by a crystal 42 to operate at a fixed and precisely determined frequency.

In operation, data is transferred from memory 12 to the CRT controller 20 via the microprocessor 10.

Normal processing of the microprocessor 10 is interrupted for each scan line to be transferred to the CRT controller 20.

The CRT controller 20 is programmable. Consequently, the number of lines of alphanumeric information to be displayed on the screen 38, the number of characters to be displayed in a line and the number of scan lines used to display a single row of characters can all be selected.

In the preferred embodiment, one of two standard display formats can be selected by specifying either one of two crystals 42, each having a different frequency. The crystal 42 can be installed at the factory or in the field by service personnel. Naturally the size of the displayed characters can be specified by a user with appropriate structural modifications to locate the crystal for easy access for replacement.

In the preferred embodiment, the crystal oscillator rates used are 35.04 MHz and 35.38 MHz.

The IPC interface 26 is functionally equivalent to the IPC interface shown and described in detail in co-pending U.S. patent application Serial No.

177,319, filed August 12, 1980, for "Communications Systems for a Word Processing System Employing Distributed Processing Circuitry".

The CRT processor forms only part of a single data processing station. The other part of the circuitry is contained on the disk processor 34, which is connected to as many as fourfioppy disk drives, not shown, and to a printer. The disk processor 34 controls disk l/O functions and performs print formatting operations.

To transfer information from the keyboard 24 once one of its keys is depressed, a character corresponding to the depressed key is transmitted across the serial line from the keyboard 24 to the CRT controller 20 via the UART 22 which converts the data from serial form to parallel form. Once the UART 22 receives the character, it signals the microprocessor 10 by raising the interrupt RESTART (RST) 7.5 line on the microprocessor 10. The microprocessor 10 then discontinues processing and interrogates the UART 22. The character is moved to the accumulator of the microprocessor 10. From the accumulator, a keyboard handler program or subroutine residing in the microprocessor 10 transfers that piece of data to a buffer in the memory 12 of the CRT processor.

The character is moved from the UART 22 to the microprocessor 10 but does not pass directly to the CRT controller 20. Information from the keyboard 24 is converted to parallel form by the UART 22 which signals the microprocessor 10 via the INTERRUPT LINE that a character has been received. The microprocessor 10 enters an interrupt handler routine for the UART 22, accepts the character from the UART 22, and then transfers it to memory 12, all by means ofthe internal buses 14, 16 and 18.

once the microprocessor 10 returns from its interrupt handler routine, it enters a program to format the CRT screen 38 and the new character is moved into a position in memory 12 so that it can be displayed on the screen 38. As the CRT controller 20 completes displaying a row of text, it signals the microprocessor 10 and the microprocessor 10 enters another interrupt handler routine, this time for the CRT controller 20, wherein the microprocessor 10 moves a row of data from memory 12 by means of a series of pop/stack instructions into the CRT controller 20.

Two line buffers, one for input and one for output, are provided within the CRT controller 20 and are used in accordance with a program residing in the CRT controller 20. The program may be change either at the factory or in the field by a service representative. Of course, the program and data allocation in memory can be changed to conform to the crystal 42 being used by the user. The specified program resides on a disk which is loaded by the user during system initialization. The input line buffer is filled or loaded with data by the microp rocessor 10 at the current microprocessor rate, determined by the frequency of the crystal 42. The output line buffer circulates once for each CRT scan line. When the CRT controller 20 completes displaying a line of text, it outputs a blank line to the CRT monitor 38.During the blank line transfer, information from the input line buffer is transferred to the output line buffer.

When a printer operation is to take place, data from the CRT processor memory 12 is transferred to the disk processor memory 34 via the IPC interface 26 and IPC bus 30. This data transfer is shown and described in detail in co-pending U.S. patent application Serial No. 177,319, as hereinabove referenced.

The CRT processor establishes a master/slave relationship with the disk processor 34, and then transfers information to the disk processor 34 one byte at a time. The information, once received by the disk processor 34, is changed by programs within the disk processor 34 to a format acceptable to the printer 36.

When the CRT processor requires information from a disk, it signals the disk processor 34 by again establishing a master/slave relationship across the IPC interface 26 and IPC bus 30. The CRT processor transfers a data request to the disk processor 34. The disk processor 34 then accesses the data from the disk and transfers it in its own memory. The disk processor 34 then signals the CRT processor that it has received the data it requested. The data is then transferred once again across the IPC interface 26 and IPC bus 30 one byte at a time. All of these transfers are performed under control of either the disk processor 34 or the CRT processor.

While the IPC interface 26 operates generally as shown and described in co-pending U.S. patent application Serial No. 177,319, as hereinabove referenced, for each byte that is transferred, the slave microprocessor of the present invention is placed into a hold state. In the system disclosed in the aforementioned patent application, a memory interleaving scheme was constructed to utilize the full bandwidth of the memory. That is not required in the present invention. Circuitry is simplified such that when data is transferred to the slave microprocessor, it is placed in the hold state for the duration of the transfer for each byte that is transferred. The use of this procedure reduces the number of components required to enable master/slave operations.

The foregoing embodiment has been presented for the purpose of illustration and should not be taken to limit the scope of the present invention. It will be apparent that such embodiment is capable of many variations and modifications which are likewise to be included within the scope of the present invention as set forth in the appended claims.

Claims (22)

1. A display processor for use in a word processing system having a monitor (38) for displaying alphanumeric data at one of a plurality of sizes, said display processor comprising: a) a central processing unit (CPU) (10) for controlling data transfer adapted to operate at a plurality of discrete operating frequencies; b) control means (20) operatively connected to said CPU (10), said control means (20) also being operatively connected to the monitor (38) for transferring data thereto; and c) means (40) operatively connected to said CPU (10) for driving said CPU (10) at one of said plurality of discrete operating frequencies, which discrete operating frequencies correspond to the sizes of alphanumeric data to be displayed.

2. A display processor in accordance with claim 1, wherein said driving means includes an oscillator (40) and an oscillating crystal (42) operatively connected thereto.

3. A display processor in accordance with claim 1 or 2, further comprising: d) memory means (12) operatively connected to said CPU (10) and operatively connected to said control means (20) for storing data representative of said alphanumeric data to be displayed on said monitor (38).

4. A display processor in accordance with claim 3, wherein said memory means (12) has memory refresh means (28) associated therewith for maintaining the data therein.

5. A display processor in accordance with claim 3 or 4, further comprising transfer means (14, 16, 18) operatively connected to said CPU (10), to said control means (20), and to said memory means (12) for transferring data thereamong.

6. A display processor in accordance with claim 5, wherein said transfer means is a communications bus network comprising a data bus (14), an address bus (16), and a control bus (18).

7. A display processor in accordance with any one of claims 1 to 6 further comprising: e) means (26, 30) for interfacing an additional processor (32, 34) for handling data, said interfacing means being operatively connected to said CPU (10).

8. A display processor in accordance with claim 7 wherein said interfacing means (26, 30) is an interprocessor communications channel for establishing bidirectional data communications between said display processor and said additional processor (32, 34).

9. A display processor in accordance with claim 8 wherein said additional processor (34) is suitable for controlling a disc drive.

10. A display processor in accordance with any one of claims 1 to 9, further comprising: f) a universal asynchronous receiver/transmitter (UART) (22) operatively connected to said CPU (10) for establishing data communications between said CPU (10) and input means (24) adapted for use therewith.

11. A display processor in accordance with any one of claims 5 to 10 wherein said monitor (38) is a cathode ray tube.

12. A display processor in accordance with claim 10, or claim 11 when dependent upon claim 10, wherein said input means (24) is a keyboard.

13. A display processor for use in a word processing system having a monitor (38) for displaying alphanumeric data at one of a plurality of sizes, said display processor comprising: a) a central processing unit (CPU) (10) for controlling data transfer adapted to operate at a plurality of discrete operating frequencies; b) control means (20) operatively connected to said CPU (10), said control means (20) also being operatively connected to the monitor (38) for trans- ferring data thereto; c) means (40) operatively connected to said CPU (10) for driving said CPU (10) at one of said plurality of discrete operating frequencies, which discrete operating frequencies correspond to the sizes of alphanumeric data to be displayed; and d) said driving means including an osillator (40) operatively connected thereto and an oscillating crystal (42), said oscillating crystal (42) being detachably and operatively connected thereto.

14. In a processor for use in a word processing system having display means (38) displaying alphanumeric data and processing means (10) for processing data, the improvement comprising a frequency source (40, 42) operatively connected to said processing means (10) for driving said processing means (10) at a predetermined rate such that the size of the alphanumeric data displayed on said display (38) is dependent thereon and proportional thereto.

15. A processor in accordance with claim 14 wherein said frequency source (42) is replaceable so that the size of the alphanumeric data displayed on said display can be increased.

16. A processor in accordance with claim 15 wherein said frequency source includes an oscillator (14) and an oscillating crystal (42) operatively connected thereto.

17. A processor in accordance with claim 14, 15 or 16 further comprising input means (24, 22) operatively connected to said processing means (10) for entering data thereto.

18. A processor in accordance with any one of claims 14to 17 wherein said display means (38) is a cathode ray tube.

19. A processor in accordance with claim 2 or any one of claims 3 to 12 as dependent upon claim 2, or claim 16 or claim 17 or 18 as dependent upon claim 16 wherein said crystal (42) is adapted to operate at 35.04 MHz.

20. A processor in accordance with claim 2 or any one of claims 3 to 12 as dependent upon claim 2, or claim 16 or claim 17 or 18 as dependent upon claim 16, wherein said crystal (42) is adapted to operate at 35.38 MHz.

21. A display processor for use in a work proces sing system having a monitor (38) for displaying alphanumeric data at one of a plurality of sizes, said display processor comprising: a) a central processing unit (CPU) (10) for controlling data transfer adapted to operate at a plurality of discrete operating frequencies; b) control means (20) operatively connected to said CPU (10), said control means (20) also being operatively connected to the monitor (38) for transferring data thereto: and c) means (40) operatively connected to said CPU for driving said CPU (10) at a predetermined rate such that the size of the alphanumeric data displayed on said monitor (38) is dependent thereon and proportional thereto.

22. A display processor for use in a word processing system substantially as hereinbefore described with reference to and as illustrated in Figure 1 or Figure 2 of the accompanying drawings.

22. A display processor for use in a word processing system substantially as hereinbefore described with reference to and as illustrated in Figure 1 or Figure 2 of the accompanying drawings.

New claims filed on 28 June 1982.

Superseded claims 1 to 22.

New or amended claims:

1. A display processor for use in a word processing system having a monitorfordisplaying alphanumeric data at one of a plurality of sizes, said display processor comprising: a) a central processing unit (CPU) for controlling data transfer adapted to operate at a plurality of discrete operating frequencies; b) control means operatively connected to said CPU, said control means also being operatively connected to the monitor for transferring data thereto; and c) means operatively connected to said CPU for driving said CPU at one of said plurality of discrete operating frequencies, which discrete operating frequencies correspond to the sizes of alphanumeric data to be displayed.

2. A display processor in accordance with claim 1, wherein said driving means includes an oscillator and an oscillating crystal operatively connected thereto.

3. A display processor in accordance with claim 1 or 2, further comprising: d) memory means operatively connected to said CPU and operatively connected to said control means for storing data representative of said alphanumeric data to be displayed on said monitor.

4. A display processor in accordance with claim 3, wherein said memory means has memory refresh means associated therewith for maintaining the data therein.

5. A display processor in accordance with claim 3 or 4, further comprising transfer means operatively connected to said CPU, to said control means, and to said memory means for transferring data thereamong.

6. A display processor in accordance with claim 5, wherein said transfer means is a communications bus network comprising a data bus, an address bus, and a control bus.

7. A display processor in accordance with any one of claims 1 to 6 further comprising: e) means for interfacing an additional processor for handling data, said interfacing means being operatively connected to said CPU.

8. A display processor in accordance with claim 7 wherein said interfacing means is an interprocessor communications channel for establishing bidirectional data communications between said display processor and said additional processor.

9. A display processor in accordance with claim 8 wherein said additional processor is suitable for controlling a disc drive.

10. A display processor in accordance with any one of claims 1 to 9, further comprising: f) a universal asynchronous receiver/transmitter (UART) operatively connected to said CPU for establishing data communications between said CPU and input means adapted for use therewith.

11. A display processor in accordance with any one of claims 5 to 10 wherein said monitor is a cathode ray tube.

12. A display processor in accordance with claim 10, or claim 11 when dependent upon claim 10, wherein said input means is a keyboard.

13. A display processor for use in a word processing system having a monitorfordisplaying alphanumeric data at one of a plurality of sizes, said display processor comprising: a) a central processing unit (CPU) for controlling data transfer adapted to operate at a plurality of discrete operating frequencies; b) control means operatively connected to said CPU, said control means also being operatively connected to the monitor for transferring data thereto; c) means operatively connected to said CPU for driving said CPU at one of said plurality of discrete operating frequencies, which discrete operating frequencies correspond to the sizes of alphanumeric data to be displayed; and d) said driving means including an oscillator operatively connected thereto and an oscillating crystal, said oscillating crystal being detachably and operatively connected thereto.

14. In a processor for use in a word processing system having display means displaying alphanumeric data and processing means for processing data, the improvement comprising a frequency source operatively connected to said processing means for driving said processing means at a predetermined rate such that the size of the alphanumeric data displayed on said display is dependent thereon and proportional thereto.

15. A processor in accordance with claim 14 wherein said frequency source is replaceable so that the size of the alphanumeric data displayed on said display can be increased.

16. A processor in accordance with claim 15 wherein said frequency source includes an oscillator and on oscillating crystal operatively connected thereto.

17. A processor in accordance with claim 14,15 or 16 further comprising input means operatively connected to said processing means for entering data thereto.

18. A processor in accordance with any one of claims 14 to 17 wherein said display means is a cathode ray tube.

19. A processor in accordance with claim 2 or any one of claims 3 to 12 as dependent upon claim 2, or claim 16 or claim 17 or 18 as dependent upon claim 16 wherein said crystal is adapted to operate at 35.04 MHz.

20. A processor in accordance with claim 2 or any one of claims 3 to 12 as dependent upon claim 2, or claim 16 or claim 17 or 18 as dependent upon claim 16, wherein said crystal is adapted to operate at 35.38 MHz.

21. A display processor for use in a work processing system having a monitor for displaying alphanumeric data at one of a plurality of sizes, said display processor comprising: a) a central processing unit (CPU) for controlling data transfer adapted to operate at a plurality of discrete operating frequencies; b) control means operatively connected to said CPU, said control means also being operatively connected to the monitor for transferring data thereto; and c) means operatively connected to said CPU for driving said CPU at a predetermined rate such that the size of the alphanumeric data displayed on said monitor is dependent thereon and proportional thereto.