CN106024899A - Semiconductor field effect transistor and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor field effect transistor and a manufacturing method thereof. The method comprises: forming a mask layer on a first partial region on a semiconductor substrate; using the mask layer as a mask to sequentially form a well region, a source The pole region and a local silicon oxide layer are grown; the mask layer is removed; and a gate oxide layer and a polysilicon layer are sequentially formed to obtain a semiconductor field effect transistor. The invention effectively solves the technical problem that the turn-on delay time of the VDMOS manufactured by the existing gate-oxide process is relatively long, and then reduces the turn-on delay time of the semiconductor field effect transistor manufactured by the gate-oxide process to effectively improve the gate-oxide process. quality of VDMOS.

Description

A kind of semiconductor field effect transistor and its manufacturing method

technical field

The invention relates to the field of semiconductors, in particular to a semiconductor field effect transistor and a manufacturing method thereof.

Background technique

In the field of power semiconductors, a vertical MOSFET formed by a vertical double diffusion process is called a VDMOSFET, or VDMOS for short. Because VDMOS has the characteristics of fast switching speed, high input impedance and good frequency characteristics, it has been widely used.

Conventional VDMOS devices apply the pre-gate oxide process, that is, the gate oxide process and polycrystalline formation process are completed before the well and source region implantation and diffusion processes. Under this pre-gate oxide process, the formation of polysilicon, well implantation, and source implantation can be self-aligned, and the gate-source overlap capacitance of the manufactured VDMOS device is small, so the turn-on delay time is short.

However, in some special fields, VDMOS requires high reliability of gate oxide, which requires gate oxide process and polysilicon to be completed after well process, that is, gate oxide last process. However, the order of the last gate oxide process is reversed. Polysilicon formation, well implantation, and source implantation each require one photolithography. Therefore, polysilicon formation, well implantation, and source implantation processes are usually not self-aligned. In order to ensure that the channel can be normally turned on under the premise of self-alignment, in the manufacture of post-gate oxide process VDMOS, the polysilicon boundary, the boundary of the well region, and the boundary of the source region usually ensure a certain overlapping length. The stack length is related to the registration accuracy between the two processes. Because the existing process equipment is difficult to guarantee the registration accuracy, the turn-on delay time of the VDMOS of the existing gate oxide last process will be relatively long, which affects the performance of the VDMOS.

Contents of the invention

The embodiment of the present invention solves the technical problem of relatively long turn-on delay time of VDMOS in the existing gate oxide last process by providing a semiconductor field effect transistor and a manufacturing method thereof.

In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a mask layer on a first partial region on a semiconductor substrate; forming a well region, a source region and growing a local silicon oxide layer; removing the mask layer; forming a gate oxide layer and a polysilicon layer in sequence to obtain the semiconductor field effect transistor.

Preferably, the sequentially forming the gate oxide layer and the polysilicon layer includes: growing the gate oxide layer on the first partial region with a thickness smaller than that of the local silicon oxide layer; The polysilicon layer is grown on a part of the local silicon oxide layer close to the gate oxide layer.

Preferably, the semiconductor substrate and the source region are P-type doped, and the well region is N-type doped; or the semiconductor substrate and the source region are N-type doped, and the The well region is P-type doped.

Preferably, forming the mask layer on the first partial region on the semiconductor substrate includes: depositing silicon nitride on the semiconductor substrate to form a silicon nitride film; etching the silicon nitride film silicon nitride except for the first partial region to form the mask layer.

Preferably, using the mask layer as a mask to sequentially form a well region, a source region and a local silicon oxide layer in the semiconductor substrate includes: using the mask layer on the semiconductor substrate performing well implantation and well advancement for masking to form the well region; forming a photoresist layer in a second partial region on the well region, wherein the second partial region is separated from the first partial region; A source region is formed in the well region by using the mask layer and the photoresist layer as a mask; removing the photoresist layer; and growing a local silicon oxide layer by using the mask layer as a mask.

In a second aspect, an embodiment of the present invention provides a semiconductor field effect transistor, comprising: a semiconductor substrate, a well region, a local silicon oxide layer, a local silicon oxide layer, a gate oxide layer, and a polysilicon layer; the well region is formed on the In the semiconductor substrate, the source region is formed in the well region, and the local silicon oxide layer is grown in the semiconductor substrate at a position aligned with the source region, wherein the local The thickness of the silicon oxide layer is greater than the thickness of the gate oxide layer, the gate oxide layer is grown between adjacent source regions in the semiconductor substrate, and the polysilicon layer is formed on the gate oxide layer and a part of the local silicon oxide layer close to the gate oxide layer.

Preferably, the semiconductor substrate and the source region are P-type doped, and the well region is N-type doped; or the semiconductor substrate and the source region are N-type doped, and the The well region is P-type doped.

One or more technical solutions provided by the embodiments of the present invention at least achieve the following technical effects or advantages:

Because the embodiment of the present invention uses the same mask layer on the semiconductor substrate as a mask to form a well region and a source region and grow a local silicon oxide layer during the VDMOS manufacturing of the gate oxide last process, so that the local silicon oxide layer and the well Region and source region are self-aligned, because the oxidation of the first part of the region will be restricted by the mask layer during oxidation, so that a local silicon oxide layer can be grown, and the growth of the local silicon oxide layer can increase the oxide layer in the gate-source overlapping region Thickness, to effectively reduce the gate-source overlap capacitance, so as to solve the technical problem that the turn-on delay time of the VDMOS manufactured by the gate oxide last process will be relatively long, thereby reducing the semiconductor field effect transistor manufactured by the gate oxide last process. Turn-on delay time to effectively improve the quality of VDMOS in gate oxide last process.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is the structural representation of semiconductor field effect transistor in the embodiment of the present invention;

Fig. 2 is the flowchart of the manufacturing method of semiconductor field effect transistor in the embodiment of the present invention;

3 to 7 are step-by-step schematic diagrams of the semiconductor field effect transistor in the embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Embodiment one:

An embodiment of the present invention provides a method for manufacturing a semiconductor field effect transistor. Referring to FIGS. 1 to 7 , the method for manufacturing a semiconductor field effect transistor provided by the embodiment of the present invention includes the following steps:

S101 , forming a mask layer 7 on a first partial region on the semiconductor substrate 1 .

Specifically, the material of the mask layer 7 can be silicon nitride (Si ₃ N ₄ ), or can be replaced by SiO ₂ , or can be replaced by non-Si materials such as film and metal chromium that can withstand high temperature processes.

Taking the material of the mask layer 7 as silicon nitride as an example: deposit silicon nitride on the semiconductor substrate 1 to form a silicon nitride film; etch the silicon nitride except the first part of the silicon nitride film to form A mask layer 7 is formed.

S102 , using the mask layer 7 as a mask to sequentially form a well region 2 , a source region 3 and grow a local silicon oxide layer 4 in the semiconductor substrate 1 .

Specifically, S102 includes: step 1, performing well implantation and well advancement on the semiconductor substrate 1 using the mask layer 7 as a mask, so as to form a well region 2 . Step 2, forming a photoresist layer 8 in a second partial area on the well region 2, wherein the second partial area is separated from the first partial area. Specifically, the photoresist layer 8 is after the photoresist film is coated on the semiconductor substrate 1, and the photoresist part on the photoresist film except the second part area is photoetched, thereby forming the photoresist layer 8. Step 3, using the mask layer 7 and the photoresist layer 8 as a mask to form the source region 3 in the well region 2 . Step 4, removing the photoresist layer 8 . Step 5, using the mask layer 7 as a mask to grow a local silicon oxide layer 4 .

S103 , removing the mask layer 7 .

S104, sequentially forming a gate oxide layer 5 and a polysilicon layer 6 to obtain a semiconductor field effect transistor.

Specifically, a gate oxide layer 5 with a thickness smaller than that of the local silicon oxide layer 4 is grown on the first partial region. A polysilicon layer 6 is grown on the gate oxide layer 5 and on a part of the local silicon oxide layer 4 close to the gate oxide layer 5 . In the specific implementation process, the formation process of the gate oxide layer 5 and the formation process of the polysilicon layer 6 refer to the prior art, and for the sake of brevity of the description, details are not repeated herein.

Specifically, the semiconductor substrate 1 and the source region 3 are P-type doped, and the well region 2 is N-type doped, then the semiconductor field effect transistor in the embodiment of the present invention is specifically an N-channel VDMOS transistor; the semiconductor substrate 1 and the The source region 3 is N-type doped, and the well region 2 is P-type doped, so the semiconductor field effect transistor provided by the embodiment of the present invention is specifically a P-channel VDMOS transistor.

The manufacturing process of the semiconductor field effect transistor after the polysilicon layer 6 is formed can refer to the prior art, and for the sake of brevity of the description, details are not repeated herein.

Referring to FIGS. 3 to 7, the manufacturing method of the semiconductor field effect transistor provided by the embodiment of the present invention is illustrated by taking the P-channel VDMOS transistor as an example:

As shown in FIG. 3, silicon nitride is deposited on an N-type doped semiconductor substrate 1 to form a silicon nitride film, and the silicon nitride on the region other than the first partial region of the silicon nitride film is etched to form a silicon nitride film. A mask layer 7 is formed as a mask for the P-well implantation.

As shown in FIG. 4 , the P-well implantation is performed in the N-type doped semiconductor substrate 1 with the mask layer 7 as a mask, and the P-well is advanced to reach the design target, so as to form the P-well region 2 .

As shown in FIG. 5 , a photoresist layer 8 is formed on the second partial region on the P well region 2 , wherein the second partial region is separated from the first partial region. Next, an N-type source region 3 is formed in the P-type well region 2 by using the mask layer 7 and the photoresist layer 8 as a mask.

As shown in FIG. 6 , the photoresist layer 8 is removed after the N-type source region 3 is formed. After removing the photoresist layer 8, a partial silicon oxide layer 4 is grown using the mask layer 7 as a mask. Thereby the oxidation of the first partial area is limited by the mask layer 7, so that the oxidation of the exposed area of the N-type doped semiconductor substrate 1 will be greater than the oxidation under the mask layer 7, thereby achieving the N-type doped semiconductor substrate. 1 LOCOS (Local Oxidation of Silicon), to form a local silicon oxide layer 4, the formed local silicon oxide layer 4 can increase the thickness of the oxide layer in the gate-source overlap area, thereby reducing the gate-source overlap capacitance , to optimize the turn-on delay time of the semiconductor field effect transistor.

Referring to FIG. 7 , the mask layer 7 is removed and the gate oxide layer 5 and the polysilicon layer 6 are sequentially formed after removing the mask layer 7 .

Specifically, after the mask layer 7 is removed, a gate oxide layer 5 with a thickness smaller than that of the local silicon oxide layer 4 is grown on the first partial region. A polysilicon layer 6 is grown on the gate oxide layer 5 and on a part of the local silicon oxide layer 4 close to the gate oxide layer 5 . The polysilicon layer 6 and the borders of the P well region 2 and the N-type source region 3 are guaranteed to have a certain overlapping length.

Other semiconductor field effect transistor manufacturing processes behind the polysilicon layer 6 can refer to the prior art. The semiconductor field effect transistors formed by manufacturing are shown in Figure 1. The manufacturing process is described.

The method for manufacturing a semiconductor field effect transistor provided by an embodiment of the present invention is described below by taking an N-channel VDMOS transistor as an example (not shown):

After depositing silicon nitride on the P-type doped semiconductor substrate to form a silicon nitride film, etching the silicon nitride except for the first partial region of the silicon nitride film to form a mask layer.

N-well implantation and N-well advancement are performed in the P-type doped semiconductor substrate using the mask layer as a mask to form an N-well region. A photoresist layer is formed on a second partial region on the N well region, and the second partial region is separated from the first partial region. Next, a P-type source region is formed in the N-type well region by using the mask layer and the photoresist layer as a mask. The photoresist layer is removed after forming the P-type source region. After removing the photoresist layer, a local silicon oxide layer is grown using the mask layer as a mask. Because the oxidation of the first part of the region will be limited by the mask layer, the oxidation of the exposed area of the P-type doped semiconductor substrate will be greater than the oxidation under the mask layer, thereby reaching the LOCOS ( local silicon oxidation), the formation of local silicon oxide layer can increase the thickness of the oxide layer in the gate-source overlap region, thereby reducing the gate-source overlap capacitance, so as to optimize the turn-on delay time of the semiconductor field effect transistor.

The mask layer is removed and a gate oxide layer and a polysilicon layer are sequentially formed after removing the mask layer. Specifically, after the mask layer is removed, a gate oxide layer with a thickness smaller than that of the local silicon oxide layer is grown on the first partial region. A polysilicon layer is grown on the gate oxide layer and on a part of the local silicon oxide layer close to the gate oxide layer. Therefore, a certain overlap length between the polysilicon layer and the boundary of the N-well region and the P-type source region is ensured. The manufacturing process of the semiconductor field effect transistor behind the polysilicon layer can refer to the prior art, and for the sake of brevity of the description, details are not described herein.

Embodiment two:

Based on the same inventive concept, an embodiment of the present invention provides a semiconductor field effect transistor. Referring to FIG. 1 and FIG. 3 to FIG. 7, the semiconductor field effect transistor provided by the embodiment of the present invention includes: a semiconductor substrate 1, a well region 2, a local silicon oxide layer 3, a local silicon oxide layer 4, a gate oxide layer 5 and Polysilicon layer 6. A well region 2 is formed in the semiconductor substrate 1; a source region 3 is formed in the well region 2; a local silicon oxide layer 4 is grown in the semiconductor substrate 1 at a position aligned with the source region 3; a gate oxide layer 5 is grown Between the adjacent source regions 3 in the semiconductor substrate 1 ; the polysilicon layer 6 is formed on the gate oxide layer 5 and a part of the local silicon oxide layer 5 close to the gate oxide layer 5 .

Specifically, the semiconductor substrate 1 and the source region 3 are P-type doped, and the well region 2 is N-type doped, then the semiconductor field effect transistor in the embodiment of the present invention is specifically an N-channel VDMOS transistor; the semiconductor substrate 1 and the The source region 3 is N-type doped, and the well region 2 is P-type doped, so the semiconductor field effect transistor provided by the embodiment of the present invention is specifically a P-channel VDMOS transistor.

One or more technical solutions provided by the embodiments of the present invention at least achieve the following technical effects or advantages:

Because the embodiment of the present invention uses the same mask layer on the semiconductor substrate as a mask to form a well region and a source region and grow a local silicon oxide layer during the VDMOS manufacturing of the gate oxide last process, so that the local silicon oxide layer and the well Region and source region are self-aligned, because the oxidation of the first part of the region will be restricted by the mask layer during oxidation, so that a local silicon oxide layer can be grown, and the growth of the local silicon oxide layer can increase the oxide layer in the gate-source overlapping region Thickness, to effectively reduce the gate-source overlap capacitance, so as to solve the technical problem that the turn-on delay time of the VDMOS manufactured by the gate oxide last process will be relatively long, thereby reducing the semiconductor field effect transistor manufactured by the gate oxide last process. Turn-on delay time to effectively improve the quality of VDMOS in gate oxide last process.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (7)

1. a semiconductor field effect transistor manufacture method, it is characterised in that including:

Part I region on a semiconductor substrate forms mask layer；

In described Semiconductor substrate, well region, source area and grow is formed successively with described mask layer for sheltering Localized oxidation of silicon layer；

Remove described mask layer；

Sequentially form grid oxide layer and polysilicon layer, to obtain described semiconductor field effect transistor.

2. semiconductor field effect transistor manufacture method as claimed in claim 1, it is characterised in that institute State and sequentially form grid oxide layer and polysilicon layer includes:

Described Part I region grows thickness less than described in the thickness of described localized oxidation of silicon layer Grid oxide layer；

Life on the subregion of described grid oxide layer on described grid oxide layer and on described localized oxidation of silicon layer Grow described polysilicon layer.

3. semiconductor field effect transistor manufacture method as claimed in claim 1 or 2, it is characterised in that:

Described Semiconductor substrate and described source area are p-type doping, and described well region is n-type doping；Or

Described Semiconductor substrate and described source area are n-type doping, and described well region is p-type doping.

4. semiconductor field effect transistor manufacture method as claimed in claim 1, it is characterised in that institute State Part I region on a semiconductor substrate and form mask layer, including:

Deposit silicon nitride on the semiconductor substrate, to form silicon nitride film；

Etch the silicon nitride in addition to described Part I region of described silicon nitride film, to form described mask Layer.

5. semiconductor field effect transistor manufacture method as claimed in claim 1, it is characterised in that institute State with described mask layer for sheltering formation well region, source area and growth striking out in described Semiconductor substrate successively Portion's silicon oxide layer, including:

On the semiconductor substrate with described mask layer for shelter carry out trap inject and trap advance, to be formed State well region；

Part II region on described well region forms photoresist layer, wherein, described Part II region with Described Part I region is separated by；

With described mask layer and described photoresist layer for being sequestered in described well region formation source area；

Remove described photoresist layer；

Localized oxidation of silicon layer is grown with described mask layer for sheltering.

6. a semiconductor field effect transistor, it is characterised in that including: Semiconductor substrate, well region, Localized oxidation of silicon layer, localized oxidation of silicon layer, grid oxide layer, polysilicon layer；

Described well region is formed in described Semiconductor substrate, and described source area is formed in described well region, institute State the localized oxidation of silicon layer growth position being directed at described source area in described Semiconductor substrate, wherein, The thickness of described localized oxidation of silicon layer is more than the thickness of described grid oxide layer, and described grid oxide layer is grown in described partly leading Between adjacent described source area in body substrate, described polysilicon layer is formed on described grid oxide layer and described office On the subregion of the close described grid oxide layer on portion's silicon oxide layer.

7. semiconductor field effect transistor as claimed in claim 6, it is characterised in that:

Described Semiconductor substrate and described source area are p-type doping, and described well region is n-type doping；Or

Described Semiconductor substrate and described source area are n-type doping, and described well region is p-type doping.