CN102544072A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device with a LOCOS separation structure and a method for manufacturing the semiconductor device, which suppress the generation of leakage current between a source region and a drain region. This semiconductor device has: a source region and a drain region of the first conductivity type, which are formed separately from each other in a part of the upper part of the semiconductor substrate; on the substrate; a LOCOS insulating film, which is arranged continuously with the gate insulating film on the semiconductor substrate, and whose film thickness is thicker than the gate insulating film; It is arranged continuously on the surrounding LOCOS insulating film, and the gate threshold voltage at the end of the gate electrode in the channel width direction, that is, the peripheral region is higher than that in the central region of the gate electrode.

Description

Semiconductor device and method for manufacturing semiconductor device

technical field

The present invention relates to a semiconductor device having a MOS transistor having a LOCOS separation structure and a method of manufacturing the semiconductor device.

Background technique

In order to realize a high withstand voltage MOS transistor, a drain region with a high impurity concentration adjacent to a drain electrode is used, and a region (LDD region) having a lower impurity concentration than the drain region is formed. By forming the LDD region, the electric field near the drain region can be relaxed. In addition, a method has been studied in which a field insulating film (hereinafter referred to as "LOCOS insulating film") thicker than the gate insulating film is formed using the LOCOS method to relax the electric field between the gate electrode and the drain (for example, refer to Patent Document 1.). Hereinafter, the structure having the LOCOS insulating film formed thicker than the gate insulating film is referred to as "LOCOS separation structure".

[Patent Document 1] Japanese Patent Laid-Open No. 2010-206163

In the MOS transistor of the LOCOS split structure, the following phenomenon may occur: in the region of the gate/source voltage lower than the designed gate threshold voltage, the drain flows between the source region and the drain region. current.

Contents of the invention

An object of the present invention is to provide a semiconductor device with a LOCOS split structure and a method of manufacturing the semiconductor device, in which leakage current between a source region and a drain region is suppressed.

According to one aspect of the present invention, there is provided a semiconductor device including: (A) a semiconductor substrate; (B) a source region and a drain region of the first conductivity type formed separately from each other on a part of the upper part of the semiconductor substrate ; (C) a gate insulating film, which includes a region sandwiched by a source region and a drain region, disposed on the semiconductor substrate; (D) a LOCOS insulating film, which surrounds a channel region formed between the source region and the drain region and a gate insulating film thicker than the gate insulating film; and (E) a gate electrode made of a polysilicon film in a region sandwiched by a source region and a drain region , continuously arranged across the gate insulating film and the LOCOS insulating film around the gate insulating film, the gate threshold voltage in the peripheral region of the gate electrode is higher than that in the central region of the gate electrode, and the gate threshold voltage in the peripheral region of the gate electrode is higher than that in the central region of the gate electrode. is the end of the gate electrode in the channel width direction.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including the following steps: (A) forming a LOCOS insulating film on a part of the surface of a semiconductor substrate by the LOCOS method; (B) forming a LOCOS insulating film after forming the LOCOS In the remaining region of the insulating film region, a gate insulating film having a film thickness thinner than the LOCOS insulating film is formed on the surface of the semiconductor substrate in a continuous manner with the LOCOS insulating film; (C) across the gate insulating film and the gate insulating film. A gate electrode made of polysilicon film is continuously formed on the LOCOS insulating film around the insulating film; (D) a source region and a drain region of the first conductivity type are formed on the upper part of the semiconductor substrate with the region where the gate electrode is formed; and (E) making the gate threshold voltage in the peripheral region of the gate electrode higher than the gate threshold voltage in the central region of the gate electrode, and extending from the boundary between the gate insulating film and the LOCOS insulating film to the central region of the gate electrode by a certain distance. A conductive impurity is implanted into the gate electrode on the gate insulating film at a distance of 1000 Å, and the peripheral region of the gate electrode is an end portion of the gate electrode in the channel width direction.

According to the present invention, it is possible to provide a semiconductor device with a LOCOS split structure and a method of manufacturing the semiconductor device, in which the generation of leakage current between the source region and the drain region is suppressed.

Description of drawings

FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.

2 is a schematic plan view showing the structure of the semiconductor device according to the first embodiment of the present invention.

Fig. 3 is a sectional view along the III-III direction of Fig. 2 .

4 is a graph showing current-voltage characteristics of the semiconductor device according to the first embodiment of the present invention and a comparative example.

FIG. 5 is a cross-sectional view (Part 1) illustrating the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

6 is a process sectional view (Part 2) for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

7 is a step sectional view (Part 3 ) for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

8 is a step sectional view (Part 4 ) for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

9 is a step sectional view (Part 5 ) for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

10 is a step sectional view (Part 6 ) for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

11 is a cross-sectional view (part 7 ) for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

12 is a step sectional view (part 8) for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

13 is a schematic cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

14 is a schematic plan view showing the structure of a semiconductor device according to a second embodiment of the present invention.

Fig. 15 is a sectional view taken along the XV-XV direction of Fig. 14 .

16 is a schematic plan view showing the structure of a semiconductor device according to a modified example of the second embodiment of the present invention.

FIG. 17 is a cross-sectional view (Part 1) illustrating the steps of the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

18 is a process sectional view (Part 2 ) for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view (Part 3 ) for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

Symbol Description

1...semiconductor device; 10...semiconductor substrate; 11...silicon substrate; 12...epitaxial layer; 13...well region; 20...source region; 21...low concentration source region; 22...high concentration source region; 30...drain region 31...low-concentration drain region; 32...high-concentration drain region; 40...gate insulating film; 50...gate electrode; 51...side wall; 60...LOCOS insulating film.

Detailed ways

Next, first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar symbols are attached to the same or similar parts. However, the drawings are schematic views, and it should be noted that the relationship between the thickness and the planar size, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, the specific thickness and size should be judged with reference to the following description. In addition, it is needless to say that the drawings also include parts in which the relationship and ratio of dimensions are different from each other.

In addition, the first and second embodiments shown below are examples of devices and methods for realizing the technical idea of the present invention. In the embodiments of the present invention, the materials, shapes, structures, The arrangement and the like are not limited to those described below. Various modifications can be made to the embodiments of the present invention within the scope of the claims.

(first embodiment)

1 to 3 show a semiconductor device 1 according to a first embodiment of the present invention. 1 is a cross-sectional view taken along the line I-I in FIG. 2 , showing a cross-sectional surface in a channel region along the gate width direction of the semiconductor device 1 . 3 is a cross-sectional view taken along the line III-III in FIG. 2 , showing a cross-section of the central region of the gate electrode 50 along the gate length direction of the semiconductor device 1 . In the top view of FIG. 2 , the gate insulating film 40 is omitted.

As shown in FIGS. 1 to 3 , the semiconductor device 1 has: a semiconductor substrate 10; a source region 20 and a drain region 30 of the first conductivity type formed separately from each other on a part of the upper part of the semiconductor substrate 10; The gate insulating film 40 disposed on the semiconductor substrate 10 in the region sandwiched by the region 20 and the drain region 30; the LOCOS insulating film 60 whose film thickness is thicker than the gate insulating film 40; A gate electrode 50 made of a polysilicon film of the first conductivity type is continuously arranged across the gate insulating film 40 and the LOCOS insulating film 60 around the gate insulating film 40 in the region of the gate insulating film 40 . The LOCOS insulating film 60 surrounds the channel region formed between the source region 20 and the drain region 30 , and is arranged continuously with the gate insulating film 40 on the semiconductor substrate 10 . In addition, the first conductivity type and the second conductivity type are mutually opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and the semiconductor device 1 is an n-channel MOS transistor. Also, if the first conductivity type is the p-type, the second conductivity type is the n-type, and the semiconductor device 1 is a p-channel MOS transistor.

The semiconductor device 1 is a MOS transistor in which the gate threshold voltage in the peripheral region S at the end of the gate electrode 50 in the channel width direction is higher than that in the central region of the gate electrode 50 . In addition, a region other than the peripheral region S is defined as a central region of the gate electrode 50 . Here, the gate threshold voltage is a voltage applied between the gate electrode 50 and the source region 20 required to turn on the semiconductor device 1 . In FIG. 1 and FIG. 2 , the peripheral region S of the gate electrode 50 is surrounded by thick lines (the same applies hereinafter). The peripheral region S includes a region where the distance w is from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 to the center region toward the gate electrode 50 and the gate electrode 50 disposed on the gate insulating film 40 area. In addition, in FIG. 2 , the end portion of the LOCOS insulating film 60 below the gate electrode 50 is indicated by a dotted line.

In the semiconductor device 1 , although details will be described later, the first conductor formed as the peripheral region S of the gate electrode 50 has a lower impurity concentration than the central region of the gate electrode 50 .

As shown in FIGS. 1 to 3 , the semiconductor device 1 has a LOCOS separation structure having a LOCOS insulating film 60 . Since the LOCOS insulating film 60 is formed by the LOCOS method, the lower portion of the LOCOS insulating film 60 is buried in a part of the upper surface of the semiconductor substrate 10 .

In addition, as shown in FIG. 1 , both ends of the gate electrode 50 in the gate width direction are arranged on the LOCOS insulating film 60 . In addition, side walls 51 are formed in contact with side surfaces of the gate electrode 50 .

The source region 20 of the semiconductor device 1 has a low-concentration source region 21 of the first conductivity type formed in a region close to the gate electrode 50 and a high-concentration source region having an impurity concentration of the first conductivity type higher than that of the low-concentration source region 21. 22 connected LDS (lightly Doped Source) structure. The drain region 30 is formed by connecting a low-concentration drain region 31 of the first conductivity type formed in a region close to the gate electrode 50 and a high-concentration drain region 32 having an impurity concentration of the first conductivity type higher than that of the low-concentration drain region 31 The LDD (lightly Doped Drain) structure.

As shown in FIGS. 1 to 3 , the semiconductor substrate 10 has a structure as follows: the epitaxial layer 12 of the first conductivity type is grown on the silicon substrate 11 of the second conductivity type, and the epitaxial layer 12 is formed on the epitaxial layer 12. 2 conductivity type well region 13 . A so-called “active region” of the semiconductor device 1 is formed in a region of the well region 13 surrounded by the LOCOS insulating film 60 .

When the LOCOS insulating film 60 is formed, impurities diffused in the well region 13 under the LOCOS insulating film 60 are absorbed to the end of the LOCOS insulating film 60 . As a result, the impurity concentration of the well region 13 near the end of the LOCOS insulating film 60 is reduced. As a result, at the end of the LOCOS insulating film 60, at the gate/source voltage (hereinafter referred to as "drain voltage V (leak)") lower than the designed gate threshold voltage, the source region 20 A leakage current flows between the drain region 30 and the drain region 30 . The "gate threshold voltage at the time of design" is a predetermined gate threshold voltage determined by a preset impurity concentration when the impurity concentration of the well region 13 in the vicinity of the end of the LOCOS insulating film 60 does not decrease.

The occurrence of the above-mentioned leakage current is often observed especially in n-channel MOS transistors. Therefore, in the following, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described by way of example.

In the semiconductor device 1 , the n-type impurity concentration near the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 , that is, the peripheral region S of the gate electrode 50 is lower than the n-type impurity concentration in the central region of the gate electrode 50 . Therefore, at the end portion of the LOCOS insulating film 60 located below the peripheral region S of the gate electrode 50 , channel inversion is less likely to be caused than in the central region of the gate electrode 50 . That is, in the peripheral region S of the gate electrode 50, the gate threshold voltage partially rises.

As described above, in the semiconductor device 1 , the gate threshold voltage in the peripheral region S of the gate electrode 50 (hereinafter referred to as “peripheral gate threshold voltage V(th)2”) is higher than that in the central region of the gate electrode 50 . The gate threshold voltage (hereinafter referred to as "central gate threshold voltage V(th)1") is high. In regions other than the peripheral region S of the gate electrode 50 , the gate threshold voltage is the central gate threshold voltage V(th)1. In addition, the central gate threshold voltage V(th)1 is the gate threshold voltage at design time.

In addition, it is preferable to set the voltage of the gate electrode 50 so that the difference between the central gate threshold voltage V(th)1 and the peripheral gate threshold voltage V(th)2 is greater than the difference between the designed gate threshold voltage and the drain voltage V(leak). The difference between the n-type impurity concentration in the peripheral region S and the n-type impurity concentration in the central region of the gate electrode 50 .

Therefore, in the semiconductor device 1 , leakage current between the source region 20 and the drain region 30 does not occur at the end of the LOCOS insulating film 60 at a gate-source voltage lower than the designed gate threshold voltage.

In addition, the conductivity type of the peripheral region S of the gate electrode 50 may be p-type, and the conductivity type of regions other than the peripheral region S may be n-type. Even in the semiconductor device 1 having this configuration, the peripheral gate threshold voltage V(th)2 of the semiconductor device 1 can be made higher than the central gate threshold voltage V(th)1.

The characteristic A shown in FIG. 4 is a current-voltage characteristic showing the relationship between the gate-source voltage Vgs and the drain current Ids of the semiconductor device 1 according to the first embodiment, and the characteristics B to C are the currents of the comparative example. voltage characteristics.

That is, the characteristic A is the current-voltage characteristic of the semiconductor device 1 as follows: from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 to the central region of the gate electrode 50 across a certain distance w and on the gate insulating film 40 The concentration of the n-type impurity of the gate electrode 50 is lower than the concentration of the n-type impurity in the central region of the gate electrode 50 .

The characteristic B is the current-voltage characteristic of Comparative Example B in which p-type impurities are ion-implanted in the region to the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 with respect to the gate electrode 50 on the LOCOS insulating film 60 . That is, Comparative Example B is a semiconductor device in which the concentration of n-type impurities in the gate electrode 50 on the LOCOS insulating film 60 to the boundary T is lower than the concentration of n-type impurities in the central region of the gate electrode 50 .

The characteristic C is the current-voltage characteristic of Comparative Example C in which no ion-implanted p-type impurity is implanted on the gate electrode 50 and the concentration of the n-type impurity in the gate electrode 50 is uniform throughout the region.

As shown in FIG. 4 , compared with the characteristics B and C, the drain current Ids is smaller in the region where the gate-source voltage Vgs is lower in the characteristic A. That is, it can be seen that the occurrence of leakage current can be suppressed by making the concentration of n-type impurities in gate electrode 50 on gate insulating film 40 in peripheral region S lower than the concentration of n-type impurities in the central region of gate electrode 50 .

As shown in characteristic B, in the peripheral region S of the gate electrode 50, p-type impurities are implanted only in the gate electrode 50 on the LOCOS insulating film 60, and no p-type impurities are implanted in the gate electrode 50 on the gate insulating film 40. In the case of Comparative Example B, although the characteristics were somewhat improved compared with Comparative Example C, leakage current could not be suppressed. Therefore, it can be seen that the peripheral gate threshold voltage V( The semiconductor device 1 in which th)2 is higher than the central gate threshold voltage V(th)1. The distance w is, for example, about 0.5 μm.

As described above, in the semiconductor device 1 according to the first embodiment of the present invention, the n-type impurity concentration in the vicinity of the end portion of the LOCOS insulating film 60 , that is, in the peripheral region S of the gate electrode 50 is higher than the n-type impurity concentration in the central region of the gate electrode 50 . low impurity concentration. Therefore, the peripheral gate threshold voltage V(th)2 in the peripheral region S of the gate electrode 50 is higher than the central gate threshold voltage V(th)1 in the central region of the gate electrode 50 . As a result, according to the semiconductor device 1 shown in FIG. 1 , even in the MOS transistor of the LOCOS separation structure, the occurrence of leakage current between the source region 20 and the drain region 30 can be suppressed.

In addition, in the above, although the case where the first conductivity type is n-type and the second conductivity type is p-type has been described, in the case where the first conductivity type is p-type and the second conductivity type is n-type, The same effect can also be obtained. That is, the p-type source region 20 and the drain region 30 are formed on the n-type well region 13, and the gate electrode 50 made of a p-type polysilicon film is disposed on the gate insulating film 40 and the LOCOS insulating film 60. The p-type impurity concentration in the peripheral region S of the gate electrode 50 is lower than the p-type impurity concentration in the central region of the gate electrode 50 . Accordingly, the gate threshold voltage in the peripheral region S of the gate electrode 50 can be made higher than the gate threshold voltage in the central region of the gate electrode 50 . In addition, in the above-described embodiments, in order to obtain desired characteristics, the conductivity type and impurity concentration of the gate electrode may be appropriately changed.

Hereinafter, an example of a method of manufacturing the semiconductor device 1 in which the n-type impurity concentration in the peripheral region S of the gate electrode 50 is lower than the n-type impurity concentration in the central region of the gate electrode 50 will be described with reference to FIGS. 5 to 12 . The manufacturing method of the semiconductor device described below is an example, and of course it can be realized by various manufacturing methods other than the above, including this modified example. In addition, in each figure of FIG. 5-FIG. 12, figure (a) is a cross-sectional view along the I-I direction of FIG. 2, and figure (b) is a cross-sectional view along the III-III direction.

(A) As shown in FIG. 5 , a p-type well region 13 is formed in an n-type epitaxial layer 12 epitaxially grown on a p-type silicon substrate 11 . Thus, the semiconductor substrate 10 is prepared. The well region 13 is formed, for example, by ion-implanting p-type impurity ions into predetermined positions of the epitaxial layer 12 by an ion implantation method, and then thermally diffusing the p-type impurity.

(B) As shown in FIG. 6 , a LOCOS insulating film 60 is formed on a part of the surface of the epitaxial layer 12 and the well region 13 . For example, after forming a silicon nitride (SiN) film on the entire surface of the epitaxial layer 12 and the well region 13, the silicon nitride film in the region where the LOCOS insulating film 60 is formed is removed using a photolithography technique or the like. Then, with the patterned silicon nitride film used as a mask, the LOCOS insulating film 60 is selectively formed by the LOCOS method. The film thickness of the LOCOS insulating film 60 is, for example, about 300 nm to 600 nm.

(C) After the silicon nitride film on the semiconductor substrate 10 is removed, the exposed surface of the well region 13 is oxidized by thermal oxidation or the like to form the gate insulating film 40 thinner than the LOCOS insulating film 60 . The film thickness of the gate insulating film 40 is, for example, about 40 nm to 60 nm. As a result, as shown in FIG. 7 , the gate insulating film 40 continuous with the LOCOS insulating film 60 is formed in the remaining region where the LOCOS insulating film 60 is formed.

(D) An n-type polysilicon film is formed on the entire surface by chemical vapor deposition (CVD) or the like. Next, the n-type polysilicon film is patterned using a photolithography technique or the like to form a gate electrode 50 as shown in FIG. 8 . That is, the gate electrode 50 made of an n-type polysilicon film is continuously formed on the LOCOS insulating film 60 straddling the gate insulating film 40 and the periphery of the gate insulating film 40 . Alternatively, the gate electrode 50 may be formed by ion-implanting n-type impurities after forming the undoped polysilicon film.

(E) Using the gate electrode 50 as a mask, implant n-type impurity ions such as phosphorus (P) or arsenic (As) into the well region 13, as shown in FIG. 9, to form a low-concentration source region 21 and a low-concentration drain District 31. The surface impurity concentrations of the low-concentration source region 21 and the low-concentration drain region 31 are, for example, about 1×10 ¹⁷ cm ⁻³ .

(F) After forming a silicon nitride film on the entire surface, the silicon nitride film is anisotropically etched by a reactive ion etching (RIE) method or the like. As a result, as shown in FIG. 10 , sidewalls 51 are formed in contact with the side surfaces of the gate electrode 50 . A silicon oxide film or the like may also be used on the side wall 51 .

(G) Using the photoresist film, gate electrode 50, and sidewall 51 patterned by photolithography as a mask, ion implantation of n-type impurities such as phosphorus or arsenic into a predetermined area of the well region 13, such as As shown in FIG. 11 , a high-concentration source region 22 and a high-concentration drain region 32 are formed. The surface impurity concentrations of the high-concentration source region 22 and the high-concentration drain region 32 are, for example, about 2×10 ¹⁹ cm ⁻³ . As shown in FIG. 11 , the low-concentration source region 21 is connected to the high-concentration source region 22 , and the low-concentration drain region 31 is connected to the high-concentration drain region 32 .

(H) After coating the photoresist film 90 on the entire surface, as shown in FIG. , the photoresist film 90 is patterned. At this time, at the end of the gate electrode 50 in the channel width direction, the gate electrode 50 is exposed to at least a distance w from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 to the central region of the gate electrode 50. In this way, the photoresist film 90 is patterned. Next, using the photoresist film 90 as a mask, p-type impurity ions such as boron (B) are implanted into the gate electrode 50 . As a result, p-type impurities are implanted into the peripheral region S of the gate electrode 50 . The implantation amount of p-type impurities is, for example, about 1×10 ¹⁵ cm ⁻² . As a result, the n-type impurity concentration in the peripheral region S of the gate electrode 50 becomes lower than the n-type impurity concentration in the central region of the gate electrode 50 . The photoresist film 90 is removed to complete the semiconductor device 1 shown in FIG. 1 .

In the above, the case where the LDS region and the LDD region are formed has been exemplarily described. However, the semiconductor device 1 may have a structure without the LDS region and the LDD region.

In addition, the step of implanting p-type impurities into the peripheral region S of the gate electrode 50 may be performed as a separate step, or may be performed simultaneously with other semiconductor element manufacturing steps. For example, when a p-channel MOS transistor (not shown) is formed on the semiconductor substrate 10 at the same time as the semiconductor device, in the ion implantation process for forming the source region or the drain region of the p-type channel MOS transistor, P-type impurities are implanted into the peripheral region S of the gate electrode 50 .

In addition, by increasing the concentration of p-type impurities implanted into the peripheral region S of the gate electrode 50, the conductivity type of the central region of the gate electrode 50 can also be maintained as n-type, and the conductivity type of the peripheral region S of the gate electrode 50 can be changed to p-type. .

As described above, according to the manufacturing method of the semiconductor device 1 according to the first embodiment of the present invention, the n-type impurity concentration in the peripheral region S of the gate electrode 50 can be made lower than the n-type impurity concentration in the central region of the gate electrode 50 . As a result, the peripheral gate threshold voltage V(th)2 in the vicinity of the boundary region between the gate insulating film 40 and the LOCOS insulating film 60 of the semiconductor device 1 can be set higher than the central gate threshold voltage V(th)2 in the central region of the gate electrode 50. The voltage V(th)1 is high. Therefore, it is possible to provide the semiconductor device 1 having the LOCOS separation structure in which the generation of leakage current between the source region 20 and the drain region 30 is suppressed.

(second embodiment)

As shown in FIG. 13, the semiconductor device 1 according to the second embodiment of the present invention differs from the semiconductor device 1 shown in FIG. The LOCOS insulating film 60 is also formed on the drain region 31 . Gate electrode 50 shown in FIG. 13 is continuously disposed on LOCOS insulating film 60 formed from gate insulating film 40 across low-concentration source region 21 and low-concentration drain region 31 .

FIG. 14 shows a plan view of the semiconductor device 1 shown in FIG. 13 . FIG. 13 shows a sectional view of the central region of the gate electrode 50 along the XIII-XIII direction of FIG. 14 , that is, the gate length direction of the semiconductor device 1 . In FIG. 14 , the end of the LOCOS insulating film 60 below the gate electrode 50 is indicated by a dotted line, and the gate insulating film 40 is omitted.

As shown in FIG. 14 , the top of the high-concentration source region 22 and the periphery of the high-concentration drain region 32 are surrounded by the LOCOS insulating film 60 . Forming the LOCOS insulating film 60 on the low-concentration drain region 31 has the effect of increasing the withstand voltage between the gate electrode 50 and the drain region 30 .

FIG. 15 shows a cross-section in the channel region along the XV-XV direction of FIG. 14 , that is, the gate width direction of the semiconductor device 1 . The sectional surface shown in FIG. 15 shows the same structure as the sectional surface shown in FIG. 1 .

In the semiconductor device 1 shown in FIGS. 13 to 15 , the area of the gate electrode 50 near the boundary between the gate insulating film 40 and the LOCOS insulating film 60 formed on the low-concentration source region 21 and the low-concentration drain region 31 is The concentration of n-type impurities in the peripheral region S is formed lower than the concentration of n-type impurities in the central region of the gate electrode 50 . Therefore, channel inversion is less likely to occur at the end portion of the LOCOS insulating film 60 under the peripheral region S of the gate electrode 50 than in the central region of the gate electrode 50 . That is, in the peripheral region S of the gate electrode 50, the threshold voltage partially rises.

Therefore, according to the semiconductor device 1 according to the second embodiment of the present invention, the peripheral gate threshold voltage V(th)2 in the peripheral region S of the gate electrode 50 is set to be higher than the central gate threshold voltage V(th)2 in the central region of the gate electrode 50 . (th) 1 high. As a result, according to the semiconductor device 1 of the second embodiment, even in the MOS transistor of the LOCOS offset structure, the occurrence of leakage current between the source region 20 and the drain region 30 can be suppressed. Others are substantially the same as those of the first embodiment, and redundant descriptions are omitted.

FIG. 16 shows another example of the semiconductor device 1 of the second embodiment. In the semiconductor device 1 shown in FIGS. 13 to 15 , in all boundary regions between the LOCOS insulating film 60 formed on the low-concentration source region 21 and the low-concentration drain region 31 and the gate insulating film 40 , the gate electrode The concentration of the n-type impurity at 50 is lower than the concentration of the n-type impurity in the central region. However, as shown in FIG. 16 , it is also possible to extend the distance w from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 to the central region of the gate electrode 50 only at the end of the gate electrode 50 in the channel width direction. , the concentration of the n-type impurity of the gate electrode 50 is lower than the concentration of the n-type impurity in the central region.

When manufacturing the semiconductor device 1 shown in FIGS. 13 to 15 , for example, the following manufacturing method can be employed. That is, as shown in FIG. 17 , a low-concentration source region 21 and a low-concentration drain region 31 are formed on the well region 13 . For example, the low-concentration source region 21 and the low-concentration drain region 31 are formed by ion implantation using a photoresist film formed by photolithography as a mask.

Next, as shown in FIG. 18 , when forming the LOCOS insulating film 60 , the LOCOS insulating film 60 is formed on the low-concentration source region 21 and on the low-concentration drain region 31 .

Thereafter, as described with reference to FIGS. 7 to 8 , the gate insulating film 40 and the gate electrode 50 are formed. Next, as described with reference to FIGS. 10 to 11 , sidewalls 51 , high-concentration source regions 22 and high-concentration drain regions 32 are formed.

Furthermore, after coating the photoresist film 91 on the entire surface, as shown in FIG. The photoresist film 91 is patterned so as to be over the boundary region between the gate insulating films 40 . At this time, at the end portion of the gate electrode 50 in the channel width direction, the gate electrode 50 is exposed at least to a distance w from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 to the central region of the gate electrode 50. In this way, the photoresist film 91 is patterned.

Next, using the photoresist film 91 as a mask, p-type impurity ions such as boron (B) are implanted into the gate electrode 50 . As a result, p-type impurities are injected into the peripheral region S of the gate electrode 50 . As a result, the n-type impurity concentration in the peripheral region S of the gate electrode 50 becomes lower than the n-type impurity concentration in the central region of the gate electrode 50 . The photoresist film 91 is removed to complete the semiconductor device 1 shown in FIGS. 13 to 15 .

According to the manufacturing method of the semiconductor device 1 according to the second embodiment described above, the gap between the gate insulating film 40 of the semiconductor device 1 and the LOCOS insulating film 60 formed on the low-concentration source region 21 and the low-concentration drain region 31 can be formed. The peripheral gate threshold voltage V(th)2 in the vicinity of the boundary region is set higher than the central gate threshold voltage V(th)1 in the central region of the gate electrode 50 . Therefore, it is possible to provide the semiconductor device 1 having the LOCOS offset structure in which the generation of leakage current between the source region 20 and the drain region 30 is suppressed.

(other embodiments)

As mentioned above, although this invention was described by 1st and 2nd embodiment, it should not be understood that this invention is limited by description and drawing which make a part of this indication. Those skilled in the art will be able to clarify various alternative embodiments, examples, and applied techniques from this disclosure.

For example, as the semiconductor substrate 10, a silicon substrate on which the epitaxial layer 12 and the well region 13 are not formed may be used, and the source region 20 and the drain region 30 may be formed on the silicon substrate.

As described above, the present invention naturally includes various embodiments and the like not described here. Therefore, the technical scope of the present invention is defined by the invention-specific matters in the corresponding claims from the above description.

Claims (9)

1. semiconductor device is characterized in that comprising:

Semiconductor substrate;

The source region of the 1st conductivity type and drain region, it is separated from each other on the part on the top of said Semiconductor substrate and forms;

Gate insulating film, it comprises the zone that is clipped by said source region and said drain region, is configured on the said Semiconductor substrate;

The LOCOS dielectric film, its be centered around the channel region that forms between said source region and the said drain region around and on said Semiconductor substrate, dispose the said gate insulation thickness of Film Thickness Ratio continuously with said gate insulating film; And

Gate electrode, it is made up of polysilicon film, and in the zone that clips by said source region and said drain region across said gate insulating film on and said gate insulating film around said LOCOS dielectric film on and continuously the configuration,

Gate threshold voltage in the neighboring area of said gate electrode is higher than the gate threshold voltage in the middle section of said gate electrode, and wherein, the neighboring area of this gate electrode is the end of the channel width dimension of this gate electrode.

2. semiconductor device according to claim 1 is characterized in that,

Different across the conductive-type impurity concentration the middle section of the conductive-type impurity concentration of the said gate electrode on gate insulating film certain distance, said and said gate electrode from the border between said gate insulating film and the said LOCOS dielectric film to the middle section of said gate electrode.

3. semiconductor device according to claim 2 is characterized in that,

Conduction type from said border across the said gate electrode on the gate insulating film said certain distance, said is the 2nd conductivity type, and the conduction type in the middle section of said gate electrode is the 1st conductivity type.

4. according to any described semiconductor device in the claim 1 to 3, it is characterized in that,

Said source region is the structure that is formed by connecting in the impurity concentration high concentration source region higher than said low concentration source region near the low concentration source region of the 1st conductivity type that forms in the zone of said gate electrode and the 1st conductivity type,

Said drain region is the structure that is formed by connecting in the impurity concentration high concentration drain region higher than said low concentration drain region near the low concentration drain region of the 1st conductivity type that forms in the zone of said gate electrode and the 1st conductivity type.

5. semiconductor device according to claim 4 is characterized in that,

On said low concentration source region and said low concentration drain region, dispose said LOCOS dielectric film.

6. the manufacturing approach of a semiconductor device is characterized in that comprising the steps:

Through the LOCOS method, the part on the surface of Semiconductor substrate forms the LOCOS dielectric film;

In the remaining areas in the zone that has formed said LOCOS dielectric film, with the continuous mode of said LOCOS dielectric film, on the surface of said Semiconductor substrate, form the thin gate insulating film of the said LOCOS dielectric film of Film Thickness Ratio;

Across on the said gate insulating film and on the said LOCOS dielectric film around the said gate insulating film and form the gate electrode that constitutes by polysilicon film continuously;

Clip the zone that formed said gate electrode and form the source region and the drain region of the 1st conductivity type on the top of said Semiconductor substrate; And

Make the gate threshold voltage in the neighboring area of said gate electrode higher than the gate threshold voltage in the middle section of said gate electrode; And the middle section from the border between said gate insulating film and the said LOCOS dielectric film to said gate electrode injects conductive-type impurity across certain distance to the said gate electrode on the said gate insulating film; Wherein, the neighboring area of this gate electrode is the end of the channel width dimension of this gate electrode.

7. the manufacturing approach of semiconductor device according to claim 6 is characterized in that,

The step that forms said source region comprises the steps: in the low concentration source region near formation the 1st conductivity type in the zone of said gate electrode; And the impurity concentration that makes the 1st conductivity type high concentration source region higher than said low concentration source region be connected with said low concentration source region and form said source region,

The step that forms said drain region comprises the steps: in the low concentration drain region near formation the 1st conductivity type in the zone of said gate electrode; And the impurity concentration that makes the 1st conductivity type high concentration drain region higher than said low concentration drain region is connected with said low concentration drain region and forms said drain region.

8. the manufacturing approach of semiconductor device according to claim 7 is characterized in that,

Forming said LOCOS dielectric film on the said low concentration source region with on the said low concentration drain region.

9. according to the manufacturing approach of any described semiconductor device in the claim 6 to 8, it is characterized in that,

Through said gate electrode being injected the step of the impurity of the 2nd conductivity type, make the said neighboring area of said gate electrode become the 2nd conductivity type.

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