CN106024806A - Thin-film transistor structure, display panel and control method of display panel - Google Patents

Abstract

The invention relates to a thin film transistor structure, a display panel and a control method thereof, and belongs to the field of display technology. The thin film transistor structure includes: a base substrate, a gate is formed on the base substrate; a source-drain metal pattern is formed on the base substrate formed with the gate, and the source-drain metal pattern includes: a source and a drain; A passivation layer is formed on the base substrate on which the metal pattern of the source and drain is formed, and at least two via holes are formed on the passivation layer above the drain; a pixel electrode is formed on the base substrate on which the passivation layer is formed, And the pixel electrode is connected with the drain electrode through at least two via holes. The invention solves the problem of poor display effect of the display panel and improves the display effect of the display panel. The present invention is used for display panels.

Description

Thin film transistor structure, display panel and control method thereof

technical field

The invention relates to the field of display technology, in particular to a thin film transistor structure, a display panel and a control method thereof.

Background technique

The display panel includes an array substrate and a color filter substrate formed in a cell, and a liquid crystal located between the array substrate and the color filter substrate. The color filter substrate includes a common electrode, and the array substrate includes a plurality of thin film transistor (English: Thin Film Transistor; TFT for short) structures arranged in an array.

Each TFT structure may include a gate, a source, a drain and a pixel electrode, wherein the gate is connected to the gate line, the source is connected to the data line, a passivation layer is formed on the drain, and a passivation layer is formed on the passivation layer. A via hole (English: via) is formed, and the drain electrode can be connected to the pixel electrode through the via hole on the passivation layer. Applying sufficient gate voltage on the gate line can write the control voltage on the data line into the pixel electrode from the source and drain; it should be noted that the array substrate also includes a common electrode line, the common electrode line and the color filter substrate The common electrodes in the circuit are connected, and a common voltage is applied on the common electrode line, so that the common voltage can be written into the common electrodes. The liquid crystal located between the pixel electrode and the common electrode can be deflected under the action of the control voltage on the pixel electrode and the common voltage on the common electrode, changing the light transmittance of the liquid crystal, and then controlling the area corresponding to the pixel electrode on the display panel Displaying preset colors causes the display panel to display images.

Because in the related art, the pixel electrode in each TFT structure is only connected to the drain through a small via hole, the pixel electrode and the drain are easily in poor contact, so that the control voltage on the data line cannot pass through the source and drain. Therefore, the area corresponding to the pixel electrode on the display panel cannot display a preset color, so the display effect of the display panel is poor.

Contents of the invention

In order to solve the problem of poor display effect of the display panel, an embodiment of the present invention provides a thin film transistor structure, a display panel and a control method thereof. Described technical scheme is as follows:

In a first aspect, a thin film transistor structure is provided, and the thin film transistor structure includes: a base substrate,

A gate is formed on the base substrate;

A source-drain metal pattern is formed on the base substrate on which the gate is formed, and the source-drain metal pattern includes: a source and a drain;

A passivation layer is formed on the base substrate on which the source-drain metal pattern is formed, and at least two via holes are formed on the passivation layer above the drain;

A pixel electrode is formed on the substrate on which the passivation layer is formed, and the pixel electrode is connected to the drain through the at least two via holes.

Optionally, the source-drain metal pattern includes: n sources and n drains, where n is an integer greater than or equal to 2, and the At least one via hole is formed on the passivation layer.

Optionally, a via hole is formed on the passivation layer above each of the n drains.

Optionally, the pixel electrode includes n pixel sub-electrodes, and any two adjacent pixel sub-electrodes in the n pixel sub-electrodes are connected to each other, and the n pixel sub-electrodes are connected to the n pixel sub-electrodes through n via holes. The n drains are connected one by one.

Optionally, the pixel electrode includes n pixel sub-electrodes, and the n pixel sub-electrodes are insulated from each other, and the n pixel sub-electrodes are connected to the n drain electrodes one by one through n via holes.

Optionally, a gate line connected to the gate and a data line connected to the n sources are further formed on the substrate,

Wherein, the orthographic projection of the gate line on the pixel electrode is located on the pixel electrode.

Optionally, m slits are formed on each of the n pixel sub-electrodes, where m is an integer greater than or equal to 2.

Optionally, the n is equal to 2,

The n pixel sub-electrodes are arranged axisymmetrically, and the symmetry axis is the orthographic projection of the gate line on the pixel electrode;

The m slits have at least two kinds of slit directions.

Optionally, a gate insulating layer is formed on the substrate on which the gate is formed;

An amorphous silicon layer is formed on the base substrate on which the gate insulating layer is formed;

An ohmic contact layer is formed on the base substrate on which the amorphous silicon layer is formed;

The source-drain metal pattern is formed on the base substrate on which the ohmic contact layer is formed.

In a second aspect, a display panel is provided, and the display panel includes: an array substrate and a color filter substrate formed in a box, and a liquid crystal located between the array substrate and the color filter substrate,

The array substrate includes: a plurality of thin film transistor structures arranged in an array, the thin film transistor structures are the thin film transistor structures described in the first aspect, the color filter substrate includes a common electrode, and among the plurality of thin film transistor structures , at least one gate line in the TFT structure is connected to the common electrode.

A third aspect provides a method for controlling a display panel, where the display panel is the display panel described in the second aspect, and the method includes:

Inputting gate voltages to gates in different thin film transistor structures through gate lines in different thin film transistor structures at different time periods;

During the time period when the gate voltage is not input to the gate in the target thin film transistor structure, the common voltage is input to the common electrode through the gate line in the target thin film transistor structure, the target thin film transistor is the at least one thin film Any thin-film transistor in a transistor.

In summary, the present invention provides a thin film transistor structure, a display panel and a control method thereof. In the thin film transistor structure, a gate, a source-drain metal pattern, a passivation layer, and a pixel electrode are formed on the base substrate. At least two via holes are formed on the passivation layer, and the pixel electrode can be connected to the drain electrode on the substrate through the at least two via holes on the passivation layer. When a certain via hole in the at least two via holes fails, the pixel electrode can also be connected to the drain on the base substrate through other via holes in the at least two via holes, and write the control voltage on the data line to The pixel electrode is inserted, so that on the display panel where the thin film transistor structure is located, the region corresponding to the pixel electrode can display a preset color, thus improving the display effect of the display panel.

It is to be understood that both the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention.

Description of drawings

In order to illustrate the embodiments of the present invention more clearly, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

FIG. 1-1 is a top view of a thin film transistor provided by an embodiment of the present invention;

1-2 are cross-sectional views of a thin film transistor provided by an embodiment of the present invention;

Fig. 2-1 is a top view of another thin film transistor provided by an embodiment of the present invention;

FIG. 2-2 is a cross-sectional view of another thin film transistor provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a pixel electrode provided by an embodiment of the present invention;

FIG. 4-1 is a schematic diagram of a partial structure of a thin film transistor provided by an embodiment of the present invention;

FIG. 4-2 is a schematic diagram of a partial structure of another thin film transistor provided by an embodiment of the present invention;

4-3 is a schematic diagram of a partial structure of another thin film transistor provided by an embodiment of the present invention;

4-4 is a schematic diagram of a partial structure of another thin film transistor provided by an embodiment of the present invention;

4-5 are schematic diagrams of a partial structure of a thin film transistor provided by another embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the present invention.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments . Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Figure 1-1 is a top view of a thin film transistor structure provided by an embodiment of the present invention, and Figure 1-2 is a cross-sectional view of a thin film transistor provided by an embodiment of the present invention, for example, Figure 1-2 may be Figure 1- Cross-sectional view at BB' of the TFT structure in 1. Please refer to FIG. 1-1 and FIG. 1-2, the thin film transistor structure 0 may include: a base substrate 01, a gate 02 is formed on the base substrate 01; The drain metal pattern 03, for example, the source-drain metal pattern 03 may include: a source 031 and a drain 032;

A passivation layer 04 is formed on the base substrate 01 on which the source and drain metal patterns 03 are formed, and at least two via holes A are formed on the passivation layer 04 above the drain 031; the substrate on which the passivation layer 04 is formed A pixel electrode 05 is formed on the substrate 01 , and the pixel electrode 05 is connected to the drain 031 through at least two via holes A formed on the passivation layer 04 .

To sum up, in the thin film transistor structure provided by the embodiment of the present invention, a gate, a source-drain metal pattern, a passivation layer, and a pixel electrode are formed on the substrate, and at least two via holes are formed on the passivation layer. And the pixel electrode can be connected to the drain on the base substrate through at least two via holes on the passivation layer. When a certain via hole in the at least two via holes fails, the pixel electrode can also be connected to the drain on the base substrate through other via holes in the at least two via holes, and write the control voltage on the data line to The pixel electrode is inserted, so that on the display panel where the thin film transistor structure is located, the region corresponding to the pixel electrode can display a preset color, thus improving the display effect of the display panel.

Optionally, the source-drain metal pattern 03 may include: n source electrodes 031 and n drain electrodes 032, wherein n is an integer greater than or equal to 2, and each of the n drain electrodes 032 At least one via hole A may be formed on the passivation layer 04 above the drains 032 , for example, one via hole A may be formed on the passivation layer 04 above each of the n drains 031 .

It should be noted that, in the embodiment of the present invention, n is equal to 2, and a via hole A (that is, the passivation layer 04, a total of n vias A are formed, and the number of vias A on the passivation layer 04 is equal to the number of drains 031) as an example, in practical applications, n can also be other integers greater than 2, n The number of via holes on the passivation layer above each of the drains may also be other integers greater than 1, which is not limited in this embodiment of the present invention.

Figure 2-1 is a top view of a thin film transistor structure provided by an embodiment of the present invention, and Figure 2-2 is an example of a cross-sectional view of a thin film transistor structure provided by an embodiment of the present invention, and Figure 2-2 may be Figure 2- Cross-sectional view of the TFT structure at BB' in 1.

Please combine Figure 2-1 and Figure 2-2, the pixel electrode 05 may include n pixel sub-electrodes 051, and any two adjacent pixel sub-electrodes 051 among the n pixel sub-electrodes 051 are connected to each other, and the n pixel sub-electrodes 051 051 can be connected to n drains 032 one by one through n via holes A. That is, the n pixel sub-electrodes 051 are connected to each other as one electrode, and the one electrode is connected to n drain electrodes 032 through n via holes. And because any two pixel sub-electrodes 051 among the n pixel sub-electrodes 051 are connected to each other, when a certain via hole A fails, the pixel sub-electrode 051 connected to the failed via hole A can pass through other pixel sub-electrodes 051 , The drain 032 connected to other pixel sub-electrodes 051 obtains a voltage.

It should be noted that the thin film transistor structures arranged in an array can form an array substrate in a display panel, and the display panel can also include a color filter substrate disposed opposite to the array substrate, and a liquid crystal located between the array substrate and the color filter substrate. A common electrode can be formed on the film substrate, and the liquid crystal can be deflected under the action of the voltage on the common electrode and the voltage on the pixel electrode.

In the related art, the thin film transistor structure may also include a common electrode line (also known as a Common line) formed on the base substrate, and the common electrode line may be connected to the common electrode on the color filter substrate, and input to the common electrode is required. When the voltage is used, the voltage can be input to the common electrode through the common electrode line. Moreover, the orthographic projection of the common electrode line on the pixel electrode may be located on the pixel electrode, and the common electrode line and the pixel electrode can form a storage capacitor. However, due to the narrow common electrode lines in the related art, the common electrode lines are prone to breakage, so that voltage cannot be input to the common electrodes, and the liquid crystal located between the array substrate and the color filter substrate cannot be effectively deflected.

In the embodiment of the present invention, the gate line 1 connected to the gate 02 and the data line 2 connected to n source electrodes 031 may also be formed on the base substrate 01 . As an example, the two pixel sub-electrodes 051 in the embodiment of the present invention may be arranged axisymmetrically, and the axis of symmetry may be the orthographic projection of the gate line 1 on the pixel electrode 05 . That is, there is no common electrode line formed on the base substrate 01, and the grid line 1 on the base substrate 01 can be connected to the common electrode on the color filter substrate, which is used to replace the common electrode line in the related art to the common electrode. The voltage is input, and the orthographic projection of the gate line 1 on the pixel electrode 05 can be located on the pixel electrode 05 , so that the gate line 1 can also replace the common electrode line in the related art to form a storage capacitor with the pixel electrode 05 . And because the gate line 1 is wider than the common electrode line in the related art, the gate line 1 is less likely to be broken, therefore, the voltage can be effectively input to the common electrode to ensure the normal deflection of the liquid crystal.

Further, m slits X may be formed on each of the n pixel sub-electrodes 051, the m slits X have at least two kinds of slit directions, and m is an integer greater than or equal to 2 . Specifically, since m slits X can be formed on each pixel sub-electrode 051, and the m slits X can cause the liquid crystal between the base substrate and the color filter substrate to have at least two kinds of deflection angles. The different viewing angles of the display panel, combined with the averaging effect of the liquid crystal alignment, can reduce the brightness difference when the display panel is displayed, and reduce the color difference when the display panel displays the picture, thereby improving the quality of the display picture of the display panel.

It should be noted that a gate insulating layer 06 may also be formed on the substrate 01 formed with the gate electrode 02; an amorphous silicon layer 07 may be formed on the substrate 01 formed with the gate insulating layer 06; an amorphous silicon layer 07 may be formed on the substrate 01 formed with the gate insulating layer 06; An ohmic contact layer 08 may be formed on the base substrate 01 of the silicon layer 07 ; and the source-drain metal pattern 03 may be formed on the base substrate 01 formed with the ohmic contact layer 08 .

Optionally, FIG. 3 is a top view of a pixel electrode 05 provided by an embodiment of the present invention. As shown in FIG. 3 , the pixel electrode 05 may further include n pixel sub-electrodes 051, and the n pixel sub-electrodes 051 are insulated from each other. The n pixel sub-electrodes are connected to the n drain electrodes one by one through n via holes. In FIG. 3, the pixel electrode 05 includes two mutually insulated pixel sub-electrodes 051 as an example. The number of included pixel sub-electrodes 051 may also be greater than two. Since the n pixel sub-electrodes 051 are insulated from each other, when the via hole A corresponding to a certain pixel sub-electrode 051 fails, the area corresponding to the pixel sub-electrode 051 on the display panel cannot display the preset color, but other pixel sub-electrodes on the display panel The area corresponding to the electrode 051 can display a preset color, and the area of each pixel sub-electrode 051 in the present invention is smaller than that of the pixel electrode in the related art, so the area on the display panel that cannot display a preset color can be reduced. area, thereby improving the display effect of the display panel.

For example, as shown in FIG. 4-1, when forming the thin film transistor structure, a gate 02 may be first formed on a base substrate 01; then, as shown in FIG. 4-2, the gate 02 may be formed on A gate insulating layer 06 , an amorphous silicon layer 07 and an ohmic contact layer 08 are sequentially formed on the base substrate 01 . As shown in FIG. 4-3, a source-drain metal pattern 03 may be formed on the base substrate 01 formed with an ohmic contact layer 08, and the source-drain metal pattern 03 may include n source electrodes 031 and n drain electrodes 032. ; As shown in FIGS. 4-4 , a passivation layer 04 can be formed on the base substrate 01 on which the source-drain metal pattern 03 is formed, wherein a passivation layer 04 located above each drain 031 can be formed with a Via hole A; as shown in FIG. 4-5, a pixel electrode 05 can be formed on the base substrate 01 formed with a passivation layer 04, and the pixel electrode 05 can pass through at least two via holes A formed on the passivation layer 04 Connected to at least two drain electrodes 031 , at least two slits X may be formed on each pixel sub-electrode 051 .

It should be noted that when the gate is formed on the base substrate, the gate line connected to the gate can be formed on the base substrate at the same time, and when the source-drain metal pattern is formed on the base substrate, the A data line is formed on the substrate, and the data line can be connected to n sources in the source-drain metal pattern.

To sum up, in the thin film transistor structure provided by the embodiment of the present invention, a gate, a source-drain metal pattern, a passivation layer, and a pixel electrode are formed on the substrate, and at least two via holes are formed on the passivation layer. And the pixel electrode can be connected to the drain on the base substrate through at least two via holes on the passivation layer. When a certain via hole in the at least two via holes fails, the pixel electrode can also be connected to the drain on the base substrate through other via holes in the at least two via holes, and write the control voltage on the data line to The pixel electrode is inserted, so that on the display panel where the thin film transistor structure is located, the region corresponding to the pixel electrode can display a preset color, thus improving the display effect of the display panel.

As shown in FIG. 5 , the embodiment of the present invention provides a display panel 5 , which may include: an array substrate 51 and a color filter substrate 52 formed in a box, and a display panel located between the array substrate 51 and the color filter substrate 52 . Between the liquid crystal 53.

The array substrate 51 may include a plurality of thin film transistor structures 0 arranged in an array, and the thin film transistor structure 0 may be the thin film transistor structure 0 shown in FIG. 1-1, FIG. 1-2, FIG. 2-1 or FIG. 2-2. . The color filter substrate 52 may include a base substrate 521 and a common electrode 522 . Among the plurality of thin film transistor structures 0 in the array substrate 51 , the gate line in at least one thin film transistor structure 0 is connected to the common electrode 522 .

Further, the display device where the display panel 5 is located may be any product or component with a display function such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, and the like.

To sum up, in the thin film transistor structure in the display panel provided by the embodiment of the present invention, a gate, a source-drain metal pattern, a passivation layer, and a pixel electrode are formed on the substrate, and at least two transistors are formed on the passivation layer. through holes, and the pixel electrode can be connected to the drain on the substrate through at least two through holes on the passivation layer. When a certain via hole in the at least two via holes fails, the pixel electrode can also be connected to the drain on the base substrate through other via holes in the at least two via holes, and write the control voltage on the data line to The pixel electrodes are inserted, so that on the display panel where the array substrate is located, the area corresponding to the pixel electrodes can display preset colors, thus improving the display effect of the display panel.

An embodiment of the present invention provides a method for controlling a display panel. The display panel may be the display panel 5 shown in FIG. 5 , and the method for controlling the display panel may include:

In different time periods, input gate voltages to gates in different thin film transistor structures through gate lines in different thin film transistor structures; , inputting a common voltage to the common electrode through the gate line in the structure of the target thin film transistor, where the target thin film transistor is any one of the at least one thin film transistor.

Exemplarily, the plurality of thin film transistors may include: a thin film transistor structure 1 , a thin film transistor structure 2 , a thin film transistor structure 3 , a thin film transistor structure 4 and a thin film transistor structure 5 . Wherein, the gate lines in the thin film transistor structure 2 and the thin film transistor structure 5 are connected to the common electrode.

When controlling the display panel, gate voltages can be sequentially input to the gates of the plurality of thin film transistor structures, specifically, when the gate voltage is input to the gates of the thin film transistor structure 1 (not connected to the common The gate of the transistor structure 2 or transistor structure 5 connected to the electrode is input gate voltage), and the common voltage can also be input to the common electrode through the gate line in the target transistor structure (such as transistor structure 2 or transistor structure 5); When the thin film transistor structure 2 inputs the gate voltage (at this time, the gate voltage is not input to the gate of the transistor structure 5 connected to the common electrode), the gate line in the target transistor structure (such as the transistor structure 5) can also be sent to The common electrode inputs the common voltage; when the gate voltage is input to the thin film transistor structure 3 (the gate voltage is not input to the gate of the transistor structure 2 or transistor structure 5 connected to the common electrode at this time), the target transistor can also pass The gate line in the structure (such as transistor structure 2 or transistor structure 5) inputs the common voltage to the common electrode; 5), the gate voltage in the target transistor structure (such as the transistor structure 2 or the transistor structure 5) can also input the common voltage to the common electrode through the gate line in the transistor structure 5; when inputting the gate voltage to the thin film transistor structure 5 ( At this time, no gate voltage is input to the gate of the transistor structure 2 connected to the common electrode), and the common voltage can also be input to the common electrode through the gate line in the target transistor structure (such as the transistor structure 2).

For example, a gate driver on array (English: Gate driver On Array; GOA for short) circuit may be used to input gate voltages to the gates of different thin film transistor structures in different time periods. Specifically, when the clock signal of the GOA circuit is at a high level, the GOA circuit can input a gate voltage to the gate of the thin film transistor structure through the gate line in the thin film transistor structure, so that the thin film transistor structure is in In the working state, that is, the control voltage on the data line in the thin film transistor can be input to the pixel electrode through the source and drain. It should be noted that the common voltage in the related art is lower than the gate voltage, when the gate voltage is applied to the gate, the corresponding source and drain of the gate can be turned on, but when the common voltage is applied to the gate When it is on, the source and drain corresponding to the gate cannot be turned on.

To sum up, in the control method of the display panel provided by the present invention, in different time periods, gate voltages are input to gates in different thin film transistor structures through gate lines in different thin film transistor structures, so that the input gate voltage The control voltage on the data line in the thin film transistor structure of the target voltage can be input to the pixel electrode through the source and the drain, and in the time period when the gate voltage is not input to the gate in the target thin film transistor structure, through the target thin film transistor The gate lines in the structure input a common voltage to the common electrodes. The control voltage is input to the pixel electrode, and the common voltage is input to the common electrode, so that the liquid crystal can be deflected under the action of the control voltage and the common voltage, so that the display panel displays images.

Other embodiments of the invention will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present invention, these modifications, uses or adaptations follow the general principles of the present invention and include common knowledge or conventional technical means in the technical field not disclosed in the present invention . The specification and examples are to be considered exemplary only, with the true scope and spirit of the invention indicated by the appended claims.

It should be understood that the present invention is not limited to the precise constructions which have been described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims (11)

1. a thin-film transistor structure, it is characterised in that described thin-film transistor structure includes: substrate base Plate,

It is formed with grid on described underlay substrate；

It is formed on the underlay substrate of described grid and is formed with source-drain electrode metal pattern, described source-drain electrode metal figure Case includes: source electrode and drain electrode；

It is formed on the underlay substrate of described source-drain electrode metal pattern and is formed with passivation layer, be positioned in described drain electrode It is formed with at least two via on the described passivation layer of side；

It is formed on the underlay substrate of described passivation layer and is formed with pixel electrode, and described pixel electrode passes through institute State at least two via to be connected with described drain electrode.

Thin-film transistor structure the most according to claim 1, it is characterised in that described source-drain electrode metal Pattern includes: n source electrode and n drain electrode, and described n is the integer more than or equal to 2,

It is formed with at least one via on the described passivation layer above each drain electrode in described n drain electrode.

Thin-film transistor structure the most according to claim 2, it is characterised in that

It is formed with a via on the described passivation layer above each drain electrode in described n drain electrode.

Thin-film transistor structure the most according to claim 3, it is characterised in that

Described pixel electrode includes any two phase in n pixel sub-electrode, and described n pixel sub-electrode Adjacent pixel sub-electrode is connected with each other, and described n pixel sub-electrode is by n via and described n drain electrode Connect one by one.

Thin-film transistor structure the most according to claim 3, it is characterised in that

Described pixel electrode includes n pixel sub-electrode, and described n pixel sub-electrode mutually insulated, institute State n pixel sub-electrode to be connected one by one with described n drain electrode by n via.

Thin-film transistor structure the most according to claim 4, it is characterised in that on described underlay substrate It is also formed with the grid line being connected with described grid, and the data wire being connected with described n source electrode,

Wherein, the orthographic projection on described pixel electrode of the described grid line is positioned on described pixel electrode.

Thin-film transistor structure the most according to claim 6, it is characterised in that

Each pixel sub-electrode in described n pixel sub-electrode has been respectively formed on m slit, and described m is Integer more than or equal to 2.

Thin-film transistor structure the most according to claim 7, it is characterised in that described n is equal to 2,

Described n pixel sub-electrode axial symmetry is arranged, and axis of symmetry is that described grid line is on described pixel electrode Orthographic projection；

Described m slit has at least 2 kinds of slit direction.

Thin-film transistor structure the most according to claim 1, it is characterised in that

It is formed on the underlay substrate of described grid and is formed with gate insulation layer；

It is formed on the underlay substrate of described gate insulation layer and is formed with amorphous silicon layer；

It is formed on the underlay substrate of described amorphous silicon layer and is formed with ohmic contact layer；

It is formed on the underlay substrate of described ohmic contact layer and is formed with described source-drain electrode metal pattern.

10. a display floater, it is characterised in that described display floater includes: the array base that box is shaped Plate and color membrane substrates, and the liquid crystal between described array base palte and color membrane substrates,

Described array base palte includes: multiple thin-film transistor structures of array arrangement, and described thin film transistor (TFT) is tied Structure is the arbitrary described thin-film transistor structure of claim 1 to 9, and described color membrane substrates includes public electrode, In the plurality of thin-film transistor structure, the grid line at least one thin-film transistor structure is public with described Electrode is connected.

The control method of 11. 1 kinds of display floaters, it is characterised in that described display floater is claim 10 Described display floater, described method includes:

In the different time periods, respectively by the grid line in different thin-film transistor structures to different thin film Grid input grid voltage in transistor arrangement；

In the time period of the not grid in aimed thin film transistor arrangement input grid voltage, by described mesh Grid line in mark thin-film transistor structure inputs common electric voltage, described aimed thin film crystal to described public electrode Pipe is the arbitrary thin film transistor (TFT) at least one thin film transistor (TFT) described.