CN104269410A - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN104269410A CN104269410A CN201410446700.3A CN201410446700A CN104269410A CN 104269410 A CN104269410 A CN 104269410A CN 201410446700 A CN201410446700 A CN 201410446700A CN 104269410 A CN104269410 A CN 104269410A
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- 239000000758 substrate Substances 0.000 title claims abstract description 78
- 239000010409 thin film Substances 0.000 claims abstract description 88
- 238000002161 passivation Methods 0.000 claims description 16
- 239000012212 insulator Substances 0.000 claims description 9
- 230000004044 response Effects 0.000 abstract description 9
- 238000002360 preparation method Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate and a display device. The array substrate comprises a substrate body, a plurality of thin-film transistors and a plurality of pixel electrodes, the thin-film transistors and the pixel electrodes are located on the array substrate, and the thin-film transistors correspond to the pixel electrodes one to one. Because the orthographic projection, on the substrate body, of each thin-film transistor is completely located within the orthographic projection, on the substrate body, of the corresponding pixel electrode, when gray scale signals loaded on data lines charge the pixel electrodes through the thin-film transistors, charging can be carried out from the interior to the periphery of each pixel electrode, the pixel electrodes can be fast charged, the charging efficiency of the pixel electrodes can be improved, and the response speed of a flat-panel display can be increased.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and display unit.
Background technology
Along with the development of Display Technique, light-emitting diode (Light Emitting Diode, LED), Organic Light Emitting Diode (Organic Light Emitting Diode, OLED), plasma display (Plasma Display Panel, PDP) and the development of the flat-panel monitor such as liquid crystal display (Liquid Crystal Display, LCD) rapidly.
Array base palte in existing flat-panel monitor, as shown in Figure 1, comprising: underlay substrate, and is positioned at grid line 101, data wire 102, thin-film transistor (Thin Film Transistor, TFT) 103 and the pixel electrode 104 on underlay substrate; Thin-film transistor 103 generally comprises grid 105, active layer 106, source electrode 107 and drain electrode 108, and wherein, grid 105 is connected with grid line 101, and source electrode 107 is connected with data wire 102, and drain electrode 108 is connected with pixel electrode 104.For N-type TFT, when the sweep signal of grid line input high potential, the TFT be connected with grid line is in opening, and the grayscale signal that data wire loads is applied on pixel electrode by TFT, charges to pixel electrode.
In existing array base palte, because in TFT, only part drain electrode is mutually overlapping with pixel electrode, like this, when the grayscale signal that data wire is loaded is charged to pixel electrode by TFT, can only from the edge of pixel electrode a bit, the position that the drain electrode namely in pixel electrode and TFT is electrically connected, start to charge to pixel electrode, like this, can cause the charge efficiency of pixel electrode lower, thus affect the response speed of flat-panel monitor.
Therefore, how improving the charge efficiency to pixel electrode, is the technical problem that those skilled in the art need solution badly.
Summary of the invention
In view of this, embodiments provide a kind of array base palte and display unit, in order to improve the charge efficiency to pixel electrode.
Therefore, embodiments provide a kind of array base palte, comprising: underlay substrate, and be positioned at described underlay substrate intersects and the grid line put and data wire, multiple thin-film transistor and with described thin-film transistor multiple pixel electrode one to one; Wherein, each described thin-film transistor comprises grid and the active layer of mutually insulated, and the source electrode be electrically connected respectively with described active layer and drain electrode;
Each described thin-film transistor is positioned at the orthographic projection of corresponding described pixel electrode at described underlay substrate completely in the orthographic projection of described underlay substrate.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, each described thin-film transistor is positioned at corresponding pixel electrode at the center of the orthographic projection of described underlay substrate in the orthographic projection of described underlay substrate.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, each described thin-film transistor covers the overlapping region of described grid line and described data wire in the orthographic projection of described underlay substrate.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the overlapping region of described grid line and described data wire, in the orthographic projection of described underlay substrate, is positioned at each described thin-film transistor at the center of the orthographic projection of described underlay substrate; Each described pixel electrode forms by arranging identical and four of area equation the pixel sub-electrodes be separated of the shape of arrangement in two row two, and four pixel sub-electrodes in each described pixel electrode are all electrically connected with the drain electrode in corresponding thin-film transistor;
In each described pixel electrode, two row pixel sub-electrodes are in the orthographic projection of described underlay substrate, are arranged in the data wire that is electrically connected with the source electrode of corresponding thin-film transistor in the both sides of the orthographic projection of described underlay substrate; In each described pixel electrode, two row pixel sub-electrodes are in the orthographic projection of described underlay substrate, are arranged in the grid line that is electrically connected with the grid of corresponding thin-film transistor in the both sides of the orthographic projection of described underlay substrate.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, in each described thin-film transistor, described source electrode surrounds described drain electrode, makes to form closed raceway groove between described source electrode and described drain electrode.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, described drain electrode is circular in the shape of the orthographic projection of described underlay substrate, and described raceway groove is annular in the shape of the orthographic projection of described underlay substrate.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, in each described thin-film transistor, described source electrode and described drain electrode are all positioned at the top of described active layer, and described grid is positioned at the below of described active layer;
Each described pixel electrode is arranged in the corresponding source electrode of thin-film transistor and the top of drain electrode.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, in each described thin-film transistor, described source electrode and described drain electrode are all positioned at the top of described active layer, and described grid is positioned at the top of described source electrode and described drain electrode;
Each described pixel electrode is arranged in the top of the grid of corresponding thin-film transistor, and with the grid mutually insulated in corresponding thin-film transistor.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, also comprise: the source electrode in each described thin-film transistor and the passivation layer between drain electrode place rete and each described pixel electrode place rete;
Each described pixel electrode is electrically connected with the drain electrode in corresponding thin-film transistor by the via hole in described passivation layer.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, also comprise: be partially filled in the chock insulator matter in described via hole.
The embodiment of the present invention additionally provides a kind of display unit, comprising: the above-mentioned array base palte that the embodiment of the present invention provides.
The above-mentioned array base palte that the embodiment of the present invention provides and display unit, array base palte comprises: underlay substrate, and the multiple thin-film transistor be positioned on underlay substrate and with thin-film transistor multiple pixel electrode one to one; Because each thin-film transistor is positioned at the orthographic projection of corresponding pixel electrode at underlay substrate completely in the orthographic projection of underlay substrate, like this, when the grayscale signal that data wire loads is charged to pixel electrode by thin-film transistor, can charge towards periphery from the inside of pixel electrode, the quick charge to pixel electrode can be realized, thus the charge efficiency that can improve pixel electrode, and then the response speed of flat-panel monitor can be improved.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing array base palte;
Fig. 2-Fig. 7 is respectively one of structural representation of the array base palte that the embodiment of the present invention provides;
Fig. 8 a is the cutaway view of Fig. 6 along AA direction;
The structural representation two of the array base palte that Fig. 8 b provides for the embodiment of the present invention;
Fig. 9 a-Fig. 9 d is respectively the structural representation of preparation method after performing each step of the array base palte shown in Fig. 6;
Figure 10 a-Figure 10 e is respectively the structural representation of preparation method after performing each step of the array base palte shown in Fig. 8 a.
Embodiment
Below in conjunction with accompanying drawing, the array base palte provide the embodiment of the present invention and the embodiment of display unit are described in detail.
In accompanying drawing, the shape of each rete and thickness do not reflect the actual proportions of array base palte, and object just signal illustrates content of the present invention.
A kind of array base palte that the embodiment of the present invention provides, as shown in Figure 2, comprise: underlay substrate, and be positioned at underlay substrate intersects and the grid line 1 put and data wire 2 (Fig. 2 is mutually vertical with data wire for grid line), multiple thin-film transistor 3 and with thin-film transistor 3 multiple pixel electrode 4 (Fig. 2 is for one of them thin-film transistor and corresponding pixel electrode) one to one; Wherein, each thin-film transistor 3 comprises grid 5 and the active layer 6 of mutually insulated, and the source electrode 7 be electrically connected respectively with active layer 6 and drain 8;
Each thin-film transistor 3 is positioned at the orthographic projection of corresponding pixel electrode 4 at underlay substrate completely in the orthographic projection of underlay substrate.
The above-mentioned array base palte that the embodiment of the present invention provides, because each thin-film transistor 3 is positioned at the orthographic projection of corresponding pixel electrode 4 at underlay substrate completely in the orthographic projection of underlay substrate, like this, when the grayscale signal that data wire 2 loads is charged by thin-film transistor 3 pairs of pixel electrodes 4, can charge towards periphery from the inside of pixel electrode 4, the quick charge to pixel electrode 4 can be realized, thus the charge efficiency that can improve pixel electrode 4, and then the response speed of flat-panel monitor can be improved.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 3, each thin-film transistor 3 is positioned at corresponding pixel electrode 4 at the center of the orthographic projection of underlay substrate in the orthographic projection of underlay substrate, like this, when the grayscale signal that data wire 2 loads is charged by thin-film transistor 3 pairs of pixel electrodes 4, can charge towards periphery from the center of pixel electrode 4, can realize charging more equably to pixel electrode 4, thus the charge efficiency that can improve further pixel electrode 4, and then make the flat-panel monitor with the above-mentioned array base palte that the embodiment of the present invention provides have response speed faster.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 4, each thin-film transistor 3 is positioned at corresponding pixel electrode 4 at the center of the orthographic projection of underlay substrate in the orthographic projection of underlay substrate, each thin-film transistor 3 covers the overlapping region of grid line 1 and data wire 2 in the orthographic projection of underlay substrate, compare with the situation of grid line with the overlapping region non-overlapping copies of data wire with thin-film transistor in existing array base palte, the flat-panel monitor with the above-mentioned array base palte that the embodiment of the present invention provides can have higher aperture opening ratio.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 5, each thin-film transistor 3 is positioned at corresponding pixel electrode 4 at the center of the orthographic projection of underlay substrate in the orthographic projection of underlay substrate, the overlapping region of grid line 1 and data wire 2 is positioned at each thin-film transistor 3 at the center of the orthographic projection of underlay substrate in the orthographic projection of underlay substrate, therefore, the overlapping region of grid line 1 and data wire 2 is positioned at corresponding pixel electrode 4 at the center of the orthographic projection of underlay substrate in the orthographic projection of underlay substrate; Each pixel electrode 4 forms by arranging identical and four of area equation the pixel sub-electrodes be separated of the shape of arrangement in two row two, and four pixel sub-electrodes in each pixel electrode 4 are all electrically connected with the drain electrode 8 in corresponding thin-film transistor 3; Further, in each pixel electrode 4, two row pixel sub-electrodes are in the orthographic projection of underlay substrate, are arranged in the data wire 2 that is electrically connected with the source electrode 7 of corresponding thin-film transistor 3 in the both sides of the orthographic projection of underlay substrate; In each pixel electrode 4, two row pixel sub-electrodes are in the orthographic projection of underlay substrate, are arranged in the grid line 1 that is electrically connected with the grid 5 of corresponding thin-film transistor 3 in the both sides of the orthographic projection of underlay substrate; Like this, each thin-film transistor 3 is positioned at four corresponding pixel sub-electrodes at the center of the orthographic projection of underlay substrate in the orthographic projection of underlay substrate, when the grayscale signal that data wire 2 loads is charged to four of correspondence pixel sub-electrodes by thin-film transistor 3, can realize charging equably to four pixel sub-electrodes of correspondence, thus the charge efficiency improved pixel electrode 4, and then the flat-panel monitor with the above-mentioned array base palte that the embodiment of the present invention provides is made to have response speed faster.
Certainly, in the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the structure of each pixel electrode 4 is not limited to plane-shape electrode as shown in figs 2-4, also be not limited to and be divided into four pixel sub-electrodes as shown in Figure 5, each pixel electrode 4 can also be divided into more pixel sub-electrode, does not limit at this.Further, the shape of each pixel electrode 4 is not limited to rectangle as shown in figs 2-4, can also be other shapes, not limit at this.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, in each thin-film transistor 3, source electrode 7 surrounds drain electrode 8, make to form closed raceway groove 9 between source electrode 7 and drain electrode 8, like this, the breadth length ratio of raceway groove 9 in each thin-film transistor 3 can be increased under the prerequisite of aperture opening ratio not affecting flat-panel monitor, thus the charging current that can increase pixel electrode 4, and then the charge efficiency that can improve further pixel electrode 4, the flat-panel monitor with the above-mentioned array base palte that the embodiment of the present invention provides is made to have response speed faster.
Preferably, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, drain electrode 8 is circular in the shape of the orthographic projection of underlay substrate, raceway groove 9 is annular in the shape of the orthographic projection of underlay substrate, like this, the breadth length ratio of raceway groove 9 in each thin-film transistor 3 can be made maximum, thus make the charging current of pixel electrode 4 maximum, and then the charge efficiency that can farthest improve pixel electrode 4, make the flat-panel monitor with the above-mentioned array base palte that the embodiment of the present invention provides have response speed faster.Fig. 7 is four thin-film transistor 3 of structure and the structural representations of corresponding pixel electrode 4 as shown in Figure 6.
Certainly, in the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the drain electrode 8 in each thin-film transistor 3 also can be other shapes in the shape of the orthographic projection of underlay substrate, such as: polygon etc.; Raceway groove 9 in each thin-film transistor 3 can be also other closed shapes in the shape of the orthographic projection of underlay substrate, does not limit at this.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, each thin-film transistor 3 is specifically as follows bottom-gate type configuration; Or, can be also top-gate type structure, not limit at this.
Particularly, when thin-film transistor 3 in the above-mentioned array base palte that the embodiment of the present invention provides is for bottom-gate type configuration, as shown in Figure 8 a, Fig. 8 a is the cutaway view of Fig. 6 along AA direction, in each thin-film transistor 3, source electrode 7 and drain electrode 8 are all positioned at the top of active layer 6, and grid 5 is positioned at the below of active layer 6; Each pixel electrode 4 is arranged in the source electrode 7 of corresponding thin-film transistor 3 and the top of drain electrode 8.
Particularly, when thin-film transistor 3 in the above-mentioned array base palte that the embodiment of the present invention provides is for top-gate type structure, as shown in Figure 8 b, in each thin-film transistor 3, source electrode 7 and drain electrode 8 are all positioned at the top of active layer 6, and grid 5 is positioned at the top of source electrode 7 and drain electrode 8; Each pixel electrode 4 is arranged in the top of the grid 5 of corresponding thin-film transistor 3, and with grid 5 mutually insulated in corresponding thin-film transistor 3.Wherein, grid 5 is by the first passivation layer 10 and source electrode 7 and 8 mutually insulateds that drain, and pixel electrode 4 is by the second passivation layer 11 and grid 5 mutually insulated.
And, in the above-mentioned array base palte that the embodiment of the present invention provides, as figures 8 a and 8 b show, can also comprise: the source electrode 7 in each thin-film transistor 3 and the passivation layer 12 (the first passivation layer 10 and the second passivation layer 11 shown in Fig. 8 b) between drain electrode 8 place retes and each pixel electrode 4 place rete; Each pixel electrode 4 is electrically connected with the drain electrode 8 in corresponding thin-film transistor 3 by the via hole in passivation layer 12.When each pixel electrode 4 is made up of four the pixel sub-electrodes be separated, four pixel sub-electrodes in each pixel electrode 4 are all electrically connected with the drain electrode 8 in corresponding thin-film transistor 3 by the via hole in passivation layer 12.
In addition, in the above-mentioned array base palte that the embodiment of the present invention provides, as figures 8 a and 8 b show, can also comprise: be partially filled in the chock insulator matter 13 in via hole, namely the height of chock insulator matter 13 is greater than the degree of depth of via hole, and, chock insulator matter 13 can with via hole one_to_one corresponding, or, also chock insulator matter 13 can be set in part via hole, not limit at this; Like this, via hole in passivation layer 12 can also play certain fixation to chock insulator matter 13, when the flat-panel monitor with the above-mentioned array base palte that the embodiment of the present invention provides is subject to the effect of external pressure, can prevent chock insulator matter 13 from sliding and make flat-panel monitor occur showing the problems such as bad, thus the compressive property of flat-panel monitor can be improved.
It should be noted that, in the above-mentioned array base palte that the embodiment of the present invention provides, as figures 8 a and 8 b show, source electrode 7 and drain electrode 8 are all positioned at the top of active layer 6, in order to avoid carrying out in patterning process to source electrode 7 and drain electrode 8, cause damage to the oxide active layer 6 be positioned at below source electrode 7 and drain electrode 8, this array base palte can also comprise: at source electrode 7 and the etching barrier layer between drain electrode 8 place retes and active layer 6 place rete.
Below for the array base palte of preparation as shown in Fig. 6 and Fig. 8 a, be described in detail the preparation process of above-mentioned array base palte, concrete preparation process comprises following step:
(1), on underlay substrate, the figure of grid 5 and grid line 1 is formed, as shown in Fig. 9 a and Figure 10 a;
(2), on the underlay substrate being formed with grid 5 and grid line 1 deposition of gate insulating barrier, as shown in fig. lob;
(3), on gate insulator, the figure of active layer 6 is formed with, as shown in Fig. 9 b and Figure 10 c;
(4) on the underlay substrate being formed with active layer 6, by patterning processes form the figure of source electrode 7, drain electrode 8 and data wire 2, wherein, form the raceway groove 9 of annular between source electrode 7 and drain electrode 8, as shown in Fig. 9 c and Figure 10 d;
(5), be formed source electrode 7, drain electrode 8 and data wire 2 underlay substrate on deposit passivation layer 12, form via hole in the passivation layer 12 above drain electrode 8, as shown in Fig. 9 d and Figure 10 e;
(6), on passivation layer 12, form the pixel electrode 4 be made up of four pixel sub-electrodes, these four pixel sub-electrodes are all electrically connected, as shown in Fig. 6 and Fig. 8 a by the via hole in passivation layer 12 and drain electrode 8.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display unit, comprise the above-mentioned array base palte that the embodiment of the present invention provides, this display unit can be: any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.The enforcement of this display unit see the embodiment of above-mentioned array base palte, can repeat part and repeats no more.
A kind of array base palte that the embodiment of the present invention provides and display unit, array base palte comprises: underlay substrate, and the multiple thin-film transistor be positioned on underlay substrate and with thin-film transistor multiple pixel electrode one to one; Because each thin-film transistor is positioned at the orthographic projection of corresponding pixel electrode at underlay substrate completely in the orthographic projection of underlay substrate, like this, when the grayscale signal that data wire loads is charged to pixel electrode by thin-film transistor, can charge towards periphery from the inside of pixel electrode, the quick charge to pixel electrode can be realized, thus the charge efficiency that can improve pixel electrode, and then the response speed of flat-panel monitor can be improved.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. an array base palte, comprising: underlay substrate, and be positioned at described underlay substrate intersects and the grid line put and data wire, multiple thin-film transistor and with described thin-film transistor multiple pixel electrode one to one; Wherein, each described thin-film transistor comprises grid and the active layer of mutually insulated, and the source electrode be electrically connected respectively with described active layer and drain electrode; It is characterized in that:
Each described thin-film transistor is positioned at the orthographic projection of corresponding described pixel electrode at described underlay substrate completely in the orthographic projection of described underlay substrate.
2. array base palte as claimed in claim 1, is characterized in that, each described thin-film transistor is positioned at corresponding pixel electrode at the center of the orthographic projection of described underlay substrate in the orthographic projection of described underlay substrate.
3. array base palte as claimed in claim 2, it is characterized in that, each described thin-film transistor covers the overlapping region of described grid line and described data wire in the orthographic projection of described underlay substrate.
4. array base palte as claimed in claim 3, it is characterized in that, the overlapping region of described grid line and described data wire, in the orthographic projection of described underlay substrate, is positioned at each described thin-film transistor at the center of the orthographic projection of described underlay substrate; Each described pixel electrode forms by arranging identical and four of area equation the pixel sub-electrodes be separated of the shape of arrangement in two row two, and four pixel sub-electrodes in each described pixel electrode are all electrically connected with the drain electrode in corresponding thin-film transistor;
In each described pixel electrode, two row pixel sub-electrodes are in the orthographic projection of described underlay substrate, are arranged in the data wire that is electrically connected with the source electrode of corresponding thin-film transistor in the both sides of the orthographic projection of described underlay substrate; In each described pixel electrode, two row pixel sub-electrodes are in the orthographic projection of described underlay substrate, are arranged in the grid line that is electrically connected with the grid of corresponding thin-film transistor in the both sides of the orthographic projection of described underlay substrate.
5. the array base palte as described in any one of claim 1-4, is characterized in that, in each described thin-film transistor, described source electrode surrounds described drain electrode, makes to form closed raceway groove between described source electrode and described drain electrode.
6. array base palte as claimed in claim 5, is characterized in that, described drain electrode is circular in the shape of the orthographic projection of described underlay substrate, and described raceway groove is annular in the shape of the orthographic projection of described underlay substrate.
7. array base palte as claimed in claim 6, it is characterized in that, in each described thin-film transistor, described source electrode and described drain electrode are all positioned at the top of described active layer, and described grid is positioned at the below of described active layer;
Each described pixel electrode is arranged in the corresponding source electrode of thin-film transistor and the top of drain electrode.
8. array base palte as claimed in claim 6, it is characterized in that, in each described thin-film transistor, described source electrode and described drain electrode are all positioned at the top of described active layer, and described grid is positioned at the top of described source electrode and described drain electrode;
Each described pixel electrode is arranged in the top of the grid of corresponding thin-film transistor, and with the grid mutually insulated in corresponding thin-film transistor.
9. array base palte as claimed in claim 7 or 8, is characterized in that, also comprise: the source electrode in each described thin-film transistor and the passivation layer between drain electrode place rete and each described pixel electrode place rete;
Each described pixel electrode is electrically connected with the drain electrode in corresponding thin-film transistor by the via hole in described passivation layer.
10. array base palte as claimed in claim 9, is characterized in that, also comprise: be partially filled in the chock insulator matter in described via hole.
11. 1 kinds of display unit, is characterized in that, comprising: the array base palte as described in any one of claim 1-10.
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| CN106125423A (en) * | 2016-06-21 | 2016-11-16 | 上海纪显电子科技有限公司 | Liquid crystal indicator, array base palte and preparation method thereof |
| CN107219690A (en) * | 2017-07-19 | 2017-09-29 | 上海中航光电子有限公司 | Display panel and display device |
| CN107219690B (en) * | 2017-07-19 | 2020-04-03 | 上海中航光电子有限公司 | Display panel and display device |
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| WO2019174136A1 (en) * | 2018-03-13 | 2019-09-19 | 深圳市华星光电半导体显示技术有限公司 | Pixel unit and fabrication method therefor, and display apparatus |
| US11322527B2 (en) | 2018-03-13 | 2022-05-03 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Pixel unit, manufacturing method thereof, and display device |
| WO2020056843A1 (en) * | 2018-09-17 | 2020-03-26 | 重庆惠科金渝光电科技有限公司 | Array substrate, display panel and display device |
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