CN105897249B - A kind of number based on pin multiplexing trims system - Google Patents
A kind of number based on pin multiplexing trims system Download PDFInfo
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- CN105897249B CN105897249B CN201610195229.4A CN201610195229A CN105897249B CN 105897249 B CN105897249 B CN 105897249B CN 201610195229 A CN201610195229 A CN 201610195229A CN 105897249 B CN105897249 B CN 105897249B
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention discloses a kind of numbers based on pin multiplexing to trim system, the control circuit for including and trimming input pulse signal and connecting, the output end of control circuit is connected separately with shift-register circuit and trims circuit, the output end of shift-register circuit is connect with the input terminal for trimming circuit, is trimmed to be connected between the output end of circuit and the input terminal of control circuit and is trimmed backfeed loop；Chip is used as without special one pin of extraction and trims pin, but the directly functional pin of multiplexing chip, can reduce the number of pin of chip；Shift-register circuit is mainly by the control signal for trimming signal pulse number and being transformed into the certain bits for needing to trim of input；It is mainly to receive the certain bits of shift-register circuit to trim signal and the fuse failure of corresponding positions will be trimmed to result simultaneously latches and export and give the module that trims of chip needs to trim circuit, and chip after the completion of trimming can effectively be avoided to be in the generation accidentally trimmed under normal operating conditions.
Description
Technical field
The present invention relates to trim circuit in IC design field more particularly to a kind of IC design field.
Background technology
As the requirement to performance of integrated circuits index is higher and higher, it is increasingly bright that integrated circuit faces high-precision requirement
Aobvious, the technology of trimming is to realize the necessary means of high-precision integrated circuit.Technology is trimmed in IC design primarily directed to electricity
Resistance network and capacitance network are trimmed, and are trimmed technology by different, can be increased or reduced resistance value and capacitance.It trims
Both stage i.e. wafer scale can have been surveyed in the chips to carry out, and can also have been carried out after chip is at survey stage, that is, scribing encapsulation, two kinds
Method cuts both ways.The former can select all defective works in wafer scale, but to make test board and be sealed in chip
Survey is still carried out into after dress, it is time-consuming and laborious；And the latter then directly carries out testing after chip package and is carried out simultaneously to chip
It trims, many costs can be saved.Due to before packaging that by test, inevitably some defective products can not sealed as non-defective unit
Dress, this can increase some packaging costs.But when the yield of chip reaches very high, selection is at the survey stage trim
A kind of more cost-effective way.
The chip that conventionally employed such method is trimmed needs special one pin of extraction as pin is trimmed, with total
Number device is trimmed with circuit progress number is trimmed, as shown in Figure 1.This can increase chip pin number and cost, and may cause to miss
Trigger the generation trimmed.
Invention content
Technical problem to be solved by the invention is to provide a kind of neither increase to trim pin, and can be to avoid trimming
The number based on pin multiplexing for accidentally trimming generation being under normal operating conditions at rear chip trims system.
In order to solve the above technical problems, the technical scheme is that：A kind of number based on pin multiplexing trims system,
The control circuit for including and trimming input pulse signal and connecting, the output end of the control circuit are connected separately with shift register
Circuit and circuit is trimmed, the output end of the shift-register circuit is connect with the input terminal for trimming circuit, described to trim
It is connected between the output end of circuit and the input terminal of the control circuit and trims backfeed loop；
The control circuit include two input terminals respectively with chip interior reference voltage signal VREF and trim input arteries and veins
Rushing the comparator of signal IN connections, the output end of the comparator is connected to an input terminal of the first NAND gate, and described first
Another input terminal of NAND gate is connect by NOT gate with the backfeed loop that trims, and the output end of first NAND gate passes through
NOT gate is connected to the Enable Pin of counter, and the output end of the counter is connected to an input terminal of the first nor gate, described
The output end of first nor gate is connect with the ends CLK of the shift-register circuit, another input terminal of first nor gate
It being connect with the output end of first NAND gate, the clock end of the counter is connected with the second nor gate, and described second or non-
One input terminal of door is connect with clock signal clk, and another input terminal and described trim of second nor gate feed back to
Road connects；
Further include the second NAND gate that two input terminals are connect with chip interior enable signal EN1 and EN2, described second with
The output end of NOT gate is connected with rest-set flip-flop, the Enable Pin of the output end of the rest-set flip-flop and the shift-register circuit and
The Enable Pin connection for trimming backfeed loop；
The shift-register circuit includes a set d type flip flop being sequentially connected in series and multiple reset d type flip flops, is owned
The Reset input terminals of the d type flip flop connect with the enable signal EN of control circuit output, all D are tactile
The ends CLK of hair device are connect with clock signal clk, are located at the signal input part D ground connection of the primary d type flip flop, behind
The signal input part D of the d type flip flop connect with the positive output end Q of the previous d type flip flop；
Described to trim the current source that circuit includes multiple parallel connections, each current source is connected to fuse circuit
The OUT1 output ends of OUT2 output ends, each fuse circuit connect an output nor gate, and the EN of the fuse circuit is defeated
Enter end connection fuse opening signal EB, the READ input terminals of the fuse circuit pass sequentially through a nor gate and a NOT gate with
The EN1 connections of chip interior enable signal；The output end output number of the output nor gate trims information.
As a kind of perferred technical scheme, the counter includes N number of concatenated d type flip flop, all D triggerings
The Reset input terminals of device are connect with the enable signal EN of control circuit output, the ends CLK of first d type flip flop
It is connect with clock signal clk, each inverse output terminal of the d type flip flop is connected with the signal input part D of the d type flip flop, often
The CLK connections of d type flip flop clock end, the last one described d type flip flop described in the inverse output terminal and the latter of a d type flip flop
Output end be connected to an input terminal of rest-set flip-flop, another input terminal of the rest-set flip-flop and the control circuit are defeated
The enable signal EN connections gone out；Output end of the output end of the rest-set flip-flop as the counter.
As a kind of perferred technical scheme, the fuse circuit includes two transmission gate circuits and three Nverter circuits
Latch circuit is constituted, for input terminal EN and BURN by being connected with metal-oxide-semiconductor with door, the drain electrode of metal-oxide-semiconductor is connected with fuse, metal-oxide-semiconductor
Drain electrode be also sequentially connected there are one transmission gate circuit and two reversers, two reversers and another described transmission gate
Circuit in parallel.
By adopting the above-described technical solution, a kind of number based on pin multiplexing trims system, including inputted with trimming
The output end of the control circuit of pulse signal connection, the control circuit is connected separately with shift-register circuit and trims electricity
Road, the output end of the shift-register circuit are connect with the input terminal for trimming circuit, the output end for trimming circuit
It is connected between the input terminal of the control circuit and trims backfeed loop；In the present invention, chip does not have to special extraction one
Pin, which is used as, trims pin, but the directly functional pin of multiplexing chip, can reduce the number of pin of chip, control circuit master
Generate the enable signal of other modules of the present invention；Input is mainly trimmed signal pulse number by shift-register circuit
It is transformed into the control signal for the certain bits for needing to trim；Trim repairing for the certain bits that circuit is mainly reception shift-register circuit
It adjusts signal and the fuse failure of corresponding positions will be trimmed to result simultaneously and latch and export and need the module trimmed to chip, to complete
At the entire control process that number trims, chip after the completion of trimming can effectively be avoided to be in accidentally repairing under normal operating conditions
The generation of tune.
Description of the drawings
Fig. 1 is existing public technology embodiment；
Fig. 2 is the general construction block diagram of the present invention；
Fig. 3 is that the N bit digitals of the present invention trim topological structure；
Fig. 4 is that the 4-digit number of the present invention trims topological structure；
Fig. 5 is the N-bit counter circuit structure diagram of the present invention；
Fig. 6 is the N bit shift register circuit structure diagrams of the present invention；
Fig. 7 is the five bit shift register circuit structure diagrams of the present invention；
Fig. 8 is that the positions N of the present invention trim circuit structure diagram；
Fig. 9 is that five of the present invention trim circuit structure diagram；
Figure 10 is the fuse and flip-latch circuit structure figure of the present invention.
Specific implementation mode
With reference to the accompanying drawings and examples, the present invention is further explained.In the following detailed description, only pass through explanation
Mode describes certain exemplary embodiments of the present invention.Undoubtedly, those skilled in the art will recognize,
In the case of without departing from the spirit and scope of the present invention, described embodiment can be repaiied with a variety of different modes
Just.Therefore, attached drawing and description are regarded as illustrative in nature, and are not intended to limit the scope of the claims.
As shown in Fig. 2, a kind of number based on pin multiplexing trims system, includes and trim input pulse signal and connect
The output end of control circuit 201, the control circuit 201 is connected separately with shift-register circuit 202 and trims circuit 203,
The output end of the shift-register circuit 202 connect with the input terminal for trimming circuit 203, the circuit 203 that trims
It is connected between output end and the input terminal of the control circuit 201 and trims backfeed loop.
As shown in Figure 3 and Figure 4, the control circuit 201 includes that two input terminals are believed with chip interior reference voltage respectively
Number VREF is connected to the first NAND gate 201_ with the comparator for trimming input pulse signal IN and connecting, the output end of the comparator
Another input terminal of 2 input terminal, the first NAND gate 201_2 is fed back to by NOT gate 201_6 and described trim
Road connects, and the output end of the first NAND gate 201_2 is connected to the Enable Pin of counter, the counting by NOT gate 201_3
The output end of device is connected to an input terminal of the first nor gate 201_4, the output end of the first nor gate 201_4 with it is described
The ends CLK of shift-register circuit 202 connect, another input terminal and first NAND gate of the first nor gate 201_4
The output end of 201_2 connects, and the clock end of the counter is connected with the second nor gate 201_5, the second nor gate 201_5
An input terminal connect with clock signal clk, another input terminal of the second nor gate 201_5 with described trim feedback
Circuit connects；Further include the second NAND gate 201_7 that two input terminals are connect with chip interior enable signal EN1 and EN2, it is described
The output end of second NAND gate 201_7 is connected with rest-set flip-flop, the output end of the rest-set flip-flop and shift register electricity
The Enable Pin on road 202 is connected with the Enable Pin for trimming backfeed loop.As shown in figure 5, the counter includes N number of concatenated
D type flip flop, the enable signal EN that the Reset input terminals of all d type flip flops are exported with the control circuit 201 connect
It connects, the ends CLK of first d type flip flop are connect with clock signal clk, the inverse output terminal and the D of each d type flip flop
The signal input part D of trigger is connected, d type flip flop clock end described in the inverse output terminal and the latter of each d type flip flop
The output end of CLK connections, the last one d type flip flop is connected to an input terminal of rest-set flip-flop, the rest-set flip-flop
Another input terminal is connect with the enable signal EN that the control circuit 201 exports；The output end of the rest-set flip-flop is as institute
State the output end of counter.
As shown in Figure 6 and Figure 7, the shift-register circuit 202 includes a set d type flip flop being sequentially connected in series and more
A reset d type flip flop, the enable signal that the Reset input terminals of all d type flip flops are exported with the control circuit 201
The ends CLK of EN connections, all d type flip flops are connect with clock signal clk, are located at the primary set D triggerings
The signal input part D ground connection of device, the subsequent signal input part D for resetting d type flip flop and the previous d type flip flop are just
To output end Q connections.
As shown in Figure 8 and Figure 9, the current source for trimming circuit 203 and including multiple parallel connections, each current source connection
An output nor gate, institute are connected in the OUT1 output ends of the OUT2 output ends of a fuse circuit, each fuse circuit
State the EN input terminals connection fuse opening signal EB of fuse circuit, the READ input terminals of the fuse circuit pass sequentially through one or
NOT gate and a NOT gate are connect with chip interior enable signal EN1；The output end output number of the output nor gate trims letter
Breath.As shown in Figure 10, the fuse circuit includes that two transmission gate circuits and three Nverter circuits constitute latch circuit, defeated
Enter to hold EN and BURN by being connected with metal-oxide-semiconductor with door, the drain electrode of metal-oxide-semiconductor is connected with fuse, and the drain electrode of metal-oxide-semiconductor is also connected in turn
One transmission gate circuit and two reversers, two reversers are in parallel with transmission gate circuit described in another.
The concrete operating principle of the present invention is done below and is illustrated:
As shown in Fig. 2, for total topological diagram of the present invention, including control circuit 201, shift-register circuit 202 and trimming
Circuit 203.IN is to trim input pulse signal, and CLK is the clock signal of chip interior, and FB is to trim end mark position signal,
OUT is to trim output control signal.After chip finds to need to trim and determine the position for needing to trim after a test, the ends IN are defeated
Enter corresponding impulse waveform, shift-register circuit 202 can carry out corresponding shift motion, one section is waited for after input pulse
Time will produce the enable signal trimmed, at this time by shift-register circuit 202 when the time is more than counter gate time
Output squeeze into and trim in circuit 203, which can complete the fusing of corresponding position fuse, wait having to carry out after the completion of trimming
Highest order fuse is blown, it is therefore intended that generate and trim the marking signal FB of end, the signal can feed back to control module to
Trimming module is locked, mistake when chip being avoided to work normally trims action.The result finally trimmed can be on every subsystem
It reads and is latched in the latch trimmed inside circuit 203 after electricity, while result output will be trimmed, to control system phase
That answers position trims function.
As shown in figure 3, the total topological diagram trimmed for a N bit digital.We are by taking a 4-digit number trims system as an example
It illustrates, the topology of the system is as shown in Figure 4.Wherein control circuit 201 with lower unit by being constituted：201_1 is comparator；
201_2 and 201_7 is two input nand gates；201_4 and 201_5 is two input nor gates；201_3 and 201_6 is NOT gate；201_
8 be rest-set flip-flop；201_9 is counter.Wherein CLK signal is chip interior oscillator output pulse signal；EN1, EN2 are core
Enable signal inside piece, two signals have the sequential relationship for becoming high level successively；VREF believes for chip interior reference voltage
Number, 0.7V or so can be taken as；The ends IN are the input pulse signal trimmed, have both the functional pin of chip simultaneously herein.Under
Face describes the operation principle of control circuit.
It determines which module of chip interior needs to trim and how to trim according to the test result of chip first, hereafter inputs
The ends signal IN need the number of the square wave inputted that can determine therewith.After system electrification, chip enable signal EN1 and EN2 are successively
Become high level：When EN1 is got higher and EN2 keeps low level, inside modules current source bias circuit is first started to work, and is locked simultaneously
Storage read signal is sent out；And when EN1 and EN2 become high level, all modules of system are enabled, while latches signal
It sends out.And above-mentioned control function is completed by control circuit 201.Chip interior oscillator is started to work upon power-up of the system,
At the beginning since input signal IN terminal voltages are less than reference voltage V REF, comparator 201_1 outputs are low level, which passes through
It is still low level, enable signal of the signal as counter 201_9 after 201_2 and 201_3.Since we set 201_9
The ends Enable Pin EN high level for when it is enabled, so 201_9 is constantly in cleared condition, output is also low level.And at this time
It shift-register circuit 202 and trims circuit 203 and be in enabled state, once the ends input signal IN level changes, shift
Register circuit 202 will be triggered and be displaced, and mobile specific digit is determined by inputting the pulse number at the ends IN.IN
It is just always maintained at high level after the completion of the pulse signal of end, this hour counter 201_9 starts to work and counts.When the ends IN keep high electricity
The flat time is more than the counting period of counter, then the output level of counter 201_9 is got higher by low, on the one hand which blocks
Shift-register circuit 202, on the other hand enabled to trim circuit 203, hereafter trimming circuit 203 can be according to shift-register circuit
202 output determines whether the fuse of corresponding positions blows to realize that number trims.This method can be only done one and repaiies every time
It adjusts, after the completion of waiting for that all positions trim work, input IN has to continue to post to force high level to be moved to displacement to pulse in end
The highest order BIT4 of latch circuit, and then realize the 5th and trim, when the 5th fuse failure after, OUT4 can be made to become high
Current potential becomes low level after 201_6, and the signal is as one of 201_5 input terminals by comparator output signal screen
It covers.It is this from lock-in techniques ensure after chip work normally when input terminal IN any variation all will not to trim play it is any
Influence, to prevent the generation accidentally trimmed.
As shown in figure 5, being a N-bit counter circuit diagram：The module has N number of D altogether by 201_9_1~201_9_N and triggers
Device and a rest-set flip-flop 201_8 are constituted.The number of N was by CLK weeks of the gate time (can be Millisecond) and chip that set
Phase common setups.All trigger resets when EN signals are low level, output OUT are low level, hereafter such as regardless of EN signals
What changes, and output remains low level, when counter counts completely count and the ends EN are high level, output end ability set,
High level is become from low level.
As shown in fig. 6, being a N bit shift register circuit diagram.We are by taking a five bit shift register circuits as an example
It illustrates, as shown in Figure 7.The shift register is made of six d type flip flops of 202_1~202_6, and wherein 202_1 set D is touched
Device is sent out, remaining 202_2~202_6 is to reset d type flip flop.Wherein set flip-flop is meant that when Set signals are low level
Output end Q is high level；And it resets d type flip flop and is meant that output end Q is low level when reset signals are low level；
The ends D of 202_1 earthing potential always, when EN signals are low level, 202_1 set, the ends output Q are high level, remaining 202_2
~202_6 resets, and the ends output Q are low level.When CLK signal constantly has pulse square wave input, the high level of 202_1 output ends
It constantly will move backward to realize the function of shift register in the rising edge of each CLK.It is high after five clock pulses
Level is moved into BIT4, if hereafter there is clock input again, the ends output Q of all d type flip flops will become low level.
As shown in figure 8, trimming circuit diagram for one N.We illustrate so that one five trim circuit as an example, such as scheme
Shown in 9,203_1 includes that 203_1_1~203_1_5 is five identical fuse modules, and 203_2 includes 203_2_1~203_2_5
For five an equal amount of current sources.In the case where fuse opening signal EB is enabled, corresponding position fuse depends on whether blowing
In the BURN signals of the module whether be high level, and the signal derive from higher level's shift register output.When 203_1_1~
After having fuse to be blown inside 203_1_5, the output of respective modules OUT1 becomes high level, need not blow the module of fuse by
The output of OUT1 is made to remain low level in the drop-down of current source 203_2_1~203_2_5, these information have just been powered in system
When read and latched wherein by latch module.The method of latches data is：It is read in when READ signal is high level
Data become latch data after low level.And output TR0~TR4 final after nor gate 203_3 is exactly system respectively trims
The number of position trims information.203_3 is made of five nor gates of 203_3_1~203_3_5, and nor gate why is needed to be intended to add
Enter enable signal EN to make output become controllable.
It needs to illustrate there are one technology point herein：It it is 1~2 megaohm since the resistance value of the fuse after blowing is finite value
Nurse rank (parameter that occurrence is provided by technique manufacturer determines), so to make the input of latch to there are one low and high levels
Correctly judge, current source is needed to provide a big current value；And after latch reads data and latches, in order to drop
The power consumption of low system wants that current source is made to maintain a low current value again, so using setting for variable pull-down current source herein
Meter.Specific work process is as follows：203_2_1~203_2_5 is the mirror current source of 203_9, and current value is N times of 203_9,
The size of 203_8 is identical with the size of 203_2_1~203_2_5, and 203_7 is switching tube, and 203_10 is the electricity that electric current is I1
Stream source.When READ signal is high level, switching tube 203_7 is disconnected, and the electric current I1 of current source all flows through 203_9, at this time
The electric current of 203_2_1~203_2_5 is N*I1, which ensures that latch inputs the correct judgement to low and high level；Hereafter
READ signal becomes low level, and switching tube 203_7 is closed, and the electric current I1 of current source 203_10 flows through 203_8 and 203_9 simultaneously,
Then the current value of 203_2_1~203_2_5 becomes (N/N+1) * I1, and the electric current is smaller, can reduce the power consumption of system.N's takes
Resistance value and supply voltage after value and fuse opening with and the size of current source current I1 have relationship, should be closed according to these factors
The value of reason selection N is to ensure the correct judgement of low and high level.
As shown in Figure 10, it is a fuse circuit and latch circuit figure；By 203_1_1_6,203,_1_,1_7 two in upper figure
Tri- Nverter circuits of a transmission gate circuit and 203_1_1_3,203_1_1_4,203_1_1_5 constitute latch circuit, when
When READ signal is high level, 203_1_1_6 is closed and 203_1_1_7 is opened, and realizes the acquisition of data；And when READ signal becomes
For low level when, 203_1_1_6 open and 203_1_1_7 be closed, realize the latch of data；When EN and BURN signals are all high electricity
Usually, metal-oxide-semiconductor 203_1_1_9 is opened, and occurs high current access between power supply and ground, which flows through fuse 203_1_1_8 productions
Heat amount leads to Wen Sheng, when temperature be more than fuse fusing point when, fuse opening, then the ends OUT2 low level is become from high level, should
Latch of the signal meeting by after is acquired and is latched.Notice that the size of metal-oxide-semiconductor 203_1_1_9 is sufficiently large.
The basic principles and main features and advantages of the present invention of the present invention have been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the above embodiments and description only describe this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these changes
Change and improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention by appended claims and its
Equivalent thereof.
Claims (3)
1. a kind of number based on pin multiplexing trims system, it is characterised in that：Include and trims input pulse signal and connect
The output end of control circuit, the control circuit is connected separately with shift-register circuit and trims circuit, the shift LD
The output end of device circuit is connect with the input terminal for trimming circuit, the output end for trimming circuit and the control circuit
It is connected between input terminal and trims backfeed loop；
The control circuit include two input terminals respectively with chip interior reference voltage signal VREF and trim input pulse believe
The comparator of number IN connections, the output end of the comparator are connected to an input terminal of the first NAND gate, described first with it is non-
Another input terminal of door is connect by NOT gate with the backfeed loop that trims, and the output end of first NAND gate passes through NOT gate
It is connected to the Enable Pin of counter, the output end of the counter is connected to an input terminal of the first nor gate, and described first
The output end of nor gate is connect with the ends CLK of the shift-register circuit, another input terminal of first nor gate and institute
The output end connection of the first NAND gate is stated, the clock end of the counter is connected with the second nor gate, second nor gate
One input terminal is connect with clock signal clk, another input terminal of second nor gate trims backfeed loop company with described
It connects；
Further include the second NAND gate that two input terminals are connect with chip interior enable signal EN1 and EN2, second NAND gate
Output end be connected with rest-set flip-flop, the Enable Pin of the output end of the rest-set flip-flop and the shift-register circuit and described
Trim the Enable Pin connection of backfeed loop；
The shift-register circuit includes a set d type flip flop being sequentially connected in series and multiple reset d type flip flops, all institutes
It states the enable signal EN that the Reset input terminals of d type flip flop are exported with the control circuit to connect, all d type flip flops
The ends CLK connect with clock signal clk, be located at the signal input part D ground connection of the primary d type flip flop, subsequent institute
The signal input part D for stating d type flip flop is connect with the positive output end Q of the previous d type flip flop；
Described to trim the current source that circuit includes multiple parallel connections, the OUT2 that each current source is connected to a fuse circuit is defeated
The OUT1 output ends of outlet, each fuse circuit connect an output nor gate, and the EN input terminals of the fuse circuit connect
Fuse opening signal EB is met, the READ input terminals of the fuse circuit pass sequentially through in a nor gate and a NOT gate and chip
Portion's enable signal EN1 connections；The output end output number of the output nor gate trims information.
2. the number based on pin multiplexing trims system as described in claim 1, it is characterised in that：The counter includes N
A concatenated d type flip flop, the enable signal of the Reset input terminals of all d type flip flops with control circuit output
The ends CLK of EN connections, first d type flip flop are connect with clock signal clk, the inverse output terminal of each d type flip flop
It is connected with the signal input part D of the d type flip flop, described in the inverse output terminal and the latter of each d type flip flop when d type flip flop
The output end of the CLK connections of clock end, the last one d type flip flop is connected to an input terminal of rest-set flip-flop, the RS triggerings
Another input terminal of device is connect with the enable signal EN that the control circuit exports；The output end of the rest-set flip-flop is as institute
State the output end of counter.
3. the number based on pin multiplexing trims system as described in claim 1, it is characterised in that：The fuse circuit includes
Two transmission gate circuits and three Nverter circuits constitute latch circuit, and input terminal EN and BURN with door by being connected with MOS
Pipe, the drain electrode of metal-oxide-semiconductor are connected with fuse, and the drain electrode of metal-oxide-semiconductor is also sequentially connected there are one transmission gate circuit and two reversers, and two
A reverser is in parallel with transmission gate circuit described in another.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610195229.4A CN105897249B (en) | 2016-03-31 | 2016-03-31 | A kind of number based on pin multiplexing trims system |
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| CN201610195229.4A CN105897249B (en) | 2016-03-31 | 2016-03-31 | A kind of number based on pin multiplexing trims system |
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| CN105897249B true CN105897249B (en) | 2018-09-28 |
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