CN101252349B - Data storage apparatus of multi-power supply area - Google Patents
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- CN101252349B CN101252349B CN2008100886661A CN200810088666A CN101252349B CN 101252349 B CN101252349 B CN 101252349B CN 2008100886661 A CN2008100886661 A CN 2008100886661A CN 200810088666 A CN200810088666 A CN 200810088666A CN 101252349 B CN101252349 B CN 101252349B
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Abstract
The invention discloses a data storage device in a multi-power supply area, comprising a clock pulse path which can receive close pulse signals, a first flip-latch controlled by close pulse signals, a data delivery path arranged between a data input terminal and a data output terminal , a second flip-latch and a three-state output logic element. The first flip-latch is arranged between the data input terminal and the data output terminal; the second flip-latch is connected with the data delivery path at a node which is arranged between the first flip-latch and the data output terminal to enable the second flip-latch to save the data signals according to data saving signals when in sleep mode; the three-state output logic element is disposed on the data delivery path and is under the control of the data saving signals so that the three-state output logic element is capable of blocking the data delivery path when the three-state output logic element is in sleep.
Description
Technical field
The present invention relates to a kind of data storage apparatus, relate in particular to a kind of data storage apparatus of multi-power supply area.
Background technology
As everyone knows, many semiconductor integrated logic devices (semiconductor integrated logicdevice) can provide a plurality of power supply areas (multi power domains), and make logic device be used in operator scheme (operational mode) and sleep pattern (sleep mode).Under operator scheme, all power supply areas are power supply all normally, makes logic device work normally.And under sleep pattern, only having the part power supply area can supply subelement in the logic device in order to reduce the loss of electric energy, another part element then continues power supply in order to avoid the data and set point disappearance in the logic device in the logic device.Therefore, when logic device is got back to operator scheme once more, can come regular event according to before data and set point.
Moreover in order to allow logic device in sleep pattern time storage data and set point, the data storage apparatus of multi-power supply area just arises at the historic moment.Please refer to Fig. 1, it is the given data save set.This data storage apparatus is disclosed in U.S. Pat 7180348, applies to operate data storage device and method " circuit and method for storing data in operational and sleep modes " with sleep pattern.This data storage device is a master-slave mode trigger (master-slave flip flop), comprising: one first ternary element (tristateable device), 30, one main latch (master latch), 10,1 second ternary element 32 and is from latch (slave latch) 20; Wherein, the one first ternary element 30 and the second ternary element 32 are transmission gate (transmission gate).Moreover, as shown in Figure 1, clock pulse signal (clk) and a sleep signal (/sleep) input to a NAND gate (NAND gate), make NAND gate export one first clock pulse signal (nclk), and first clock pulse signal (nclk) input, the one non-second clock pulse signal (bclk) of exporting behind the door, and first clock pulse signal (nclk) and second clock pulse signal (bclk) complementary (complement).When sleep signal (/sleep) be high level interval scale operator scheme, at this moment, first clock pulse signal (nclk) with second clock pulse signal (bclk) but normal running; When sleep signal (/sleep) be low level interval scale sleep pattern, at this moment, first clock pulse signal (nclk) maintains high level and second clock pulse signal (bclk) maintains low level.
The input of one data-signal (D) input, the first ternary element 30, the output of the first ternary element 30 be connected to first latch 10 export in order to receive this data-signal reverse data-signal (/D); Moreover, reverse data-signal (/D) input of the input second ternary element 32, the output of this three-state element 32 be connected to from latch 20 in order to receive reverse data-signal (/D) and in output (Q) outputting data signals (D).Moreover, a switch element 40, for example power transistor (power transistor) can be controlled main latch 10 and two supply voltage (V
DdWith V
Ss) between connection; And be connected directly to two supply voltage (V from latch 20
DdWith V
Ss).
When operator scheme, sleep signal (/sleep) be high level.Therefore, when first clock pulse signal (nclk) is low level for high level second clock pulse signal (bclk), 30 actions of the first ternary element make input signal (D) can be passed to main latch 10 and the second ternary element 32 be failure to actuate make reverse input signal (/D) can't be passed to from latch 20; Otherwise, when first clock pulse signal (nclk) is high level for low level second clock pulse signal (bclk), the first ternary element 30 be failure to actuate make input signal (D) can't be passed to main latch 10 and 32 actions of the second ternary element make reverse input signal (/D) can be passed to from latch 20.
When sleep pattern, sleep signal (/sleep) be low level.Therefore, switch element 40 open circuit (open) main latch 10 and two supply voltage (V
DdWith V
Ss) between connection, therefore, the data of main latch 10 stored can disappear.Yet second clock pulse signal (bclk) maintains low level because first clock pulse signal (nclk) maintains high level, and therefore, the second ternary element 32 is failure to actuate.That is to say that when sleep pattern, the second ternary element can completely cut off the signal of (isolate) its input and output, therefore, make and to continue to keep from latch 20 interior storage data.
As shown in Figure 1, can be considered a data delivery path (data forward path) by data-signal (D) input to output (Q), and the data delivery path comprises: the first ternary element 30, main latch 10, the second ternary element 32 and from latch 20.
Please refer to Fig. 2, it is known another data storage apparatus.This data storage apparatus is disclosed in U.S. Patent Publication No. 20070085585 and 20070103217, at the data storage device " data retention in operational and sleep modes " of operation with sleep pattern.This data storage device is a master-slave mode trigger (master-slave flip flop), comprising: the ternary element of the ternary element of one first not gate 230, one first 232, a main latch 210, one second 234, is from latch 220, one the 3rd ternary element 250, one second not gate 236; Wherein, one first ternary element 232, second ternary element 234 and the 3rd ternary element 250 are transmission gate (transmission gate).
Moreover, as shown in Figure 2, clock pulse path 212 comprises: a clock pulse signal (clk) inputs to non-one first clock pulse signal (nclk) of exporting behind the door, and first clock pulse signal (nclk) is imported another non-second clock pulse signal (bclk) of exporting behind the door, and first clock pulse signal (nclk) and second clock pulse signal (bclk) complementary (complement).Moreover, data are preserved signal path 214 and comprised: data preservation signals (ret) input to the non-reverse data of exporting behind the door and preserve signal (nret), and data preservation signals (ret) are preserved signal (nret) number complementation (complement) with reverse data.Wherein, first ternary element 232, the second ternary element 234 is controlled by first clock pulse signal (nclk) and second clock pulse signal (bclk); And the 3rd ternary element 232 is controlled by data preservation signals (ret) and reverse data preservation signal (nret).Moreover preserving signals (ret) when data be low level interval scale operator scheme, at this moment, first clock pulse signal (nclk) and second clock pulse signal (bclk) but normal running; Preserving signal (ret) when data is high level interval scale sleep pattern.
In Fig. 2, be connected in series between a data-signal (D) and the output (Q) first not gate, 230, the first ternary element 232, main latch 210, the second ternary element 234, with second not gate 236.And the input of second not gate 236 has a branch (branch), comprise in this branch the 3rd ternary element 250 with from latch 220.That is to say that data-signal (D) input to the data delivery path of output (Q) comprising: first not gate, 230, the first ternary element 232, main latch 210, the second ternary element 234, second not gate 236.Clearly, from latch 220 and the 3rd ternary element 250 not on the data delivery path.
When sleep pattern, it is high level that data are preserved signal (ret).Therefore, the 3rd ternary element 250 is failure to actuate and is isolated from latch 220 and data delivery path.Otherwise when operator scheme, it is low level that data are preserved signal (ret), and therefore, the 3rd ternary element 250 actions and connection make with the data delivery path from latch 220 and can be passed to output (Q) from latch 220.
Moreover the shadow region representative of Fig. 2 needs the part of power supply supply when sleep pattern.That is to say that when sleep pattern, the part of power supply supply comprises: element, data on latch the 220, the 3rd ternary element 250, clock pulse path 212 are preserved the element on the signal path 214.
Please refer to Fig. 3, it is known another data storage apparatus.This data storage apparatus is disclosed in U.S. Patent Publication No. 20070085585 and 20070103217, at the data storage device " data retention in operational and sleep modes " of operation with sleep pattern.This data storage device is a master-slave mode trigger (master-slave flip flop), comprising: the ternary element of the ternary element of one first not gate 330, one first 332, a main latch 310, one second 334, is from latch 320, one the 3rd ternary element 350, one second not gate 336; Wherein, one first ternary element 332, second ternary element 334 and the 3rd ternary element 350 are transmission gate (transmission gate).
In like manner, data-signal (D) input to the data delivery path of output (Q) comprising: first not gate, 330, the first ternary element 332, main latch 310, the second ternary element 334, second not gate 336.Clearly, from latch 320 and the 3rd ternary element 350 not on the data delivery path.
Be compared to Fig. 2, its difference is can make that from the structure of latch 320 when the sleep pattern, the element on the clock pulse path 312 can not need to be powered, can be so that from latch 320 storage data, reach more purpose of power saving.That is, the representative of the shadow region of Fig. 3 needs the part of power supply supply when sleep pattern.That is to say that when sleep pattern, the part of power supply supply comprises: preserve the element on the signal path 214 from latch the 220, the 3rd ternary element 250, data.
Summary of the invention
The object of the present invention is to provide a kind of and the different data storage apparatus of given data save set structure.
The present invention proposes a kind of data storage apparatus, and this data storage apparatus comprises: a clock pulse path, can receive a clock pulse signal, and according to complementary one first clock pulse signal and the second clock pulse signal of this clock pulse signal output; One first latch is controlled by this first clock pulse signal and second clock pulse signal, and according to this first clock pulse signal and second clock pulse signal storage data; One data delivery path, between a data input pin and a data output end, and this first latch is arranged between this data input pin and this data output end, makes a data-signal can import this data input pin and be stored in this first latch and be passed to this data output end along this data delivery path according to this first clock pulse signal and second clock pulse signal; One second latch be connected in this data passes path in a node, and this node is arranged between this first latch and this data output end, makes this second latch preserve signal according to data and keeps this data-signal when the sleep pattern; And, a ternary output logic element, this three-state output logic arrangements of components is on this data passes path and be controlled by this data preservation signal, makes this three-state output logic element can block this data delivery path when this sleep pattern.
Description of drawings
Fig. 1 is the given data save set.
Fig. 2 is known another data storage apparatus.
Fig. 3 is known another data storage apparatus.
Fig. 4 A is first embodiment of data storage apparatus of the present invention.
Fig. 4 B is the ternary output logic element circuitry of the present invention figure.
Fig. 4 C is the another kind of circuit diagram of the ternary output logic element of the present invention.
Fig. 5 A is second embodiment of data storage apparatus of the present invention.
Fig. 5 B is the ternary output logic element circuitry of the present invention figure.
Fig. 5 C is the another kind of circuit diagram of the ternary output logic element of the present invention.
And the description of reference numerals in the above-mentioned accompanying drawing is as follows:
10 main latch 20 are from latch
30 first ternary element 32 second ternary elements
40 switch elements
210,310,410,510 main latch
212,312,412,512 clock pulse paths
214,314,414,514 data are preserved signal path
220,320,420,520 from latch
230,330,430,530 first not gates
232,332,432,532 first ternary output logic elements
234,334,434,534 second ternary output logic elements
236,336,436,536 second not gates
250,350,450,550 the 3rd ternary output logic elements
Embodiment
In order will to reach and the different data storage apparatus of given data save set structure, the present invention preserves signal (ret) and reverse data with data and preserves the 3rd ternary element that signals (nret) are controlled and place the data delivery path.Please refer to Fig. 4 A, it is first embodiment of data storage apparatus of the present invention.The data storage device of first embodiment is a master-slave mode trigger (master-slave flip flop), comprising: the ternary output logic element of one first not gate, 430, one first ternary output logic element (tri-state buffer), 432, one main latch 410, one second 434, is from latch 420, one the 3rd ternary output logic element 450, one second not gate 436.
Moreover, by Fig. 4 A as can be known, clock pulse path 412 comprises: a clock pulse signal (clk) inputs to non-one first clock pulse signal (nclk) of exporting behind the door, and first clock pulse signal (nclk) is imported another non-second clock pulse signal (bclk) of exporting behind the door, and first clock pulse signal (nclk) and second clock pulse signal (bclk) complementary (complement).Moreover, data are preserved signal path 414 and comprised: data preservation signals (ret) input to the non-reverse data of exporting behind the door and preserve signal (nret), and data preservation signals (ret) are preserved signal (nret) complementation (complement) with reverse data.Wherein, first ternary output logic element 432, the second ternary output logic element 434 is controlled by first clock pulse signal (nclk) and second clock pulse signal (bclk); And the 3rd ternary output logic element 432 is controlled by data preservation signals (ret) and reverse data preservation signal (nret).Moreover preserving signals (ret) when data be low level interval scale operator scheme, at this moment, first clock pulse signal (nclk) and second clock pulse signal (bclk) but normal running; Preserving signal (ret) when data is high level interval scale sleep pattern.
In Fig. 4 A, be connected in series between a data-signal (D) and the output (Q) first not gate, 430, the first ternary output logic element 432, main latch the 410, the 3rd ternary output logic element 450, the second ternary output logic element 434, with second not gate 436.And the input of second not gate 436 has a branch (branch), comprises from latch 420 in this branch.That is to say that data-signal (D) input to the data delivery path of output (Q) comprising: first not gate, 430, the first ternary output logic element 432, main latch the 410, the 3rd ternary output logic element 450, the second ternary output logic element 434, second not gate 436.Clearly, from latch 220 not on the data delivery path.
When operator scheme, data are preserved signals (ret) for low level and make the 3rd ternary output logic element 450.That is to say that the data on the data delivery path are along with first clock pulse signal (nclk) moves with the variation of second clock pulse signal (bclk) at this moment.
When sleep pattern, data preservation signals (ret) are for high level and make the 3rd ternary output logic element 450 be failure to actuate.That is to say that this moment the 3rd, ternary output logic element 450 can be blocked the data delivery path.And, therefore, can store data from latch 420 owing to provide power supply from latch 420.
Moreover the shadow region representative of Fig. 4 A needs the part of power supply supply when sleep pattern.That is to say that when sleep pattern, the part of power supply supply comprises: element, data on latch the 420, the 3rd ternary output logic element 450, clock pulse path 412 are preserved the element on the signal path 414.
Please refer to Fig. 4 B, it is the ternary output logic element circuitry of the present invention figure.That is, first ternary output logic element 432, second ternary output logic element the 434, the 3rd ternary output logic element 450 can be transmission gate (transmission gate).Perhaps, please refer to Fig. 4 C, it is the another kind of circuit diagram of the ternary output logic element of the present invention.That is, first ternary output logic element 432, second ternary output logic element the 434, the 3rd ternary output logic element 450 can be by a gate, and for example not gate (not gate) is connected in series a transmission gate (transmission gate).
Please refer to Fig. 5 A, it is second embodiment of data storage apparatus of the present invention.The data storage device of second embodiment is a master-slave mode trigger (master-slave flip flop), comprising: the ternary output logic element of the ternary output logic element of one first not gate 530, one first 532, a main latch 510, one second 534, is from latch 520, one the 3rd ternary output logic element 550, one second not gate 536.
In like manner, data-signal (D) input to the data delivery path of output (Q) comprising: first not gate, 530, the first ternary output logic element 532, main latch the 510, the 3rd ternary output logic element 550, the second ternary output logic element 534, second not gate 536.Clearly, from latch 320 not on the data delivery path.
Be compared to Fig. 4 A, its difference is can make that from the structure of latch 520 when the sleep pattern, the element on the clock pulse path 512 can not need to be powered, can be so that from latch 520 storage data, reach more purpose of power saving.That is, the representative of the shadow region of Fig. 5 A needs the part of power supply supply when sleep pattern.That is to say that when sleep pattern, the part of power supply supply comprises: preserve the element on the signal path 514 from latch the 520, the 3rd ternary output logic element 550, data.
Please refer to Fig. 5 B, it is the ternary output logic element circuitry of the present invention figure.That is, first ternary output logic element 532, second ternary output logic element the 534, the 3rd ternary output logic element 550 can be transmission gate (transmission gate).Perhaps, please refer to Fig. 5 C, it is the another kind of circuit diagram of the ternary output logic element of the present invention.That is, first ternary output logic element 532, second ternary output logic element the 534, the 3rd ternary output logic element 550 can be by a gate, and for example not gate (not gate) is connected in series a transmission gate (transmission gate).
Because the of the present invention the 3rd ternary output logic element is to be positioned to make only have in the branch from latch 520 and also can reach the purpose that data are preserved when the sleep pattern on the data delivery path.Clearly, data storage apparatus structure of the present invention is different from known data storage apparatus.
Be compared to the known technology of Fig. 2/Fig. 3, the present invention has following two advantages at least.At first, the present invention can simplify the required sequencing control mechanism of switching between sleep pattern/operator scheme.In general, the data storage apparatus that the present invention mentions other the circuit of can arranging in pairs or groups, such as be buffer circuit (isolation cell), correctly operate so that when sleep pattern/operator scheme is switched, keep data.Such as this buffer circuit can be connected to the output Q of data storage apparatus, and this buffer circuit can receive the data output of data storage apparatus in output Q according to the control/triggering of an isolation control signal.But, if the given data save set among Fig. 2/Fig. 3 that will arrange in pairs or groups just must produce an extra isolation control signal separately; This isolation control signal must and data preserve suitable delay arranged between signal ret, can not directly preserve signal ret (or signal synchronous) and be used as isolation control signal with it with data.This is because in the known technology of Fig. 2/Fig. 3, in the time will returning to operator scheme by sleep pattern, data are preserved signal ret and are wanted the ternary element 250/350 of first conducting, the transfer of data that could will preserve from latch 220/320 is to the data delivery path, so also need the time of one section delay transfer of data could be arrived output Q.Also therefore, the buffer circuit that is connected output Q will be controlled with the isolation control signal of an extra delay, could the correct dateout that receives from latch 220/320.This extra isolation control signal that produces will increase the complexity of sequencing control mechanism undoubtedly.
Relatively, utilize data storage apparatus of the present invention, just can directly preserve signal ret (or other signals synchronous) and be used as isolation control signal with the buffer circuit of control connection at output Q with it with data.Because of the present invention is to be directly connected on the data delivery path from latch 420/520, so when returning to operator scheme by sleep pattern, control buffer circuit, the data that buffer circuit access is correctly preserved as long as directly preserve signal ret from latch with data.That is to say that the present invention can simplify the sequencing control mechanism between sleep pattern/operator scheme switching, reduces circuit complexity and cost.
Another advantage of the present invention, then be can be certain make clear and definite sequential according to circuit running characteristic (similarly being transistor driving ability or the like) for data storage apparatus of the present invention and limit (timing constraint).Known to IC design field technical staff, clear and definite sequential restriction is the important evidence of checking winding placement in the IC design; Concerning the data save set, clear and definite sequential restriction has been arranged, can guarantee just whether sequencing control is correct.Such as, but the mutual sequential relationship between clear and definite sequential restriction standard clock pulse, data preservation signal ret and data, the time sequences that makes data storage apparatus is clear and definite expected.
Yet the given data save set in Fig. 2/Fig. 3, the defective on its circuit arrangement but makes it be difficult to come element characteristicization (cell characterization) to go out clear and definite sequential restriction according to circuit running characteristic.With the known technology among Fig. 2 is example, because two ternary element 234,250 is controlled two independently data delivery paths respectively, so the sequential dependence relation that clock pulse clk and data are preserved between signal ret also becomes indeterminate.Also therefore, try to achieve clear and definite sequential restriction, have actual difficulty, and then influence the correctness in circuit design/checking/enforcement at the known technology among Fig. 2/Fig. 3.
Under comparing, the present invention just successfully element characteristicization (cell characterization) go out clear and definite sequential restriction (relation of ret and clk).Because two ternary element controls of the present invention is same data delivery path, so the sequential dependence relation that clock pulse clk/nclk and data are preserved between signal ret can positively dissolve according to circuit running characteristic element characteristic, for data storage apparatus of the present invention defines clear and definite sequential restriction, and then the correctness of promoting circuit design/checking/enforcement.
In sum; though the present invention with the preferred embodiment explanation as above; yet it is not in order to limit the present invention; any those skilled in the art; do not breaking away within the spirit and scope of the present invention; can do various changes and retouching, therefore, protection scope of the present invention is as the criterion when looking the scope that accompanying Claim defines.
Claims (5)
1. data storage apparatus comprises:
One clock pulse path can receive a clock pulse signal, and according to complementary one first clock pulse signal and the second clock pulse signal of this clock pulse signal output;
One first latch is controlled by this first clock pulse signal and second clock pulse signal, and according to this first clock pulse signal and second clock pulse signal storage data;
One data delivery path, between a data input pin and a data output end, and this first latch is arranged between this data input pin and this data output end, makes a data-signal can import this data input pin and be stored in this first latch and be passed to this data output end along this data delivery path according to this first clock pulse signal and second clock pulse signal;
One second latch be connected in this data passes path in a node, and this node is arranged between this first latch and this data output end, makes this second latch preserve signal according to data and keeps this data-signal when the sleep pattern; And
One ternary output logic element, this three-state output logic arrangements of components are on this data passes path and be controlled by this data preservation signal, make this three-state output logic element can block this data delivery path when this sleep pattern.
2. data storage apparatus as claimed in claim 1, wherein this first latch is a main latch, and this second latch is one from latch.
3. data storage apparatus as claimed in claim 1 should three-state output logic element be a transmission gate wherein.
4. data storage apparatus as claimed in claim 1 should three-state output logic element be that a gate is connected in series a transmission gate wherein.
5. data storage apparatus as claimed in claim 4, wherein this gate is a not gate.
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| CN2008100886661A CN101252349B (en) | 2008-04-10 | 2008-04-10 | Data storage apparatus of multi-power supply area |
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