CN105870201B - TFT device structure and fabrication method thereof - Google Patents
TFT device structure and fabrication method thereof Download PDFInfo
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- CN105870201B CN105870201B CN201610404269.5A CN201610404269A CN105870201B CN 105870201 B CN105870201 B CN 105870201B CN 201610404269 A CN201610404269 A CN 201610404269A CN 105870201 B CN105870201 B CN 105870201B
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- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 238000000034 method Methods 0.000 title description 17
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 87
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 63
- 239000010703 silicon Substances 0.000 claims abstract description 63
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 408
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 46
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 22
- 239000011229 interlayer Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229910052750 molybdenum Inorganic materials 0.000 claims description 22
- 239000011733 molybdenum Substances 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- 239000004411 aluminium Substances 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 13
- 239000002356 single layer Substances 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 abstract description 27
- 229910017083 AlN Inorganic materials 0.000 abstract description 26
- 239000000463 material Substances 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 11
- -1 silicon oxide compound Chemical class 0.000 abstract description 8
- 239000000126 substance Substances 0.000 abstract description 8
- 238000002955 isolation Methods 0.000 abstract description 7
- 229910021645 metal ion Inorganic materials 0.000 abstract description 7
- 230000008646 thermal stress Effects 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 238000003486 chemical etching Methods 0.000 abstract description 3
- 238000002360 preparation method Methods 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 28
- 239000010408 film Substances 0.000 description 23
- 229910052593 corundum Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 229910001845 yogo sapphire Inorganic materials 0.000 description 12
- 229910004205 SiNX Inorganic materials 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 239000013077 target material Substances 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 2
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 241000894007 species Species 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 125000004494 ethyl ester group Chemical group 0.000 description 1
- 208000021760 high fever Diseases 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
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- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of TFT device architecture and preparation method thereof.TFT device architecture of the invention, using the insulating medium layer for the double-layer structure that alumina layer is superimposed with aln layer, since aluminium oxide has excellent isolation steam, the characteristic of each metal ion species, and have strong resistant to chemical etching, the features such as high thermal stability, the alumina layer can be good at protecting semiconductor layer and TFT device, and aluminium nitride has good electrical conductivity and chemical stability, good contact interface can be formed with silicon, the aln layer being superimposed on the alumina layer can eliminate the thermal stress of alumina layer and silicon interface, and it prevents from forming silicon oxide compound at interface under high temperature, in addition, aluminium oxide can be formed a film with aluminium nitride by simple magnetron sputtering or CVD mode, therefore compared to traditional TFT device architecture, with lower material technology cost, properties of product are more excellent.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of TFT device architecture and preparation method thereof.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, TFT) is current liquid crystal display device (Liquid Crystal
Display, LCD) and active matrix drive type organic electroluminescence display device and method of manufacturing same (Active Matrix Organic Light-
Emitting Diode, AMOLED) in main driving element, the display performance of direct relation panel display apparatus.
Thin film transistor (TFT) has various structures, and the material for preparing the thin film transistor (TFT) of corresponding construction also has a variety of, low temperature
Polysilicon (Low Temperature Poly Silicon, LTPS) be it is wherein more preferred a kind of, due to low temperature polycrystalline silicon
Atomic rule arrangement, carrier mobility is high, and for the liquid crystal display device of voltage driven type, low-temperature polysilicon film is brilliant
Body pipe is due to its mobility with higher.The electron mobility of traditional amorphous silicon material is about 0.5-1.0cm2/V.S, and
The electron mobility of low temperature polycrystalline silicon is up to 30-300cm2/V.S.Therefore LTPS-TFT LCD has high-res, reaction speed
Fastly, the advantages that high aperture, high-end handsets are widely used in, on tablet computer.
Silicon nitride (SiNx) layer, silica (SiO2) layer, silicon oxynitride would generally be used in the processing procedure of TFT device
(SiON) layer or its stepped construction are as dielectric, to play the functions such as insulation, barrier ion.
As shown in Figure 1, being the structure chart of existing LTPS-TFT device, comprising: including underlay substrate 100, be set to institute
State patterned light shield layer 200 on underlay substrate 100, the covering light shield layer 200 and underlay substrate 100 buffer layer 300,
Low-temperature polysilicon silicon semiconductor layer 400, the covering low temperature above the light shield layer 200 on the buffer layer 300 is more
Crystal silicon semiconductor layer 400 is set to the gate insulating layer 500 of buffer layer 300, above the low-temperature polysilicon silicon semiconductor layer 400
Grid 600 on the gate insulating layer 500, the covering grid 600 and gate insulating layer 500 interlayer insulating film 700, with
And the source electrode 910 on the interlayer insulating film 700 and drain electrode 920.Wherein, buffer layer 300 is generally bis- using SiNx/SiO2
Layer structure, SiNx layer mainly plays blocking ionization, prevents boron, sodium, potassium plasma pollutant from entering semiconductor layer, and SiO2 layers
The main threshold voltage (Vth) for influencing LTPS-TFT device generally uses high-cost positive silicic acid to guarantee the performance of device
Ethyl ester (TEOS) makes the SiO2 layers, to improve the cost of manufacture of LTPS-TFT device.
As shown in Fig. 2, being the structure chart of existing a-Si (amorphous silicon) TFT device, comprising: underlay substrate 100 ' is set to
Grid 200 ' on underlay substrate 100 ' covers the gate insulating layer 300 ' of the grid 200 ' and underlay substrate 100 ', in institute
It states the amorphous silicon semiconductor layer 400 ' being set on gate insulating layer 300 ' above grid 200 ', be set to the amorphous silicon semiconductor layer
Source electrode 510 ' and drain electrode 520 ' on 400 '.Because gate insulating layer 300 ' requires have excellent insulation performance, high field breakdown strong
The characteristics such as degree, low electronic defects density and high dielectric constant, and it also requires having with amorphous silicon semiconductor layer 400 ' good
Interfacial contact, so gate insulating layer 300 ' generally using SiNx, SiON, SiO2 material and passes through plasma enhanced chemical gas
Phase sedimentation (Plasma Enhanced Chemical Vapor Deposition, PECVD) deposition is formed in underlay substrate
On 100 '；And as TFT device size constantly reduces, the thickness of gate insulating layer 300 ' will also reduce therewith, then will will appear
The problems such as leakage current increase, impurity diffusion, and pecvd process is high to the purity requirement of gas, equipment cost is high, in coating mistake
The violent noise, high light radiation, metallic vapour dust etc. being harmful to the human body can be also generated in journey.
Summary of the invention
The purpose of the present invention is to provide a kind of TFT device architecture, the Al being superimposed using alumina layer with aln layer2O3/
The insulating medium layer of AlN double-layer structure, process costs are low, and properties of product are excellent.
Another object of the present invention is to provide a kind of production methods of TFT device, using alumina layer and aln layer
The Al of superposition2O3The insulating medium layer of/AlN double-layer structure, process costs are low, properties of product are excellent.
To achieve the above object, present invention firstly provides a kind of TFT device architecture, including insulating medium layer, the insulation
Dielectric layer includes the alumina layer and aln layer set gradually from bottom to top.
Optionally, the TFT device architecture further includes underlay substrate, light shield layer, low-temperature polysilicon silicon semiconductor layer, grid
Insulating layer, grid, interlayer insulating film, source electrode and drain electrode；
The light shield layer is set on the underlay substrate；The insulating medium layer is set to the shading as buffer layer
On layer and underlay substrate and cover the light shield layer and underlay substrate；The low-temperature polysilicon silicon semiconductor layer corresponds to the screening
It is set on the insulating medium layer above photosphere；The gate insulating layer be set to the low-temperature polysilicon silicon semiconductor layer with it is described
On insulating medium layer and cover the low-temperature polysilicon silicon semiconductor layer and the insulating medium layer；The grid corresponds to described
Above low-temperature polysilicon silicon semiconductor layer and it is set on the gate insulating layer；The interlayer insulating film is located at the grid and grid
On the insulating layer of pole and cover the grid and gate insulating layer；Correspond on the interlayer insulating film and gate insulating layer described
The both ends of polysilicon semiconductor layer are equipped with the first via hole, the second via hole, and the source electrode, drain electrode are set on the interlayer insulating film simultaneously
The both ends of low-temperature polysilicon silicon semiconductor layer are contacted by first via hole, the second via hole respectively.
The grid, source electrode are superimposed with drain electrode for the single layer structure that is made of molybdenum layer or with aluminium layer by molybdenum layer and are constituted
Double-layer structure.
Optionally, the TFT device architecture further includes underlay substrate, grid, amorphous silicon semiconductor layer, source electrode and leakage
Pole；
The grid is set on the underlay substrate；The insulating medium layer is set to the grid as gate insulating layer
On pole and underlay substrate and cover the grid and underlay substrate；The amorphous silicon semiconductor layer corresponds to above the grid
And it is set on insulating medium layer；The source electrode, drain electrode are set on the insulating medium layer and amorphous silicon semiconductor layer and divide
It is not in contact with the amorphous silicon semiconductor layer both ends.
The source electrode and drain electrode are tied for the single layer structure being made of molybdenum layer or the bilayer for being superimposed with aluminium layer by molybdenum layer and being constituted
Structure.
The present invention also provides a kind of production method of TFT device, including using magnetron sputtering mode or CVD mode from lower and
On the step of being sequentially depositing alumina layer and aln layer, alumina layer and aln layer is made to collectively constitute insulating medium layer.
Optionally, the production method of the TFT device, specifically comprises the following steps:
Step 1 provides a underlay substrate, and patterned light shield layer is formed on the underlay substrate；
Step 2 uses magnetron sputtering mode or CVD mode successively to sink from bottom to top on the light shield layer and underlay substrate
Product alumina layer and aln layer, the alumina layer and aln layer collectively constitute insulating medium layer；
The insulating medium layer covers the light shield layer and underlay substrate as buffer layer；
Step 3 forms the low-temperature polysilicon silicon semiconductor layer for corresponding to the light shield layer on the insulating medium layer；
Step 4, the deposition covering gate insulating layer in the low-temperature polysilicon silicon semiconductor layer and insulating medium layer, described
The first metal layer is deposited and patterned on gate insulating layer, forms the grid being located above low-temperature polysilicon silicon semiconductor layer；
Step 5, the deposition covering interlayer insulating film on the grid and gate insulating layer, to the interlayer insulating film and grid
Pole insulator layer etch forms the first via hole and the second mistake for exposing low-temperature polysilicon silicon semiconductor layer both ends surface respectively
Hole；
Second metal layer is deposited and patterned in step 6 on the interlayer insulating film, forms source electrode and drain electrode, the source
Pole, drain electrode contact the low-temperature polysilicon silicon semiconductor layer by the first via hole, the second via hole respectively.
The first metal layer with second metal layer be the single layer structure being made of molybdenum layer or be superimposed by molybdenum layer with aluminium layer and
The double-layer structure of composition.
Optionally, the production method of the TFT device, specifically comprises the following steps:
Step 1 ', a underlay substrate is provided, be deposited and patterned the first metal layer in the underlay substrate, form grid；
Step 2 ', successively sunk from bottom to top using magnetron sputtering mode or CVD mode on the grid and underlay substrate
Product alumina layer and aln layer, the alumina layer and aln layer collectively constitute insulating medium layer；
The insulating medium layer covers the grid and underlay substrate as gate insulating layer；
Step 3 ', on the insulating medium layer formed correspond to the grid amorphous silicon semiconductor layer；
Step 4 ', on the amorphous silicon semiconductor layer and insulating medium layer second metal layer is deposited and patterned, formed
Source electrode and drain electrode.
The second metal layer be the single layer structure being made of molybdenum layer or be superimposed by molybdenum layer with aluminium layer and the double-deck knot that constitutes
Structure.
Beneficial effects of the present invention: TFT device architecture of the invention is superimposed using alumina layer with aln layer
Al2O3The insulating medium layer of/AlN double-layer structure, it is exhausted as the buffer layer of LTPS-TFT device or the grid of a-Si TFT device
Edge layer since aluminium oxide has the characteristic of excellent isolation steam, each metal ion species, and has strong resistant to chemical etching, high fever
The features such as stability, the alumina layer can be good at protecting semiconductor layer and TFT device, and aluminium nitride has good heat
Electric conductivity and chemical stability can form good contact interface with silicon, the aln layer energy being superimposed on the alumina layer
The thermal stress of alumina layer and silicon interface is enough eliminated, and prevents from forming silicon oxide compound at interface under high temperature, in addition, aluminium oxide
It can be formed a film by simple magnetron sputtering or CVD mode with aluminium nitride, therefore compared to traditional TFT device architecture,
With lower material technology cost, properties of product are more excellent.The production method of TFT device of the invention, using aluminium oxide
The insulating medium layer for the double-layer structure that layer is superimposed with aln layer, material technology is at low cost, and properties of product are excellent.
Detailed description of the invention
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
In attached drawing,
Fig. 1 is the structural schematic diagram of existing LTPS-TFT device；
Fig. 2 is the structural schematic diagram of existing a-Si TFT device；
Fig. 3 is the schematic diagram of TFT device architecture first embodiment of the invention；
Fig. 4 is the schematic diagram of TFT device architecture second embodiment of the invention；
Fig. 5 is the flow diagram of the first embodiment of TFT device manufacture method of the invention；
Fig. 6 is the schematic diagram of the step 1 of the first embodiment of TFT device manufacture method of the invention；
Fig. 7 is the signal of aluminum oxide layer in the step 2 of the first embodiment of TFT device manufacture method of the invention
Figure；
Fig. 8 is the signal of cvd nitride aluminium layer in the step 2 of the first embodiment of TFT device manufacture method of the invention
Figure；
Fig. 9 is the flow diagram of the second embodiment of TFT device manufacture method of the invention；
Figure 10 be TFT device manufacture method of the invention second embodiment step 1 ' schematic diagram；
Figure 11 be TFT device manufacture method of the invention second embodiment step 2 ' in aluminum oxide layer signal
Figure；
Figure 12 be TFT device manufacture method of the invention second embodiment step 2 ' in cvd nitride aluminium layer signal
Figure.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
Referring to Fig. 3, the schematic diagram of the first embodiment for TFT device architecture of the invention, the TFT device architecture
It include: insulating medium layer 30, the insulating medium layer 30 includes the alumina layer 31 and aln layer set gradually from bottom to top
32。
Specifically, the present embodiment is unfolded based on LTPS-TFT device architecture, as shown in figure 3, the TFT device
Part structure specifically includes underlay substrate 10, the patterned light shield layer 20 on the underlay substrate 10, as buffer layer and
It covers the insulating medium layer 30 of the light shield layer 20 and underlay substrate 10, be set to the dielectric above the light shield layer 20
Low-temperature polysilicon silicon semiconductor layer 40, covering the low-temperature polysilicon silicon semiconductor layer 40 and the insulating medium layer 30 on layer 30
Gate insulating layer 50, covers the grid 60 being set on the gate insulating layer 50 above the low-temperature polysilicon silicon semiconductor layer 40
Cover the grid 60 and the interlayer insulating film 70 on gate insulating layer 50 and the source electrode 91 on the interlayer insulating film 70
With drain electrode 92.
Specifically, the interlayer insulating film 70 is equipped with the first via hole 71, the second via hole 72 with gate insulating layer 50, described
Source electrode 91, drain electrode 92 pass through the first via hole 71, the second via hole through the interlayer insulating film 70 and gate insulating layer 50 respectively
The both ends of 72 contact low-temperature polysilicon silicon semiconductor layers 40.The low-temperature polysilicon silicon semiconductor layer 40 can pass through for low-temperature polycrystalline silicon layer
N-type doping is formed, and can also adulterate to be formed through p-type for low-temperature polycrystalline silicon layer.
Specifically, due to aluminium oxide (Al2O3) there are the characteristics such as excellent isolation steam, metal ion, while having strong resistance to
The features such as chemical attack, high thermal stability, therefore the alumina layer 31 can be good at protecting low-temperature polysilicon silicon semiconductor layer
40 and TFT device.
Further, the water vapor transmittance of the SiNx of 500nm order of magnitude diameter is 10g/ (m2* d), the 130nm order of magnitude
The Al of diameter2O3Water vapor transmittance be 4.7*10-5g/(m2D), therefore thinner Al *2O3More it is able to satisfy current TFT device
The smaller and smaller trend of part size, while Al2O3It is also a kind of excellent transparent dielectric material, dielectric constant 9 is
3 times of SiNx can form good interfacial contact with silicon layer.
Further, aluminium nitride (AlN) has good electrical conductivity and chemical stability, can eliminate alumina layer 31
With the thermal stress of silicon interface, therefore, the aln layer 32 on alumina layer 31 can prevent 31 high temperature of alumina layer
Under low-temperature polysilicon silicon semiconductor layer 40 silicon interface formed contain silicon oxygen bond (Si-O) compound, and AlN also can and silicon layer
Form good contact interface.In addition, Al2O3Simple magnetron sputtering or the side CVD can be passed through with the film of AlN material
Formula film forming.
Further, since the double-layer structure that aln layer 32 is superimposed alumina layer 31 can be very good the blocking as Al
Layer, therefore, the metal layer on insulating medium layer 30 are not needed using traditional molybdenum/aluminium/molybdenum (Mo/Al/Mo) superposition three
Layer structure, i.e., the described grid 60, source electrode 91 can be the single layer structure being made of molybdenum layer with drain electrode 92 or be folded by molybdenum layer and aluminium layer
The Al/Mo double-layer structure for adding and constituting, so that TFT thickness of detector is thinner, cost is further decreased.
Therefore, the present embodiment is folded with alumina layer 31 and aln layer 32 compared to traditional LTPS-TFT device architecture
The Al added2O3The insulating medium layer 30 of/AlN double-layer structure is used as buffer layer, has lower material technology cost, properties of product
It is more excellent.
Referring to Fig. 4, the schematic diagram of the second embodiment for TFT device architecture of the invention, with above-mentioned first embodiment
It compares, which is a-Si TFT device architecture, and the insulating medium layer 30 is exhausted as the grid of a-Si TFT device architecture
Edge layer.
As shown in figure 4, the TFT device architecture of the present embodiment specifically includes underlay substrate 10 ', is set to the underlay substrate
Grid 20 ' on 10 ', the insulating medium layer 30 of the covering grid 20 ' and underlay substrate 10 ', on the grid 20 '
Side be set to insulating medium layer 30 on amorphous silicon semiconductor layer 40 ', be set to the amorphous silicon semiconductor layer 40 ' on source electrode 51 ',
And drain electrode 52 '.
Specifically, due to Al2O3With characteristics such as excellent isolation steam, metal ions, while having strong chemically-resistant rotten
The features such as erosion, high thermal stability, therefore the alumina layer 31 can be good at protecting amorphous silicon semiconductor layer 40 ' and TFT device
Part, while Al2O3It is also a kind of excellent transparent dielectric material, dielectric constant 9 is 3 times of SiNx, can be with silicon layer
Form good interfacial contact.
Further, AlN has good electrical conductivity and chemical stability, can eliminate alumina layer 31 and silicon interface
Thermal stress, therefore, the aln layer 32 on alumina layer 31 can prevent under 31 high temperature of alumina layer in amorphous
The silicon interface of silicon semiconductor layer 40 ' forms Si-O compound, and AlN can also form good contact interface with silicon layer.In addition,
Al2O3It can be formed a film by simple magnetron sputtering or CVD mode with the film of AlN material.
Further, since the double-layer structure that aln layer 32 is superimposed alumina layer 31 can be very good the blocking as Al
Layer, therefore, the metal layer on insulating medium layer 30 is not needed using traditional Mo/Al/Mo three-decker, i.e., the described source electrode
51 ' and drain electrode 52 ' can for the single layer structure that is made of molybdenum layer or be superimposed by molybdenum layer with aluminium layer and the Al/Mo bilayer knot that constitutes
Structure, so that TFT thickness of detector is thinner, cost is further decreased.
Therefore, the present embodiment is folded with alumina layer 31 and aln layer 32 compared to traditional a-Si TFT device architecture
The Al added2O3The insulating medium layer 30 of/AlN double-layer structure is used as gate insulating layer, has lower material technology cost, product
Performance is more excellent.
Referring to Fig. 5, the flow diagram of the first embodiment for the production method of TFT device of the invention, the implementation
Example is the production method of LTPS-TFT device, is specifically comprised the following steps:
Step 1, as shown in fig. 6, provide a underlay substrate 10, form patterned light shield layer on the underlay substrate 10
20。
Step 2, as Figure 7-8, the light shield layer 20 on underlay substrate 10 using magnetron sputtering mode from lower and
On be sequentially depositing alumina layer 31 and aln layer 32, the alumina layer 31 and aln layer 32 collectively constitute dielectric
Layer 30.
Specifically, the insulating medium layer 30 is used as buffer layer, covers the light shield layer 20 and underlay substrate 10.
Specifically, using the specific steps of magnetron sputtering mode aluminum oxide layer 31 are as follows: use Al as target, i.e., it is high
The target material of fast lotus energy particle bombardment, while argon gas and oxygen are injected, argon ion accelerates to fly to cathode under the action of electric field
Target, and target material surface is bombarded with high-energy, so that target as sputter is gone out Al ion, Al ion and oxygen react to form Al2O3Deposition
Alumina layer 31 is formed on underlay substrate 10；This mode is with equipment is simple, easily controllable, plated film area is big and adhesive force is strong
The advantages that, so that process costs are lower, performance is more excellent.
Specifically, using the specific steps of magnetron sputtering mode cvd nitride aluminium layer 32 are as follows: use Al as target, i.e., it is high
The target material of fast lotus energy particle bombardment, while argon gas and nitrogen are injected, argon ion accelerates to fly to cathode under the action of electric field
Target, and target material surface is bombarded with high-energy, so that target as sputter is gone out Al ion, Al ion and nitrogen react to form AlN deposition
Aln layer 32 is formed on alumina layer 31.
Step 3 forms the low-temperature polysilicon silicon semiconductor layer for corresponding to the light shield layer 20 on the insulating medium layer 30
40。
Specifically, the technical process for forming low-temperature polysilicon silicon semiconductor layer 40 is no different with the prior art: first deposited amorphous silicon
Layer then carries out Crystallizing treatment to amorphous silicon layer and forms low-temperature polycrystalline silicon layer, then patterned polysilicon layer, then to polysilicon layer
Ion doping is carried out, the low-temperature polysilicon silicon semiconductor layer 40 including heavily doped region, lightly doped district and channel region is formed.
Certainly, the ion doping is not limited to the n-type doping using phosphonium ion, is also not necessarily limited to mix using the p-type of boron ion
It is miscellaneous, correspondingly, the TFT in final low temperature polycrystalline silicon tft array substrate obtained can be N-type TFT, it can also be p-type TFT.
Step 4 covers gate insulating layer 50 in the low-temperature polysilicon silicon semiconductor layer 40 and deposition on insulating medium layer 30,
The first metal layer is deposited and patterned on the gate insulating layer 50, is formed and is located at 40 top of low-temperature polysilicon silicon semiconductor layer
Grid 60.
Step 5 covers interlayer insulating film 70 in the grid 60 and deposition on gate insulating layer 50, to the layer insulation
Layer 70 and gate insulating layer 50 etch, and formation exposes the first of 40 liang of end surfaces of low-temperature polysilicon silicon semiconductor layer respectively
Via hole 71 and the second via hole 72.
Second metal layer is deposited and patterned in step 6 on the interlayer insulating film 70, forms source electrode 91 and drain electrode 92,
The source electrode 91, drain electrode 92 contact the low-temperature polysilicon silicon semiconductor layer 40 by the first via hole 71, the second via hole 72 respectively.
Specifically, due to Al2O3With characteristics such as excellent isolation steam, metal ions, while having strong chemically-resistant rotten
The features such as erosion, high thermal stability, therefore the alumina layer 31 can be good at protecting low-temperature polysilicon silicon semiconductor layer 40 and TFT
Device, while Al2O3It is also a kind of excellent transparent dielectric material, dielectric constant 9 is 3 times of SiNx, can be with silicon
Layer forms good interfacial contact.
Further, AlN has good electrical conductivity and chemical stability, can eliminate alumina layer 31 and silicon interface
Thermal stress, therefore, the aln layer 32 on alumina layer 31 can prevent under 31 high temperature of alumina layer in low temperature
The silicon interface of polysilicon semiconductor layer 40 forms Si-O compound, and AlN can also form good contact interface with silicon layer.
In addition, the present embodiment forms alumina layer 31 and aln layer 32 using magnetron sputtering, compared to PECVD mode
It is more simple, effectively reduce production cost.
Further, since the double-layer structure that aln layer 32 is superimposed alumina layer 31 can be very good the blocking as Al
Layer, therefore, the metal layer on insulating medium layer 30 are not needed using traditional Mo/Al/Mo three-decker, i.e., and described first
Metal layer can be bis- for the single layer structure being made of molybdenum layer or the Al/Mo for being superimposed with aluminium layer by molybdenum layer and being constituted with second metal layer
Layer structure, so that TFT thickness of detector is thinner, cost is further decreased.
Therefore, the present embodiment using alumina layer 31 and is nitrogenized compared to the production method of traditional LTPS-TFT device
The Al that aluminium layer 32 is superimposed2O3The insulating medium layer 30 of/AlN double-layer structure is used as buffer layer, has lower material technology cost,
Properties of product are more excellent.
Referring to Fig. 9, the flow diagram of the second embodiment for the production method of TFT device of the invention, and above-mentioned
First embodiment is compared, and the present embodiment is the production method of a-Si TFT device, is specifically comprised the following steps:
Step 1 ', as shown in Figure 10, a underlay substrate 10 ' is provided, is deposited and patterned first in the underlay substrate 10 '
Metal layer forms grid 20 '.
Step 2 ', as depicted in figs. 11-12, chemical vapor deposition is used on grid 20 ' and underlay substrate 10 '
(Chemical Vapor Deposition, CVD) mode is sequentially depositing alumina layer 31 and aln layer 32, institute from bottom to top
It states alumina layer 31 and aln layer 32 collectively constitutes insulating medium layer 30.
Specifically, the insulating medium layer 30 is used as gate insulating layer, covers the grid 20 ' and underlay substrate 10 '.
Specifically, the present embodiment forms alumina layer 31 and aln layer 32 using CVD mode, compared to PECVD mode
It is more simple, effectively reduce production cost.
Step 3 ', on the insulating medium layer 30 formed correspond to the grid 20 ' amorphous silicon semiconductor layer 40 '.
Step 4 ', on the amorphous silicon semiconductor layer 40 ' and insulating medium layer 30 second metal layer is deposited and patterned,
Form source electrode 51 ' and drain electrode 52 '.
Specifically, due to Al2O3With characteristics such as excellent isolation steam, metal ions, while having strong chemically-resistant rotten
The features such as erosion, high thermal stability, therefore the alumina layer 31 can be good at protecting low-temperature polysilicon silicon semiconductor layer 40 and TFT
Device, while Al2O3It is also a kind of excellent transparent dielectric material, dielectric constant 9 is 3 times of SiNx, can be with silicon
Layer forms good interfacial contact.
Further, AlN has good electrical conductivity and chemical stability, can eliminate Al2O3It is answered with the heat of silicon interface
Power, therefore, the aln layer 32 on alumina layer 31 can prevent from partly leading under 31 high temperature of alumina layer in amorphous silicon
The silicon interface of body layer 40 ' forms Si-O compound, and AlN can also form good contact interface with silicon layer.
Further, since the double-layer structure that aln layer 32 is superimposed alumina layer 31 can be very good the blocking as Al
Layer, therefore, the metal layer on insulating medium layer 30 are not needed using traditional Mo/Al/Mo three-decker, i.e., and described second
Metal layer can for the single layer structure that is made of molybdenum layer or be superimposed by molybdenum layer with aluminium layer and the Al/Mo double-layer structure that constitutes, thus
So that TFT thickness of detector is thinner, cost is further decreased.
Therefore, the present embodiment compared to traditional a-Si TFT device production method, with alumina layer 31 and aluminium nitride
The Al of 32 superposition of layer2O3The insulating medium layer 30 of/AlN double-layer structure be used as gate insulating layer, have lower material technology at
This, properties of product are more excellent.
In conclusion TFT device architecture of the invention, the Al being superimposed using alumina layer with aln layer2O3/ AlN is double-deck
The insulating medium layer of structure, as the buffer layer of LTPS-TFT device or the gate insulating layer of a-Si TFT device, due to oxygen
Change the characteristic that aluminium has excellent isolation steam, each metal ion species, and there are the spies such as strong resistant to chemical etching, high thermal stability
Point, the alumina layer can be good at protecting semiconductor layer and TFT device, and aluminium nitride has good electrical conductivity and change
Stability is learned, good contact interface can be formed with silicon, the aln layer being superimposed on the alumina layer can eliminate oxidation
The thermal stress of aluminium layer and silicon interface, and prevent from forming silicon oxide compound at interface under high temperature, in addition, aluminium oxide is equal with aluminium nitride
It can be formed a film by simple magnetron sputtering or CVD mode, therefore compared to traditional TFT device architecture, had lower
Material technology cost, properties of product are more excellent.The production method of TFT device of the invention, using alumina layer and aluminium nitride
The insulating medium layer of the double-layer structure of layer superposition, material technology is at low cost, and properties of product are excellent.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the appended right of the present invention
It is required that protection scope.
Claims (4)
1. a kind of TFT device architecture, which is characterized in that including insulating medium layer (30), the insulating medium layer (30) includes certainly
The alumina layer (31) and aln layer (32) set gradually on down；
The TFT device architecture further includes underlay substrate (10), light shield layer (20), low-temperature polysilicon silicon semiconductor layer (40), grid
Insulating layer (50), grid (60), interlayer insulating film (70), source electrode (91) and drain electrode (92)；
The light shield layer (20) is set on the underlay substrate (10)；The insulating medium layer (30) is used as buffer layer, is set to
On the light shield layer (20) and underlay substrate (10) and cover the light shield layer (20) and underlay substrate (10)；The low temperature is more
Crystal silicon semiconductor layer (40), which corresponds to above the light shield layer (20), to be set on the insulating medium layer (30)；The grid is exhausted
Edge layer (50) is set on the low-temperature polysilicon silicon semiconductor layer (40) and the insulating medium layer (30) and covers the low temperature
Polysilicon semiconductor layer (40) and the insulating medium layer (30)；The grid (60) corresponds to the low-temperature polysilicon silicon semiconductor
Above layer (40) and it is set on the gate insulating layer (50)；The interlayer insulating film (70) is located at the grid (60) and grid
On pole insulating layer (50) and cover the grid (60) and gate insulating layer (50)；The interlayer insulating film (70) and grid are exhausted
Both ends in edge layer (50) corresponding to the polysilicon semiconductor layer (40) are equipped with the first via hole (71), the second via hole (72), institute
State source electrode (91), drain electrode (92) is set on the interlayer insulating film (70) and respectively by first via hole (71), the second mistake
Hole (72) contacts the both ends of low-temperature polysilicon silicon semiconductor layer (40).
2. TFT device architecture as described in claim 1, which is characterized in that the grid (60), source electrode (91) and drain electrode
(92) for the single layer structure that is made of molybdenum layer or be superimposed by molybdenum layer with aluminium layer and the double-layer structure that constitutes.
3. a kind of production method of TFT device, which is characterized in that including using magnetron sputtering mode or CVD mode from bottom to top
It is sequentially depositing alumina layer (31) and aln layer (32), alumina layer (31) and aln layer (32) is made to collectively constitute insulation
The step of dielectric layer (30)；
Specifically comprise the following steps:
Step 1 provides a underlay substrate (10), and patterned light shield layer (20) are formed on the underlay substrate (10)；
Step 2, on the light shield layer (20) and underlay substrate (10) using magnetron sputtering mode or CVD mode from bottom to top according to
Secondary aluminum oxide layer (31) and aln layer (32), the alumina layer (31) and aln layer (32) collectively constitute insulation
Dielectric layer (30)；
The insulating medium layer (30) is used as buffer layer, covers the light shield layer (20) and underlay substrate (10)；
Step 3 forms the low-temperature polysilicon silicon semiconductor layer for corresponding to the light shield layer (20) on the insulating medium layer (30)
(40)；
Step 4, the deposition covering gate insulating layer on the low-temperature polysilicon silicon semiconductor layer (40) and insulating medium layer (30)
(50), the first metal layer is deposited and patterned on the gate insulating layer (50), is formed and is located at low-temperature polysilicon silicon semiconductor layer
(40) grid (60) above；
Step 5, deposition covering interlayer insulating film (70) on the grid (60) and gate insulating layer (50), it is exhausted to the interlayer
Edge layer (70) and gate insulating layer (50) etching, formation expose (40) two end surfaces of low-temperature polysilicon silicon semiconductor layer respectively
The first via hole (71) and the second via hole (72)；
Second metal layer is deposited and patterned in step 6 on the interlayer insulating film (70), forms source electrode (91) and drains
(92), the source electrode (91), drain electrode (92) contact the low temperature polycrystalline silicon by the first via hole (71), the second via hole (72) respectively
Semiconductor layer (40).
4. the production method of TFT device as claimed in claim 3, which is characterized in that the first metal layer and the second metal
Layer for the single layer structure that is made of molybdenum layer or be superimposed by molybdenum layer with aluminium layer and the double-layer structure that constitutes.
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