[go: up one dir, main page]

CN105870165A - InAlN/GaN HEMT device comprising barrier layer with gradually varied components - Google Patents

InAlN/GaN HEMT device comprising barrier layer with gradually varied components Download PDF

Info

Publication number
CN105870165A
CN105870165A CN201610348582.1A CN201610348582A CN105870165A CN 105870165 A CN105870165 A CN 105870165A CN 201610348582 A CN201610348582 A CN 201610348582A CN 105870165 A CN105870165 A CN 105870165A
Authority
CN
China
Prior art keywords
layer
gan
inaln
composition
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610348582.1A
Other languages
Chinese (zh)
Inventor
任舰
顾晓峰
闫大为
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangnan University
Original Assignee
Jiangnan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangnan University filed Critical Jiangnan University
Priority to CN201610348582.1A priority Critical patent/CN105870165A/en
Publication of CN105870165A publication Critical patent/CN105870165A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/852Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/854Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种势垒层组分渐变的InAlN/GaN HEMT器件。该器件包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,SiN钝化层以及其上形成的栅极、源极和漏极,其特征是底层In0.17Al0.83N势垒与GaN材料形成晶格匹配,通过逐层增加In组分,增加极化效应产生的二维电子气浓度,提高器件的饱和电流和输出功率。本发明在减少异质界面形成线性位错和抑制逆压电效应的同时,有效提高了InAlN/GaN HEMT器件的电学性能。

The invention discloses an InAlN/GaN HEMT device with gradually changing components of the barrier layer. The device includes a GaN nucleation layer, a GaN buffer layer, an AlN insertion layer, an InAlN barrier layer with a graded In composition, a GaN cap layer, a SiN passivation layer, and gate and source electrodes formed on the substrate material in sequence. And the drain, which is characterized by the underlying In 0.17 Al 0.83 N barrier and the GaN material to form a lattice match, by increasing the In composition layer by layer, increasing the two-dimensional electron gas concentration generated by the polarization effect, and improving the saturation current and output of the device power. The invention effectively improves the electrical performance of the InAlN/GaN HEMT device while reducing the formation of linear dislocations at the heterogeneous interface and suppressing the inverse piezoelectric effect.

Description

一种势垒层组分渐变的InAlN/GaN HEMT器件A InAlN/GaN HEMT Device with Gradient Barrier Layer Composition

技术领域technical field

本发明涉及半导体功率器件制造领域,尤其涉及一种势垒层组分渐变的InAlN/GaNHEMT器件。The invention relates to the field of manufacturing semiconductor power devices, in particular to an InAlN/GaN HEMT device with a gradient composition of a barrier layer.

背景技术Background technique

与传统窄禁带半导体相比,以GaN为代表的宽禁带III族氮化物半导体具有高击穿电场、高电子饱和速度与高热稳定性等优越的电学特性。尤其是压电与自发极化效应显著的AlGaN/GaN异质结,能在界面处诱导高浓度的二维电子气(2DEG),是HEMT的核心结构。目前,已报道的AlGaN/GaN HEMT的截止频率超过100GHz,最大输出功率接近10W/mm。但是,由于AlGaN和GaN两种材料之间存在晶格失配,材料生长过程中会引入的大量的线性位错,导致器件漏电流比理论值大很多。很多针对AlGaN/GaN HEMT栅反向漏电流电流的研究指出,异质界面之间的线性位错是其漏电流的主要输运通道。除此之外,因晶格失配引起的逆压电效应也被认为是造成AlGaN/GaN HEMT诸多可靠性问题的主要原因。因此,减少异质界面形成的线性位错和抑制甚至消除势垒层逆压电效应对提高器件性能十分重要。Compared with traditional narrow-bandgap semiconductors, wide-bandgap III-nitride semiconductors represented by GaN have superior electrical properties such as high breakdown electric field, high electron saturation velocity, and high thermal stability. In particular, the AlGaN/GaN heterojunction with significant piezoelectric and spontaneous polarization effects can induce a high concentration of two-dimensional electron gas (2DEG) at the interface, which is the core structure of HEMT. At present, the cut-off frequency of the reported AlGaN/GaN HEMT exceeds 100GHz, and the maximum output power is close to 10W/mm. However, due to the lattice mismatch between AlGaN and GaN materials, a large number of linear dislocations will be introduced during the material growth process, resulting in device leakage current much larger than the theoretical value. Many studies on the reverse leakage current of the AlGaN/GaN HEMT gate point out that the linear dislocation between heterointerfaces is the main transport channel of the leakage current. In addition, the inverse piezoelectric effect caused by lattice mismatch is also considered to be the main cause of many reliability problems of AlGaN/GaN HEMTs. Therefore, reducing the linear dislocations formed at the heterointerface and suppressing or even eliminating the inverse piezoelectric effect of the barrier layer are very important to improve device performance.

目前,最有效的一种解决办法是在GaN外延片上直接生长与之晶格匹配的In0.17Al0.83N势垒层。尽管没有压电极化效应,其强自发极化也能够在异质界面诱发大量的2DEG,提供较大的饱和电流和输出功率。但是,研究表明势垒层材料组分改变可以明显影响异质界面诱发的2DEG浓度。而2DEG浓度的高低直接影响形成器件的饱和电流和输出功率的高低。而组分固定的晶格匹配结构将势垒层In组分固定为0.17,该组分获得的2DEG浓度并不是最高。很明显,为了实现晶格匹配,组分固定晶格匹配结构在器件的部分电学性能方面未能达到最佳。At present, one of the most effective solutions is to directly grow a lattice-matched In 0.17 Al 0.83 N barrier layer on the GaN epitaxial wafer. Although there is no piezoelectric polarization effect, its strong spontaneous polarization can also induce a large number of 2DEGs at the heterointerface, providing a large saturation current and output power. However, studies have shown that changes in the composition of barrier layer materials can significantly affect the 2DEG concentration induced by the heterointerface. The level of 2DEG concentration directly affects the saturation current and output power of the formed device. However, the lattice matching structure with fixed composition fixes the In composition of the barrier layer at 0.17, and the 2DEG concentration obtained by this composition is not the highest. It is clear that the component-fixed lattice-matched structure is suboptimal in terms of partial electrical performance of the device in order to achieve lattice matching.

本发明的目的就是针对现有技术上的不足,提供一种势垒层组分渐变的InAlN/GaNHEMT器件。实现底层In0.17Al0.83N势垒与GaN材料晶格匹配、减少异质界面形成线性位错和抑制逆压电效应的同时,通过提高其他层势垒的In组分,增强自发极化效应产生的2DEG浓度,提高器件的饱和电流和输出功率。该器件结构减少异质界面形成的线性位错和抑制逆压电效应的同时,提高了器件的饱和电流和输出功率。不仅考虑了器件的可靠性,同时提升了器件的电学性能。The object of the present invention is to provide an InAlN/GaN HEMT device with a gradient composition of the barrier layer for the deficiencies in the prior art. Realize the lattice matching between the underlying In 0.17 Al 0.83 N barrier and the GaN material, reduce the formation of linear dislocations at the heterogeneous interface, and suppress the inverse piezoelectric effect, and at the same time enhance the spontaneous polarization effect by increasing the In composition of other layer barriers The concentration of 2DEG increases the saturation current and output power of the device. The device structure improves the saturation current and output power of the device while reducing the linear dislocation formed by the heterogeneous interface and suppressing the inverse piezoelectric effect. Not only the reliability of the device is considered, but also the electrical performance of the device is improved.

发明内容Contents of the invention

鉴于现有技术存在的不足,本发明的目的旨在提供一种势垒层组分渐变的InAlN/GaNHEMT器件,该器件采用底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,通过逐渐增加势垒层In组分,增加极化效应产生的2DEG浓度,提高器件的饱和电流和输出功率。In view of the deficiencies in the prior art, the object of the present invention is to provide an InAlN/GaN HEMT device with a gradient composition of the barrier layer, which uses the underlying In 0.17 Al 0.83 N barrier to achieve lattice matching with the GaN material. Increase the In composition of the barrier layer, increase the concentration of 2DEG generated by the polarization effect, and increase the saturation current and output power of the device.

本发明通过如下技术方案实现:The present invention realizes through following technical scheme:

为达到上述目的,本发明提供了一种势垒层组分渐变的InAlN/GaN HEMT器件,主要包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,钝化层以及其上形成的栅极、源极和漏极。该结构中,衬底材料为Si,SiC,蓝宝石或者GaN;GaN成核层厚度为30nm;GaN缓冲层为非故意掺杂,厚度为3μm;AlN插入层厚度为5nm;InAlN势垒分为3-6层,每层厚度为2-5nm。底层势垒In组分为0.17,与GaN实现晶格匹配,其余势垒层In组分逐渐增加,顶层组分不不超过0.32,例如:0.17,0.20,0.23,0.26,0.29,0.32;GaN帽层厚度为2nm;钝化层为SiN,SiO2,或者Si3N4,厚度为150nm;源极和漏极为欧姆接触金属采用Ti/Al/Ti/Au,厚度分别为30nm,120nm,50nm,100nm;栅极金属采用Ni/Au,厚度分别为50nm,300nm;In order to achieve the above object, the present invention provides an InAlN/GaN HEMT device with a gradually changing composition of the barrier layer, which mainly includes a GaN nucleation layer, a GaN buffer layer, an AlN insertion layer, and a gradually changing In composition on the substrate material. InAlN barrier layer, GaN cap layer, passivation layer and gate, source and drain formed thereon. In this structure, the substrate material is Si, SiC, sapphire or GaN; the thickness of the GaN nucleation layer is 30nm; the GaN buffer layer is unintentionally doped with a thickness of 3μm; the thickness of the AlN insertion layer is 5nm; - 6 layers, each layer thickness is 2-5nm. The In composition of the bottom barrier layer is 0.17, which realizes lattice matching with GaN, and the In composition of the remaining barrier layers gradually increases, and the composition of the top layer does not exceed 0.32, for example: 0.17, 0.20, 0.23, 0.26, 0.29, 0.32; GaN cap The layer thickness is 2nm; the passivation layer is SiN, SiO 2 , or Si 3 N 4 , with a thickness of 150nm; the source and drain are ohmic contact metals using Ti/Al/Ti/Au, with a thickness of 30nm, 120nm, and 50nm, respectively. 100nm; the gate metal is Ni/Au, the thicknesses are 50nm and 300nm respectively;

本发明提供的这种势垒层组分渐变的InAlN/GaN HEMT器件,底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,有效减少材料生长过程中异质界面形成的线性位错,同时抑制了异质界面处的逆压电效应。在保证器件的可靠性前提下,通过逐渐改变势垒层In的组分,进一步提高了器件的饱和电流和输出功率。本发明对于GaN基HEMT器件的制备和提高其电学性能具有重要的意义。In the InAlN/GaN HEMT device with a gradient composition of the barrier layer provided by the present invention, the underlying In 0.17 Al 0.83 N barrier realizes lattice matching with the GaN material, effectively reducing the linear dislocation formed at the heterogeneous interface during the material growth process, At the same time, the inverse piezoelectric effect at the heterointerface is suppressed. On the premise of ensuring the reliability of the device, the saturation current and output power of the device are further improved by gradually changing the composition of the barrier layer In. The invention has important significance for the preparation of GaN-based HEMT devices and the improvement of their electrical properties.

附图说明Description of drawings

图1是本发明势垒层组分渐变的InAlN/GaN HEMT器件的层结构示意图;Fig. 1 is a schematic diagram of the layer structure of an InAlN/GaN HEMT device with a gradient composition of the barrier layer of the present invention;

图2是势垒层组分固定的的InAlN/GaN HEMT器件的层结构示意图;Figure 2 is a schematic diagram of the layer structure of an InAlN/GaN HEMT device with a fixed barrier layer composition;

图3是势垒层组分渐变和组分固定的两种InAlN/GaN HEMT器件的Id-Vg曲线;Figure 3 is the I d -V g curves of two InAlN/GaN HEMT devices with barrier layer composition gradient and fixed composition;

图4是势垒层组分渐变和组分固定的两种InAlN/GaN HEMT器件的Id-Vd曲线。Figure 4 is the I d -V d curves of two InAlN/GaN HEMT devices with barrier layer composition gradient and fixed composition.

具体实施方式detailed description

下面结合附图和实施例对本发明的技术方案作进一步的说明。The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

本发明提供的这种势垒层组分渐变的InAlN/GaN HEMT器件,包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,钝化层以及其上形成的栅极、源极和漏极。The InAlN/GaN HEMT device with a graded barrier layer composition provided by the present invention comprises a GaN nucleation layer, a GaN buffer layer, an AlN insertion layer, an InAlN barrier layer with a graded In composition, and a GaN Cap layer, passivation layer and gate, source and drain formed thereon.

势垒层组分渐变的InAlN/GaN HEMT器件层结构示意图如图1所示。衬底材料为Si,SiC,蓝宝石或者GaN;GaN成核层厚度为30nm;GaN缓冲层为非故意掺杂,厚度为3μm;AlN插入层厚度为5nm;InAlN势垒分为3-6层,每层厚度为2-5nm。底层势垒In组分为0.17,与GaN实现晶格匹配,其余势垒层In组分逐渐增加,顶层组分不不超过0.32,例如:0.17,0.20,0.23,0.26,0.29,0.32;GaN帽层厚度为2nm;钝化层为SiN,SiO2,或者Si3N4,厚度为150nm;源极和漏极为欧姆接触金属采用Ti/Al/Ti/Au,厚度分别为30nm,120nm,50nm,100nm;栅极金属采用Ni/Au,厚度分别为50nm,300nm;势垒层组分固定的InAlN/GaNHEMT器件层结构示意图如图2所示,其势垒层In组分固定,厚度为30nm。制备过程为采用金属有机物化学气相沉积法在衬底材料上逐步生长GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,通过光刻工艺和电子束蒸发工艺定义电极结构,最后生长钝化层来减少表面横向漏电流。值得注意的是,势垒层的In组分和厚度的改变对2DEG的浓度具有一定的影响。随着势垒层In组分和厚度增加,极化效应诱发的2DEG浓度也不断增加。但是,若组分过大,则会引起势垒层应变驰豫,令异质结的材料特性恶化。因此,本发明势垒层的组分和厚度需要分别控制在低于0.32和低于30nm范围内。除此之外,势垒层组分和厚度控制能够获得较高的2DEG迁移率值。这是由于当势垒层组分和厚度增加时会引起2DEG密度增大、分布变窄且更靠近异质界面造成各种散射作用发生变化,反而会降低2DEG浓度。同样条件下,相比于组分固定的InAlN/GaN HEMT器件,本发明提出的势垒层组分渐变InAlN/GaN HEMT具有更大的饱和电流,其输出功率更高(如图3和4所示)。The schematic diagram of the InAlN/GaN HEMT device layer structure with the barrier layer composition gradient is shown in Figure 1. The substrate material is Si, SiC, sapphire or GaN; the thickness of the GaN nucleation layer is 30nm; the GaN buffer layer is unintentionally doped with a thickness of 3μm; the thickness of the AlN insertion layer is 5nm; the InAlN barrier is divided into 3-6 layers, The thickness of each layer is 2-5nm. The In composition of the bottom barrier layer is 0.17, which realizes lattice matching with GaN, and the In composition of the remaining barrier layers gradually increases, and the composition of the top layer does not exceed 0.32, for example: 0.17, 0.20, 0.23, 0.26, 0.29, 0.32; GaN cap The layer thickness is 2nm; the passivation layer is SiN, SiO 2 , or Si 3 N 4 , with a thickness of 150nm; the source and drain are ohmic contact metals using Ti/Al/Ti/Au, with a thickness of 30nm, 120nm, and 50nm, respectively. 100nm; the gate metal is Ni/Au, and the thicknesses are 50nm and 300nm respectively; the schematic diagram of the InAlN/GaN HEMT device layer structure with a fixed barrier layer composition is shown in Figure 2, and the barrier layer In composition is fixed, and the thickness is 30nm. The preparation process is to gradually grow a GaN nucleation layer, a GaN buffer layer, an AlN insertion layer, an InAlN barrier layer with a gradient In composition, and a GaN cap layer on the substrate material by metal-organic chemical vapor deposition. The evaporation process defines the electrode structure, and finally a passivation layer is grown to reduce the surface lateral leakage current. It is worth noting that changes in the In composition and thickness of the barrier layer have certain effects on the concentration of 2DEG. The concentration of 2DEG induced by the polarization effect also increases with the increase of In composition and thickness of the barrier layer. However, if the composition is too large, the strain relaxation of the barrier layer will be caused, which will deteriorate the material properties of the heterojunction. Therefore, the composition and thickness of the barrier layer of the present invention need to be controlled within the range of less than 0.32 nm and less than 30 nm, respectively. In addition, barrier layer composition and thickness control can achieve higher 2DEG mobility values. This is because when the composition and thickness of the barrier layer increase, the 2DEG density will increase, the distribution will narrow, and it will be closer to the heterointerface, resulting in changes in various scattering effects, which will instead reduce the 2DEG concentration. Under the same conditions, compared with the InAlN/GaN HEMT device with fixed composition, the barrier layer composition gradient InAlN/GaN HEMT proposed by the present invention has a larger saturation current, and its output power is higher (as shown in Figures 3 and 4 Show).

本发明采用底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,通过逐渐增加势垒层In组分,增强异质界面的自发极化效应诱发的2DEG浓度,来提高了饱和电流和输出功率,实现了对InAlN/GaN HEMT电学性能的提升。由此,该结构有助于GaN基功率器件的制备及其电学性能的提升。对于AlGaN/GaN HEMT器件,晶格失配引起的异质界面线性位错和逆压电效应对严重影响其工作时的可靠性。而实现了晶格匹配的In0.17Al0.83N/GaN HEMT,由于In组分被固定在0.17,其电学性能还有进一步提升的空间。本发明通过采用底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,通过逐渐增加势垒层In组分,实现了对InAlN/GaN HEMT电学性能的进一步提升。同时,控制每层In组分变化较小,减少势垒层之间形成的线性位错和抑制逆压电效应,通过分别控制势垒层In组分和势垒层厚度,获得最佳的电学性能。相比于现有技术,本发明具有如下有益效果:在保证器件的可靠性前提下,通过逐渐改变势垒层In的组分,进一步提高了器件的饱和电流和输出功率。The present invention adopts the underlying In 0.17 Al 0.83 N barrier to realize lattice matching with GaN materials, and increases the saturation current and output by gradually increasing the In composition of the barrier layer and enhancing the 2DEG concentration induced by the spontaneous polarization effect of the heterogeneous interface. power, which improves the electrical performance of InAlN/GaN HEMTs. Therefore, the structure is helpful for the preparation of GaN-based power devices and the improvement of their electrical performance. For AlGaN/GaN HEMT devices, the linear dislocations at the heterointerface and the inverse piezoelectric effect caused by lattice mismatch seriously affect the reliability of their work. However, for In 0.17 Al 0.83 N/GaN HEMTs that have achieved lattice matching, since the In composition is fixed at 0.17, there is room for further improvement in its electrical performance. In the present invention, the electrical performance of the InAlN/GaN HEMT is further improved by using the underlying In 0.17 Al 0.83 N barrier to realize lattice matching with the GaN material, and gradually increasing the In composition of the barrier layer. At the same time, the change of In composition in each layer is controlled to be small, the linear dislocation formed between the barrier layers is reduced and the inverse piezoelectric effect is suppressed. By controlling the In composition of the barrier layer and the thickness of the barrier layer respectively, the best electrical performance. Compared with the prior art, the present invention has the following beneficial effects: on the premise of ensuring the reliability of the device, by gradually changing the composition of the barrier layer In, the saturation current and output power of the device are further improved.

最后说明的是,以上实施例仅用以说明本发明的技术方案而非限制,尽管参照较佳实施例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或者等同替换,而不脱离本发明技术方案的宗旨和范围,其均应涵盖在本发明的权利要求范围当中。Finally, it is noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out Modifications or equivalent replacements without departing from the spirit and scope of the technical solution of the present invention shall be covered by the claims of the present invention.

Claims (5)

1.一种势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于:该器件包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,钝化层以及其上形成的栅极、源极和漏极。1. A barrier layer composition graded InAlN/GaN HEMT device, characterized in that: the device comprises a GaN nucleation layer formed sequentially on the substrate material, a GaN buffer layer, an AlN insertion layer, and an In composition graded InAlN potential Barrier layer, GaN cap layer, passivation layer and gate, source and drain formed thereon. 2.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,所述衬底材料为Si,SiC,蓝宝石或者GaN。2 . The InAlN/GaN HEMT device with graded barrier layer composition according to claim 1 , wherein the substrate material is Si, SiC, sapphire or GaN. 3.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,InAlN势垒分为3-6层,每层厚度为2-5nm,总厚度在18nm-30nm范围内。3. The InAlN/GaN HEMT device with gradual barrier layer composition according to claim 1, characterized in that the InAlN barrier is divided into 3-6 layers, each layer thickness is 2-5nm, and the total thickness is 18nm-30nm within range. 4.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,底层势垒In组分为0.17,实现与GaN的晶格匹配,其余势垒层In组分逐渐增加,顶层组分不不超过0.32,例如:0.17,0.20,0.23,0.26,0.29,0.32。4. The InAlN/GaN HEMT device according to claim 1, wherein the composition of the barrier layer is graded, wherein the In composition of the underlying barrier layer is 0.17 to achieve lattice matching with GaN, and the In composition of the remaining barrier layers is 0.17. Gradually increase, the top component does not exceed 0.32, for example: 0.17, 0.20, 0.23, 0.26, 0.29, 0.32. 5.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,所述钝化层为SiN,SiO2,或者Si3N45 . The InAlN/GaN HEMT device with graded barrier layer composition according to claim 1 , wherein the passivation layer is SiN, SiO 2 , or Si 3 N 4 .
CN201610348582.1A 2016-05-24 2016-05-24 InAlN/GaN HEMT device comprising barrier layer with gradually varied components Pending CN105870165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610348582.1A CN105870165A (en) 2016-05-24 2016-05-24 InAlN/GaN HEMT device comprising barrier layer with gradually varied components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610348582.1A CN105870165A (en) 2016-05-24 2016-05-24 InAlN/GaN HEMT device comprising barrier layer with gradually varied components

Publications (1)

Publication Number Publication Date
CN105870165A true CN105870165A (en) 2016-08-17

Family

ID=56635816

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610348582.1A Pending CN105870165A (en) 2016-05-24 2016-05-24 InAlN/GaN HEMT device comprising barrier layer with gradually varied components

Country Status (1)

Country Link
CN (1) CN105870165A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107123668A (en) * 2017-04-12 2017-09-01 西安电子科技大学 A kind of InAs/AlSb HEMT epitaxial structures and preparation method thereof
CN111755510A (en) * 2019-03-26 2020-10-09 苏州捷芯威半导体有限公司 A kind of semiconductor device and preparation method thereof
CN113053748A (en) * 2021-03-12 2021-06-29 浙江大学 GaN device and preparation method
CN115394842A (en) * 2022-05-16 2022-11-25 山东大学 InAlN/GaN HEMT with high power gain cut-off frequency and preparation method thereof
CN118763107A (en) * 2024-09-06 2024-10-11 江西兆驰半导体有限公司 A gallium nitride-based high electron mobility transistor and a method for preparing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101140947A (en) * 2006-09-06 2008-03-12 中国科学院半导体研究所 GaN-based heterojunction field effect transistor structure and fabrication method
US20110049570A1 (en) * 2009-08-28 2011-03-03 Ngk Insulators, Ltd. Epitaxial substrate for semiconductor device, semiconductor device, and method of manufacturing epitaxial substrate for semiconductor device
CN103346068A (en) * 2013-07-11 2013-10-09 中国科学院半导体研究所 Method for preparing high In component AlInN thin film
CN205666237U (en) * 2016-05-24 2016-10-26 江南大学 InAlNGaN HEMT device of barrier layer component gradual change

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101140947A (en) * 2006-09-06 2008-03-12 中国科学院半导体研究所 GaN-based heterojunction field effect transistor structure and fabrication method
US20110049570A1 (en) * 2009-08-28 2011-03-03 Ngk Insulators, Ltd. Epitaxial substrate for semiconductor device, semiconductor device, and method of manufacturing epitaxial substrate for semiconductor device
CN103346068A (en) * 2013-07-11 2013-10-09 中国科学院半导体研究所 Method for preparing high In component AlInN thin film
CN205666237U (en) * 2016-05-24 2016-10-26 江南大学 InAlNGaN HEMT device of barrier layer component gradual change

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107123668A (en) * 2017-04-12 2017-09-01 西安电子科技大学 A kind of InAs/AlSb HEMT epitaxial structures and preparation method thereof
CN107123668B (en) * 2017-04-12 2019-12-13 西安电子科技大学 InAs/AlSb HEMT epitaxial structure and preparation method thereof
CN111755510A (en) * 2019-03-26 2020-10-09 苏州捷芯威半导体有限公司 A kind of semiconductor device and preparation method thereof
CN111755510B (en) * 2019-03-26 2024-04-12 苏州捷芯威半导体有限公司 Semiconductor device and preparation method thereof
CN113053748A (en) * 2021-03-12 2021-06-29 浙江大学 GaN device and preparation method
CN115394842A (en) * 2022-05-16 2022-11-25 山东大学 InAlN/GaN HEMT with high power gain cut-off frequency and preparation method thereof
CN118763107A (en) * 2024-09-06 2024-10-11 江西兆驰半导体有限公司 A gallium nitride-based high electron mobility transistor and a method for preparing the same
CN118763107B (en) * 2024-09-06 2024-12-31 江西兆驰半导体有限公司 Gallium nitride-based high electron mobility transistor and preparation method thereof

Similar Documents

Publication Publication Date Title
US20180182879A1 (en) Aluminum-gallium-nitride compound/gallium-nitride high-electron-mobility transistor
JP5634681B2 (en) Semiconductor element
JP5587564B2 (en) Field effect transistor and method of manufacturing field effect transistor
CN105609552B (en) HEMT and its manufacture method
CN110518068A (en) A kind of normally-off InAlN/GaN HMET device and preparation method thereof with p-GaN grid structure
CN102856374B (en) GaN enhanced MIS-HFET device and preparation method of same
CN105870165A (en) InAlN/GaN HEMT device comprising barrier layer with gradually varied components
JP2013074045A (en) Semiconductor device
CN102856373A (en) High-electronic-mobility-rate transistor
CN110310981A (en) Nitrogen-enhanced GaN-based Heterojunction Field-Effect Transistor with Composite Barrier Layer
CN113745332A (en) Enhanced high electron mobility transistor based on ferroelectric group III nitride polarization reversal
CN205666237U (en) InAlNGaN HEMT device of barrier layer component gradual change
CN112687738A (en) N-polar AlGaN/GaN HEMT device and growth method thereof
CN105322009A (en) Gallium nitride based high electronic mobility transistor epitaxial structure and manufacturing method therefor
CN108807500B (en) An Enhancement Mode High Electron Mobility Transistor with High Threshold Voltage
CN206441733U (en) A kind of high threshold voltage high mobility notched gates MOSFET structure
CN104409492A (en) Nitrogen polar GaN transistor
TWI572036B (en) Nitride crystal structure
CN209447805U (en) A kind of semiconductor structure
CN109742144B (en) Groove gate enhanced MISHEMT device and manufacturing method thereof
CN209447804U (en) A kind of semiconductor structure
CN109273527B (en) Semiconductor structure and forming method thereof
CN212542443U (en) Gallium nitride transistor structure and gallium nitride-based epitaxial structure
US11791407B2 (en) Semiconductor transistor structure with reduced contact resistance and fabrication method thereof
CN109599437A (en) High electron mobility transistor and preparation method thereof based on InGaN double channel heterojunction structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160817