CN105865319A - PCB testing method, PCB manufacturing method and PCB - Google Patents
PCB testing method, PCB manufacturing method and PCB Download PDFInfo
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- CN105865319A CN105865319A CN201610201026.1A CN201610201026A CN105865319A CN 105865319 A CN105865319 A CN 105865319A CN 201610201026 A CN201610201026 A CN 201610201026A CN 105865319 A CN105865319 A CN 105865319A
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- 238000012360 testing method Methods 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims description 38
- 230000005611 electricity Effects 0.000 claims description 9
- 238000007639 printing Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 abstract 3
- 239000002344 surface layer Substances 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000977 initiatory effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000011990 functional testing Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000003908 quality control method Methods 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
- G01B7/02—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
- G01B7/02—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness
- G01B7/06—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness for measuring thickness
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
A PCB testing method, a PCB manufacturing method and the PCB are disclosed. The testing method includes the steps of arranging a section of line on each signal layer of the PCB, leading the section of line to the surface layer of the PCB through at least one pair of through holes, testing the test value of the section of line through the at least one pair of through holes and determining whether the line width and line thickness of signal line of each signal layer meet the standards according to the test value and the preset threshold indicating the preset resistance. The section of line has preset resistance, preset width and preset thickness, the preset thickness is identical to the thickness of the signal lines on a same signal layer, and the length of the line is determined according to the preset resistance, preset width, preset thickness, and the electrical resistivity of the line. The test value indicates the tested resistance of the line.
Description
Technical field
The present invention relates to printed circuit board technology field, particularly relate to the test side of a kind of printing board PCB
Method, the manufacture method of PCB and PCB.
Background technology
Printed circuit board (English: Printed Circuit Board, it is called for short: live width and line thickness PCB) refer to
The width of cabling and copper thickness in each signals layer of PCB.PCB manufacturer can be done by user under normal circumstances
Basic norm requirement, each performance indications of PCB must are fulfilled for every design requirement.PCB manufacturer is detailed according to these
Thin design requires processing PCB, and user carries out an acceptance inspection with this specification, and wherein live width and line thickness are weights
The acceptance index wanted.
The thick inherent character as PCB of live width and line and important performance indexes, it exceeds standard and belongs to PCB supplied materials and lack
Fall into, time serious, can directly cause signal lead characteristic impedance to deviate, and for hardware designs, its signal
Cabling characteristic impedance have to strictly be controlled well, because it directly influences the signal quality of single plate hardware.
In the prior art, generally there are two kinds of live widths and the detection mode of line thickness.The first: dispatch from the factory at PCB
Before carry out batch sampling observation, tester manual detection after using easy hand-held test Instrument of Line Width and hand-held logical,
All of test data manual record also preserves, common tester such as OXFORD-95M.The second,
PCB user does supplied materials quality control, and (English: Incoming Quality Control is called for short: IQC), make
With Time Domain Reflectometry, (English: Time-Domain Reflectometry, is called for short: TDR) specialty Meter Test list
The characteristic impedance of partitioned signal cabling, common instrument has CSA8200.
But the first detection mode measuring instrument is simple, test error is relatively big, measures relatively time-consuming, so nothing
Method realizes batch detection.The second needs to buy special instrument instrument, and testing cost is high, so also cannot be real
Existing batch detection.Therefore, in prior art, the detection mode detection ratio of live width and line thickness is limited, detection effect
Rate is low.
Summary of the invention
The embodiment of the present invention provide the method for testing of a kind of printing board PCB, the manufacture method of PCB and
PCB, in order to solve the technical problem that in prior art, the method for detection live width and line thickness is inefficient.
First aspect, embodiments provides the method for testing of a kind of PCB, including:
Each signals layer at PCB arranges one section of cabling；Wherein, described one section of cabling has predetermined resistance, pre-
Fixed width degree, predetermined thickness, at same signals layer, described predetermined thickness is identical with the thickness of signal lead；Institute
State the length of cabling by described predetermined resistance, described preset width, described predetermined thickness, described cabling electricity
Resistance rate determines；Described cabling is guided to by least one pair of via the top layer of described PCB；By described at least one
Via test is obtained the test value of described cabling；Described test value is for characterizing the test resistance of described cabling
Value；Described each signals layer is determined by described test value with for characterizing the predetermined threshold of described predetermined resistance
The live width of signal lead and line thickness whether conformance with standard.
By the method in the embodiment of the present invention, because the test resistance value for characterizing cabling of test cabling
Instrument relatively simple, cost is relatively low, such as circuit tester, as long as and because the test resistance value of test cabling,
So the used time is shorter, usually Microsecond grade, so from cost and the test used time support can survey in batches
The examination live width of PCB and line thickness whether conformance with standard, so improve test live width and the thick efficiency of line.
In conjunction with first aspect, in the first possible implementation of first aspect, described each signals layer
Described cabling between the most separate；Or, with also between the described cabling of described each signals layer
The mode of connection is connected with each other；
Corresponding, by described test value and for characterize the predetermined threshold of described predetermined resistance determine described often
The live width of the signal lead of individual signals layer and line thickness whether conformance with standard, including:
Determine that the difference between described test value and described predetermined threshold is whether in default range of error；Institute
State difference in described default range of error time, determine live width and the line thickness conformance with standard of described signal lead；
When described difference is outside described default range of error, determine the live width of described signal lead and/or line thickness not
Conformance with standard.
In conjunction with first aspect, in the implementation that the second of first aspect is possible, described each signals layer
Described cabling between be connected with each other in series；
Corresponding, by described test value and for characterize the predetermined threshold of described predetermined resistance determine described often
The live width of the signal lead of individual signals layer and line thickness whether conformance with standard, including:
Determine that whether the difference between described test value and the described predetermined threshold sum of described each signals layer exists
In preset range；When described difference is in described default range of error, determine the live width of described signal lead
With line thickness conformance with standard；When described difference is outside described default range of error, determine described signal lead
Live width and/or line thickness do not meet standard.
Second aspect, the embodiment of the present invention provides the manufacture method of a kind of printing board PCB, including:
Each signals layer at PCB arranges one section of cabling；Wherein, described one section of cabling has predetermined resistance, pre-
Fixed width degree, predetermined thickness, at same signals layer, described predetermined thickness is identical with the thickness of signal lead；Institute
State the length of cabling by described predetermined resistance, described preset width, described predetermined thickness, described cabling electricity
Resistance rate determines；Described cabling is guided to by least one pair of via the top layer of described PCB；Wherein, described at least
A pair via is used in testing for the test value of described cabling, and described test value is for characterizing the test of described cabling
Resistance value.
By the method in the present embodiment, a kind of being easy to can be made and test live width and the PCB of line thickness, at not shadow
In the case of ringing the performance of PCB, it is achieved test live width rapidly and efficiently and line thickness whether conformance with standard.
In conjunction with second aspect, in the first possible implementation of second aspect, described method also includes:
On at least one pair of via described, pad is set；Wherein, described pad be placed on described at least one pair of
It is connected with at least one pair of via described on via or by lead-in wire.
The third aspect, the embodiment of the present invention provides a kind of printing board PCB, including:
At least one signals layer, is provided with one section of cabling and signal lead on each signals layer；Wherein,
Described one section of cabling has predetermined resistance, preset width, predetermined thickness, at same signals layer, described predetermined
Thickness is identical with the thickness of described signal lead；The length of described cabling is by described predetermined resistance, described pre-
Fixed width degree, described predetermined thickness, described trace resistances rate determine；At least one pair of via, extends through in institute
State the top PCB layer at the two ends of cabling；Wherein, at least one pair of via described is used in testing for the survey of described cabling
Examination value, described test value is for characterizing the test resistance value of described cabling.
In conjunction with the third aspect, in the first possible implementation of the third aspect, described PCB also includes:
At least one pair of lead-in wire, lays respectively at least one pair of via described, with the two ends electricity of described one section of cabling
Property be connected.By this lead-in wire, in that context it may be convenient to measure the test resistance value of cabling.
In conjunction with the first possible implementation of the third aspect, the realization that the second in the third aspect is possible
In mode, described PCB also includes: pad, is arranged at least one pair of via described；Wherein, described weldering
Dish is placed at least one pair of via described or is connected with at least one pair of via described by lead-in wire.By setting
Put pad, be on the one hand easy to encapsulate PCB, on the other hand can facilitate and be electrically connected with test instrunment.
In any one above-mentioned possible implementation, described cabling is to be different from walking of described signal lead
Line；Or, described cabling is the part of described signal lead.
In any one above-mentioned possible implementation, at electricity between the described cabling of described each signals layer
In property separate；Or, it is connected in parallel with between the described cabling of described each signals layer；
Or, it is connected with each other in series between the described cabling of described each signals layer.
Accompanying drawing explanation
The flow chart of the manufacture method of a kind of PCB that Fig. 1 provides for the embodiment of the present invention；
A kind of schematic diagram netlist relation schematic diagram that Fig. 2 provides for the embodiment of the present invention；
The schematic diagram of the relation between a kind of each signal lead that Fig. 3 a-Fig. 3 b provides for the embodiment of the present invention；
The structure chart of a kind of PCB that Fig. 4 a-Fig. 4 d provides for the embodiment of the present invention；
The flow chart of the method for testing of the live width of a kind of PCB that Fig. 5 provides for the embodiment of the present invention and line thickness；
The equivalent circuit diagram of a kind of resistance testing cabling that Fig. 6 provides for the embodiment of the present invention.
Detailed description of the invention
The embodiment of the present invention provide the method for testing of a kind of printing board PCB, the manufacture method of PCB and
PCB, in order to solve the technical problem that in prior art, the method for detection live width and line thickness is inefficient.
The implementation process of scheme, purpose in the embodiment of the present invention described in detail below.
The terms "and/or", a kind of incidence relation describing affiliated partner, expression can exist
Three kinds of relations, such as, A and/or B, can represent: individualism A, there is A and B, individually simultaneously
There is B these three situation.It addition, character "/" herein, typically represent forward-backward correlation to as if a kind of "or"
Relation.
Refer to as it is shown in figure 1, be the flow chart of the manufacture method of PCB in the embodiment of the present invention.As it is shown in figure 1,
The method includes:
Step 101: each signals layer at PCB arranges one section of cabling；Wherein, described one section of cabling has pre-
Determine resistance, preset width, predetermined thickness, in the thickness of same signals layer, described predetermined thickness and signal lead
Spend identical；The length of described cabling by described predetermined resistance, described preset width, described predetermined thickness,
Described trace resistances rate determines；
Step 102: described cabling is guided to by least one pair of via the top layer of described PCB.
Optionally, in the design phase of PCB, each PCB has a PCB file (file format is * .brd),
This PCB file record, for generating the information of PCB, including the level of PCB, such as, has how many layers, respectively
It is any layer, every layer of requirement to line thickness.
Then, on the schematic diagram (file format is * .prj, * .dprj) of PCB, each signals layer increases a net
Network also sets up schematic diagram netlist relation.Each network uses similar structure.Each network includes: a net
Network mark (ID) point, this network ID point is not electrically connected with other functional device on PCB.
Refer to shown in Fig. 2, it is assumed that the PCB of current design includes 8 layer signal layers, does not include bus plane and connects
Stratum.Circular dot on the left of Fig. 2 represents the network ID of each signals layer, such as ID68 to ID75.The side on right side
Block and line represent network cabling.Network 0 is corresponding with n-th layer signals layer.N value is 0 to 8.
Embody, so can there is no real cabling on schematic diagram it should be noted that Fig. 2 is only drawing.
Schematic diagram netlist relation shown in Fig. 2 be used to instruct PCB manufacturer when manufacturing PCB, at these signals layers
It is respectively provided with cabling.
Therefore, when PCB placement-and-routing, respectively one section of cabling is set at each signals layer of PCB.Wherein, institute
State one section of cabling and there is predetermined resistance, preset width, predetermined thickness.At same signals layer, predetermined thickness with
The thickness of signal lead is identical.As known in PCB file, every layer signal layer is to the line of signal lead thick
Requirement, so at the line of same signals layer, the predetermined thickness of described one section of cabling and the signal lead of requirement
Thick identical.
The length of described cabling is by described predetermined resistance, described preset width, described predetermined thickness, described
Trace resistances rate determines.
Specifically, the D.C. resistance computing formula of conductor is formula (1).
R=ρ * L/S formula (1)
Wherein, R is resistance, when routing of layout, can make a reservation for a resistance value, such as 1 Europe or 2 Europe.
ρ is resistivity, and for known conductor material, resistivity is a known constant.And S depends on cabling
Thickness h and live width l, so formula (2) can be obtained by formula (1).
R=ρ * L/ (h*l) formula (2)
When PCB design cabling, the thickness h of cabling is known.Therefore, live width l and length L of cabling is determined
Fixed final resistance R.In the present embodiment, resistance R is the pre-resistance reserved, so can by formula (2)
With predetermined live width l and length L.
Then, while arranging normal signal cabling, or before or after, also arrange at each signals layer
One section of cabling, this section of cabling has predetermined resistance, preset width, predetermined thickness, predetermined length.
Next perform step 102, the top layer of PCB will be guided to by least one pair of via by described cabling.Cause
The internal layer of PCB it is usually located at for signals layer, for the ease of follow-up test, punched in the position at the two ends of cabling,
Then described cabling is guided to the top layer of PCB.So, can by via can test described cabling resistance,
Electric current or voltage.
Optionally, follow-up test and the encapsulation of PCB, also arrange pad at least one pair of via for convenience.
Described pad is placed at least one pair of via described or is connected with at least one pair of via described by lead-in wire.
Therefore, when follow-up test, directly the resistance of described cabling, electric current or voltage can be tested by pad.
Optionally, described cabling can be different from the cabling of normal signal cabling, such as outside signal lead
Being separately provided one section of cabling, this cabling is not connected with the components and parts on PCB.
Optionally, cabling can also is that a part for signal lead.Such as at signals layer, inherently need cloth
Office's signal lead, then just can determine, according to the predetermined resistance of holding wire, thickness, width, the signal chosen
Length L of cabling, then corresponding at the two ends of the signal lead of a length of L chosen position is punched to be led to
Top layer.
In above-mentioned two situations, it is separate electrically between the cabling of each signals layer.At this
In the case of two kinds, predetermined resistance, width and the length of the cabling that each layer signal layer is arranged all can be different.
Optionally, it is connected in parallel with between the cabling of each signals layer.Specifically refer to Fig. 3 a
Shown in, in this example, still illustrate as a example by 8 layer signal layers.On each layer signal layer 10, cabling
20 are all disposed within identical upright position, so the via 40 of each layer is all beaten on identical position, so
Rear lead-in wire 50 passes the via 40 on top layer 30.It it is now mode in parallel between every section of cabling 20.This
Under parallel way, the length of cabling 20 on each layer signal layer 10, width and thickness, material are the most identical.
Optionally, it is connected with each other in series between the described cabling of each signals layer.Refer to Fig. 3 b
Shown in.In this example, still illustrate as a example by 7 layer signal layers.Cabling 20 is a complete cabling,
The length of this cabling 20 is determined by predetermined resistance, line thickness, live width.Cabling 20 runs through each by via 40
Signals layer 10.When punched, a via can be made a call at the initiating terminal of cabling 20, will by lead-in wire 50
Cabling 20 is drawn out to top layer 30.And make a call to a via at the end end of cabling 20, by lead-in wire 50 by cabling 20
It is drawn out to top layer 30.As in fig 3b, at a bottom layer signal layer 10, right side is the initiating terminal of cabling 20,
Then cabling 20 is by via 40 through each signals layer 10, then walks one on uppermost signals layer 20
After measured length, then on the position that the end of cabling 20 is corresponding, make a call to a via 40 on top layer 30, so
End is led to top layer 30 by rear lead-in wire 50.A mistake is made a call on signals layer 10 on initiating terminal and top layer 30
Hole, leads to top layer 30 by initiating terminal by lead-in wire 50.
It should be noted that the length of the cabling of each layer signal layer can not wait, it is also possible to equal.Not
Deng time, cabling run through signals layer via and lead-in wire place via be probably different vias.
The PCB made by preceding method may include that at least one signals layer, arranges on each signals layer
There are one section of cabling and signal lead；Wherein, described one section of cabling has predetermined resistance, preset width, pre-
Determining thickness, at same signals layer, described predetermined thickness is identical with the thickness of described signal lead；Described cabling
Length true by described predetermined resistance, described preset width, described predetermined thickness, described trace resistances rate
Fixed；At least one pair of via, extends through the top PCB layer in the two ends of described cabling.
Optionally, described cabling is the cabling being different from described signal lead；Or, described cabling is described letter
The part of number cabling.
Optionally, the most separate between the described cabling of each signals layer；Or, described each letter
It is connected in parallel with between the described cabling of number floor；Or, the described cabling of described each signals layer
Between be connected with each other in series.
Optionally, this PCB also includes: at least one pair of lead-in wire, lays respectively at least one pair of via described, with
The two ends of described one section of cabling are electrical connected.
Optionally, this PCB also includes: pad, is arranged at least one pair of via described；Wherein, described
Pad is placed at least one pair of via described or is connected with at least one pair of via described by lead-in wire.
Below by the structure of the PCB in illustration the present embodiment.Refer to shown in Fig. 4 a and Fig. 4 b, for this
The structure chart of a kind of PCB that bright embodiment provides.This PCB is for example, made by aforementioned manner.Wherein,
Fig. 4 a is the sectional view of PCB, and Fig. 4 b is the top view of PCB.
As shown in fig. 4 a, signals layer 201 is provided with cabling 202.The top PCB that the two ends of cabling 202 are corresponding
Layer, signals layer 301, signals layer 401 and top layer 501 are provided with a pair via 203.Pair of lead wires 204 position respectively
In a pair via 203, it is electrically connected with the two ends of cabling 202.
On the top layer 501 of Fig. 4 b, it can be seen that via to 403, via to 303 and via to 203.
Certainly, in figs. 4 a and 4b, the cabling of each signals layer is separately provided, and at Vertical Square
Upwards position is the most overlapping, it is possible to see via pair as shown in Figure 4 b.
If the cabling of each signals layer is in parallel or series connection, then will only have one on top layer
To via.
Further, it is possible to via on pad is set, refer to shown in Fig. 4 c.Corresponding to via to 203,
It is provided with pad to 205, corresponding to via to 303, is provided with pad to 305, corresponding to via
To 403, it is provided with pad to 405.
Optionally, two pairs or more via can be beaten in the two ends of every section of cabling, refer to shown in Fig. 4 d.
Assume that the two ends of cabling 202 are to there being two pairs of vias 203.When the quantity of via is more, relative number of vias is relatively
Few situation, measurement result can be more accurate.
Optionally, at every section of cabling to when should have at least two pairs of vias, every pair of via is distributed axisymmetricly.
Referring next to shown in Fig. 5, the flow process of the method for testing of a kind of PCB provided for the embodiment of the present invention
Figure.The method includes: step 101, step 102, step 103 and step 104.Wherein, step 101 and step
Rapid 102 is identical with abovementioned steps 101 and step 102.
Step 103 is: obtained the test value of described cabling by least one pair of via described test；Described test
Value is for characterizing the test resistance value of described cabling；
Step 104 is: determine described by described test value with for characterizing the predetermined threshold of described predetermined resistance
The live width of the signal lead of each signals layer and line thickness whether conformance with standard.
Wherein, the execution stage of step 103 and step 104 can be in the manufacturing process of PCB, it is also possible to is
Test when PCB arrives PCB party in request.Such as it is synchronized to veneer on-line testing (English: In-Circuit
Test, is called for short: ICT), (English: Functional Test is called for short: in FT) in functional test.
In step 103, described test value is for characterizing the test resistance value of described cabling, it is possible to pass through
At least one pair of via described tests the test resistance value of described cabling, such as, use the resistance test skill of milliohm level
The resistance of cabling is measured by art.In practice, it is also possible to according to Ohm's law, resistance is equal to electricity
Press divided by electric current, measure voltage and current, be then calculated the actual resistance of cabling according to Ohm's law.
Or test value can also be directly curtage.
Refer to shown in Fig. 6, for a kind of possible equivalent circuit during resistance test of cabling.In this example,
Assuming that cabling correspondence two, to via, is for a pair via a, via d, another is to for via b and via c.Rx is
The D.C. resistance of cabling, r1, r2, r3 and r4 are PCB and the contact resistance of test instrunment introducing.Test system
Driving voltage source DCV, electric current is I1, measures voltage V, the electric current I2 of resistance Rx, because voltmeter internal resistance is non-
Chang great, so I2 approximates 0, so r2 and r3 is negligible relative to voltmeter, and flows through r1's and r2
Electric current is identical with the electric current of Rx, is all I1, so Rx=V/I1, this formula is referred to as formula (3).Public
Formula (3) is the formula meeting Ohm's law.
Accordingly, at step 104, by test value and true for characterizing the predetermined threshold of described predetermined resistance
The live width of the signal lead of fixed each signals layer and line thickness whether conformance with standard.In with once comparing, test
Value and characterize the predetermined threshold of predetermined resistance and belong to same type of parameter, such as, be resistance, voltage or electricity
Stream.
It should be noted that it is the most separate between the described cabling of each signals layer；Or, institute
Stating when being connected in parallel with between the described cabling of each signals layer, step 104 comprises determining that institute
State the difference between test value and described predetermined threshold whether in default range of error；In described difference in institute
When stating in default range of error, determine live width and the line thickness conformance with standard of described signal lead；In described difference
Time outside described default range of error, determine that the live width of described signal lead and/or line thickness do not meet standard.
And the most interconnective situation between the cabling for each signals layer, step 104 has two
Plant processing mode, first kind of way: determine described test value and the described predetermined threshold of described each signals layer
Whether the difference between sum is in preset range；When described difference is in described default range of error, really
The live width of fixed described signal lead and line thickness conformance with standard；In described difference outside described default range of error
Time, determine that the live width of described signal lead and/or line thickness do not meet standard.Under this kind of mode, every section is walked
The predetermined threshold of line is sued for peace, because measure in step 103 is also the series resistance of all cablings.
The second way, in a step 101, predetermined resistance and length refer to the situation that all cablings add up,
I.e. a piece cabling of design, runs through all signals layers, and this situation needs every layer signal layer thickness to cabling
The requirement of degree is identical.Corresponding, step 104 comprise determining that described test value and described predetermined threshold it
Between difference whether in preset range；When described difference is in described default range of error, determine described
The live width of signal lead and line thickness conformance with standard；When described difference is outside described default range of error, really
Live width and/or the line thickness of fixed described signal lead do not meet standard.
For example, when Rx exceeds default range of error more than R, according to formula (1), then cabling is described
Live width h and/or line thickness l are less than what design required, wired children and/or the defect of copper thickness deficiency.
When Rx less than R beyond when presetting range of error, according to formula (1), then illustrate cabling live width h and/
Or line thickness l is bigger than what design required, there is cabling wide and/or defect that Copper Foil is blocked up.
Because this cabling and signal lead are identical process equipment processing, if so line of this section of cabling
Wide defective with line thickness, then also to illustrate that the live width of other signal lead and line thickness are defective, do not meet
Standard.
It should be noted that during judging, be provided with default range of error, so can eliminate one
The error that a little measurements or other factors bring, and then avoid erroneous judgement.
By above description it can be seen that the embodiment of the present invention provides a kind of PCB manufacture method and method of testing,
The PCB made by the method has testability, and method of testing is simple, low cost, test speed
Hurry up, so improve testing efficiency, it is possible to achieve batch detection.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (14)
1. the method for testing of a printing board PCB, it is characterised in that including:
Each signals layer at PCB arranges one section of cabling；Wherein, described one section of cabling has predetermined resistance, pre-
Fixed width degree, predetermined thickness, at same signals layer, described predetermined thickness is identical with the thickness of signal lead；Institute
State the length of cabling by described predetermined resistance, described preset width, described predetermined thickness, described cabling electricity
Resistance rate determines；
Described cabling is guided to by least one pair of via the top layer of described PCB；
The test value of described cabling is obtained by least one pair of via described test；Described test value is used for characterizing
The test resistance value of described cabling；
Described each signals layer is determined by described test value with for characterizing the predetermined threshold of described predetermined resistance
The live width of signal lead and line thickness whether conformance with standard.
2. the method for claim 1, it is characterised in that described cabling is walked for being different from described signal
The cabling of line；Or, described cabling is the part of described signal lead.
3. the method for claim 1, it is characterised in that the described cabling of described each signals layer it
Between the most separate；Or, the most mutual between the described cabling of described each signals layer
Connect；
Corresponding, by described test value and for characterize the predetermined threshold of described predetermined resistance determine described often
The live width of the signal lead of individual signals layer and line thickness whether conformance with standard, including:
Determine that the difference between described test value and described predetermined threshold is whether in default range of error；
When described difference is in described default range of error, determine live width and the line thickness symbol of described signal lead
Standardization；
When described difference is outside described default range of error, determine live width and/or the line of described signal lead
Thickness does not meets standard.
4. the method for claim 1, it is characterised in that the described cabling of described each signals layer it
Between be connected with each other in series；
Corresponding, by described test value and for characterize the predetermined threshold of described predetermined resistance determine described often
The live width of the signal lead of individual signals layer and line thickness whether conformance with standard, including:
Determine that whether the difference between described test value and the described predetermined threshold sum of described each signals layer exists
In preset range；
When described difference is in described default range of error, determine live width and the line thickness symbol of described signal lead
Standardization；
When described difference is outside described default range of error, determine live width and/or the line of described signal lead
Thickness does not meets standard.
5. the method as described in any one of claim 1-4, it is characterised in that described method also includes:
On at least one pair of via described, pad is set；Described pad is placed at least one pair of via described
Or it is connected with at least one pair of via described by lead-in wire.
6. the manufacture method of a printing board PCB, it is characterised in that including:
Each signals layer at PCB arranges one section of cabling；Wherein, described one section of cabling has predetermined resistance, pre-
Fixed width degree, predetermined thickness, at same signals layer, described predetermined thickness is identical with the thickness of signal lead；Institute
State the length of cabling by described predetermined resistance, described preset width, described predetermined thickness, described cabling electricity
Resistance rate determines；
Described cabling is guided to by least one pair of via the top layer of described PCB；
Wherein, at least one pair of via described is used in testing for the test value of described cabling, and described test value is used for
Characterize the test resistance value of described cabling.
7. method as claimed in claim 6, it is characterised in that described cabling is walked for being different from described signal
The cabling of line；Or, described cabling is the part of described signal lead.
8. method as claimed in claim 6, it is characterised in that the described cabling of described each signals layer it
Between the most separate；Or, the most mutual between the described cabling of described each signals layer
Connect；Or, it is connected with each other in series between the described cabling of described each signals layer.
9. the method as described in any one of claim 6-8, it is characterised in that described method also includes:
On at least one pair of via described, pad is set；Wherein, described pad be placed on described at least one pair of
It is connected with at least one pair of via described on via or by lead-in wire.
10. a printing board PCB, it is characterised in that including:
At least one signals layer, is provided with one section of cabling and signal lead on each signals layer；Wherein,
Described one section of cabling has predetermined resistance, preset width, predetermined thickness, at same signals layer, described predetermined
Thickness is identical with the thickness of described signal lead；The length of described cabling is by described predetermined resistance, described pre-
Fixed width degree, described predetermined thickness, described trace resistances rate determine；
At least one pair of via, extends through the top PCB layer in the two ends of described cabling；
Wherein, at least one pair of via described is used in testing for the test value of described cabling, and described test value is used for
Characterize the test resistance value of described cabling.
11. PCB as claimed in claim 10, it is characterised in that described cabling is walked for being different from described signal
The cabling of line；Or, described cabling is the part of described signal lead.
12. PCB as claimed in claim 10, it is characterised in that the described cabling of described each signals layer it
Between the most separate；Or, the most mutual between the described cabling of described each signals layer
Connect；Or, it is connected with each other in series between the described cabling of described each signals layer.
13. PCB as described in claim 10-12, it is characterised in that described PCB also includes:
At least one pair of lead-in wire, lays respectively at least one pair of via described, with the two ends electricity of described one section of cabling
Property be connected.
14. PCB as claimed in claim 13, it is characterised in that described PCB also includes:
Pad, is arranged at least one pair of via described；Wherein, described pad be placed on described at least one
To on via or by lead-in wire be connected with at least one pair of via described.
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| CN201610201026.1A CN105865319A (en) | 2016-03-31 | 2016-03-31 | PCB testing method, PCB manufacturing method and PCB |
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| CN107493655A (en) * | 2017-08-28 | 2017-12-19 | 郑州云海信息技术有限公司 | The method and system that circuit easily fuses at a kind of solution DIP device solder joints |
| CN108445339A (en) * | 2017-02-16 | 2018-08-24 | 通用汽车环球科技运作有限责任公司 | The leak testing method of low electric conductivity part |
| CN109492310A (en) * | 2018-11-14 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of method and check device of the inspection of line |
| CN110220449A (en) * | 2019-06-28 | 2019-09-10 | 广东品能实业股份有限公司 | Circuit board and conductive layer thickness detection method and detection equipment |
| CN110244214A (en) * | 2019-05-29 | 2019-09-17 | 晶晨半导体(上海)股份有限公司 | A kind of detection method of printed circuit board |
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| CN113804095A (en) * | 2020-06-16 | 2021-12-17 | 健鼎（湖北）电子有限公司 | Circuit board convenient for testing copper thickness and copper thickness testing method thereof |
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| CN108445339A (en) * | 2017-02-16 | 2018-08-24 | 通用汽车环球科技运作有限责任公司 | The leak testing method of low electric conductivity part |
| CN107493655B (en) * | 2017-08-28 | 2019-05-14 | 郑州云海信息技术有限公司 | It is a kind of to solve the method and system that route easily fuses at DIP device solder joint |
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| CN109492310B (en) * | 2018-11-14 | 2021-10-29 | 郑州云海信息技术有限公司 | Method and device for checking circuit |
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| CN110375696B (en) * | 2019-07-23 | 2021-07-09 | 福州瑞华印制线路板有限公司 | Method for rapidly calculating thickness of copper in PCB (printed circuit board) via hole |
| CN110375696A (en) * | 2019-07-23 | 2019-10-25 | 福州瑞华印制线路板有限公司 | A kind of method of quick reckoning PCB via hole hole copper thickness |
| WO2021227977A1 (en) * | 2020-05-09 | 2021-11-18 | 中兴通讯股份有限公司 | Printed circuit board |
| CN113804095A (en) * | 2020-06-16 | 2021-12-17 | 健鼎（湖北）电子有限公司 | Circuit board convenient for testing copper thickness and copper thickness testing method thereof |
| CN113804095B (en) * | 2020-06-16 | 2024-09-13 | 健鼎（湖北）电子有限公司 | Circuit board convenient for testing copper thickness and copper thickness testing method thereof |
| CN111707928A (en) * | 2020-06-29 | 2020-09-25 | 广东浪潮大数据研究有限公司 | Method and device for testing PCB wiring processing capacity |
| CN112188725B (en) * | 2020-09-25 | 2021-10-08 | 深圳市景旺电子股份有限公司 | Impedance test module of printed circuit board and manufacturing method of printed circuit board |
| CN112188725A (en) * | 2020-09-25 | 2021-01-05 | 深圳市景旺电子股份有限公司 | Impedance test module of printed circuit board and manufacturing method of printed circuit board |
| WO2022156132A1 (en) * | 2021-01-22 | 2022-07-28 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| US11846670B2 (en) | 2021-01-22 | 2023-12-19 | Changxin Memory Technologies, Inc. | Chip testing board and chip testing method |
| CN113923860A (en) * | 2021-10-11 | 2022-01-11 | 恒为科技（上海）股份有限公司 | SFI interface-based electrical signal testing device |
| CN113923860B (en) * | 2021-10-11 | 2023-08-29 | 恒为科技（上海）股份有限公司 | Electric signal testing device based on SFI interface |
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