CN105826421A - Indium bump device structure and preparation method for same - Google Patents

Abstract

The invention relates to an indium bump device structure and a preparation method thereof, and belongs to the technical field of indium bump device preparation. The device structure includes a semiconductor substrate, a pad, a first passivation layer, a second passivation layer, a UBM metal layer and an indium bump; the UBM metal layer includes an adhesion layer, a barrier layer, a buffer layer and a wetting layer; in the In the device structure, the adhesion layer covers part of the first passivation layer, and the second passivation layer covers part of the adhesion layer. This stack structure provides high structural strength and prevents the The case where the structure consisting of indium bumps and UBM is detached along the interface between the adhesion layer and the first passivation layer due to thermal stress. In addition, the setting of the buffer layer alleviates the change of the internal stress between the substrate and the UBM during reflow, thereby preventing the indium bump from falling off the wetting layer due to excessive change of the internal stress. Therefore, the device structure of the present invention has higher stability and longer service life.

Description

A kind of indium bump device structure and its preparation method

technical field

The invention belongs to the technical field of indium bump device preparation, and in particular relates to an indium bump device structure and a preparation method thereof.

Background technique

At present, infrared focal plane detectors have been widely used in military, industry, environment, medicine, etc., and with the advancement of science and technology, people's demand for large area array detectors is increasing. However, with the increase of the number of picture elements, the difficulty of designing and interconnecting the focal plane and the readout circuit is also increasing. Traditional gold wire bonding technology has exposed obvious disadvantages, such as: high interconnection resistance, long circuit, large package size and low interconnection density. Flip-chip interconnection technology can not only overcome the above-mentioned shortcomings, but also has low cost, so it is widely used.

In the infrared detector flip-chip interconnection technology, the underlying metal (UBM) plays the roles of adhesion, diffusion barrier, wetting and work function matching. In addition, metal indium has good ductility at low temperature, good flexibility at room temperature, easy to realize bonding, good mechanical and electrical interconnection characteristics, and is especially suitable for low-temperature working requirements of infrared detectors. Therefore, the indium bump structure with underlying metal UBM is crucial for the flip-chip interconnection of infrared detectors.

FIG. 1 is a cross-sectional structural diagram of an indium bump device in the prior art. The structure 100 includes a semiconductor substrate 101 , a bonding pad 102 , a passivation layer 103 , an underlying metal UBM 104 , and an indium ball 105 . The passivation layer 103 covers the substrate 101 and a part of the bonding pad 102 , and the UBM 104 is located between the bonding pad 102 and the indium ball 105 .

The UBM 104 has three layers in total, which are an adhesion layer 104a, a barrier layer 104b, and a wetting layer 104c. Adhesive layer 104a covers exposed pad 102 and part of passivation layer 103, barrier layer 104b covers adhesive layer 104a, wetting layer 104c covers barrier layer 104b, and adhesive layer 104a, barrier layer 104b and The cross-sectional dimensions of the wetting layers 104c are the same; the indium balls 105 cover the wetting layers 104c. Among them, the adhesion layer 104a can enhance the adhesion between the pad 102 and the barrier layer 104b, the function of the barrier layer 104b is to block the diffusion reaction between the indium ball 105 and the underlying metal, and the wetting layer 104c can enhance the adhesion between the indium ball 105 and the UBM104. Adhesion.

Generally, before the formation of the indium ball 105, the process of reflow and shrinkage is required, that is, the indium column before reflow is heated to melt it, and the surface tension of indium and the infiltration of UBM are used to make the indium column into an indium ball, thereby improving the indium column. The height of the bump. During the reflow process, the molten indium will react with the wetting layer 104c at the bottom to form a layer of metal compound. The formation of the metal compound layer will change the internal stress between the UBM 104 and the substrate 101. When the internal stress changes greatly , the indium balls 105 will fall off from the wetting layer 104c.

In addition, in the structure 100, since the peripheral portion of the UBM 104 is distributed on the passivation layer 103, the coefficient of thermal expansion between the structure 106 composed of the substrate 101 and the passivation layer 103 and the structure 107 composed of the UBM 104 and the indium bump 105 difference, when the indium bump device is subjected to high temperature (180°C) thermal shock during reflow, thermal stress is generated between the adhesion layer 104a and the passivation layer 103, which eventually leads to the structure 107 composed of UBM104 and indium bump 105 along the adhesion The interface between the layer 104a and the passivation layer 103 is peeled off.

The above two situations will affect the performance and stability of the device and shorten the life of the device. Therefore, how to overcome the deficiencies of the prior art is an urgent problem to be solved in the field of indium bump device fabrication technology.

Contents of the invention

The object of the present invention is to solve the deficiencies of the prior art, and provide an indium bump device structure and a preparation method thereof, so as to improve the falling off of the indium bump and improve the stability and life of the indium bump device.

To achieve the above object, the technical scheme adopted in the present invention is as follows:

An indium bump device structure, characterized in that it includes a semiconductor substrate, a pad, a first passivation layer, a second passivation layer, a UBM metal layer, and an indium bump;

The UBM metal layer includes an adhesion layer, a barrier layer, a buffer layer and a wetting layer arranged sequentially from bottom to top;

The pad is placed on the surface of the semiconductor substrate, the first passivation layer is covered on the surface of the semiconductor substrate and the pad, and a first opening is provided at the overlap between the first passivation layer and the pad, and the surface of the pad is separated from the first opening exposed;

The adhesive layer covers the surface of the pad exposed at the first opening, and the peripheral portion of the adhesive layer is located on the surface of the first passivation layer, so that the adhesive layer partially overlaps with the first passivation layer;

The second passivation layer is covered on the surface of the first passivation layer and the surface of the adhesion layer, and a second opening is provided at the overlap between the second passivation layer and the adhesion layer, exposing the adhesion layer through the second opening;

the cross-sectional width of the second opening is greater than the cross-sectional width of the first opening;

The barrier layer is arranged on the surface of the adhesive layer exposed at the second opening, the buffer layer covers the surface of the barrier layer, the wetting layer covers the surface of the buffer layer, and the indium bump covers the surface of the wetting layer;

And, the barrier layer, the buffer layer and the wetting layer are not in contact with the second passivation layer;

The cross-sectional widths of the barrier layer, the buffer layer and the wetting layer are all the same; the cross-sectional width of the adhesive layer is greater than that of the barrier layer.

Further, preferably, the material of the semiconductor substrate is Si.

Further, preferably, the material of the first passivation layer is SiO ₂ or Si ₃ N ₄ , the material of the second passivation layer is SiO ₂ or Si ₃ N ₄ , and the first passivation layer and the second passivation layer Layer material is the same.

Further, it is preferred that the material of the pad is metal Al or Cu.

Further, preferably, the material of the adhesion layer is metal Ti, Ni, Cr or Ta.

Further, preferably, the material of the barrier layer is metal Pt, Pd, Ni.

Further, preferably, the buffer layer and the wetting layer are made of the same material, both being metal Au.

Further, it is preferred that the material of the indium bumps is metal indium; the indium bumps are spherical or columnar.

The method for preparing the above-mentioned indium bump device structure includes the following steps:

Step (1), taking a semiconductor substrate with a pad, covering the substrate and the pad with a first passivation layer, and then obtaining a first opening by photolithography and etching to expose part of the pad;

Step (2), covering the surface of the pad exposed at the first opening with an adhesive layer, and partially covering the first passivation layer;

Step (3), coating the second passivation layer on the surface of the first passivation layer and the surface of the adhesion layer, and then obtaining a second opening by photolithography and etching to expose part of the adhesion layer;

Step (4), depositing a barrier layer on the surface of the adhesive layer exposed at the second opening, then covering the barrier layer with a buffer layer, and then covering the buffer layer with a wetting layer;

In step (5), metal indium is deposited on the wetting layer to form indium pillars, and then reflowed so that the indium pillars become indium balls.

Compared with the prior art, the present invention has the beneficial effects of:

In the indium bump device structure provided by the present invention, the adhesive layer covers part of the first passivation layer, and the second passivation layer covers part of the adhesive layer. This stacked structure provides higher structural strength, so When the device is subject to thermal shock, it can prevent the structure composed of the indium bump and the UBM from falling off along the interface between the adhesive layer and the first passivation layer due to thermal stress.

In addition, in the indium bump device structure provided by the present invention, there is a layer of buffer layer metal Au in the UBM structure, which plays a buffer role, that is, it eases the change of internal stress between the substrate and the UBM during reflow, and then Prevent the indium bump from falling off the wetting layer due to excessive internal stress changes.

Therefore, compared with the traditional device structure, the indium bump device structure provided by the present invention has higher stability, and the service life of the device is increased by 15% compared with the traditional device.

Description of drawings

FIG. 1 is a cross-sectional structural diagram of an indium bump device in the prior art.

FIG. 2 is a cross-sectional structure view of the indium bump device of the present invention.

3A-3I are flow charts showing the formation of the indium bump device structure of the present invention.

Wherein, 200, indium bump device structure; 201, semiconductor substrate; 202, pad; 203, first passivation layer; 203a, first opening; 204, second passivation layer; 204a, second opening; 205 , UBM metal layer; 205a, adhesion layer; 205b, barrier layer; 205c, buffer layer; 205d, wetting layer; 206, indium bump; 207, first photolithography mask layer; 208, first cross-sectional opening; 209 , the second photolithographic mask layer; 210, the second cross-sectional opening; 211, the third photolithographic mask layer; 212, the third cross-sectional opening; 213, the indium column; 214, the indium ball with the UBM layer.

detailed description

The present invention will be further described in detail below in conjunction with the examples.

Those skilled in the art will understand that the following examples are only for illustrating the present invention and should not be considered as limiting the scope of the present invention. If no specific technique or condition is indicated in the examples, it shall be carried out according to the technique or condition described in the literature in this field or according to the product specification. The reagents or instruments used were not indicated by the manufacturer, and they were all conventional products that could be purchased.

Those skilled in the art should understand that since the layered structure of the present invention overlaps, the two sides of the first opening 203 a and the second opening 204 a are drawn out and then marked, and the drawn width is also the cross-sectional width.

FIG. 2 is a cross-sectional structure view of the indium bump device of the present invention. The indium bump device structure 200 includes a semiconductor substrate 201 , pads 202 , a first passivation layer 203 , a second passivation layer 204 , a UBM metal layer 205 , and an indium bump 206 . The UBM metal layer 205 includes an adhesion layer 205a, a barrier layer 205b, a buffer layer 205c and a wetting layer 205d arranged in sequence from bottom to top.

The pad 202 is placed on the surface of the semiconductor substrate 201, the first passivation layer 203 covers the surface of the semiconductor substrate 201 and the pad 202, and a first opening 203a is provided where the first passivation layer 203 overlaps with the pad 202, exposing the surface of the pad 202 through the first opening 203a;

The adhesive layer 205a is covered on the surface of the pad 202 exposed at the first opening 203a, and the peripheral portion of the adhesive layer 205a is located on the surface of the first passivation layer 203, so that the adhesive layer 205a and the first passivation layer 203 part overlapping;

The second passivation layer 204 is covered on the surface of the first passivation layer 203 and the surface of the adhesion layer 205a, and the second passivation layer 204 and the adhesion layer 205 overlap are provided with a second opening 204a, the adhesion layer 205a is separated from the first Two openings 204a are exposed;

The cross-sectional width of the second opening 204a is greater than the cross-sectional width of the first opening 205a;

The barrier layer 205b is disposed on the surface of the adhesive layer 205a exposed at the second opening 204a, the buffer layer 205c covers the surface of the barrier layer 205b, the wetting layer 205d covers the surface of the buffer layer 205c, and the indium bump 206 covers the surface of the wetting layer; 2, the indium bumps 206 are spherical, that is, indium balls.

Moreover, the barrier layer 205b, the buffer layer 205c and the wetting layer 205d are not in contact with the second passivation layer 204;

The cross-sectional widths of the barrier layer 205b, the buffer layer 205c and the wetting layer 205d are all the same; the cross-sectional width of the adhesive layer 205a is greater than that of the barrier layer 205b.

That is, the first passivation layer 203 covers the substrate 201 and part of the pad 202; the adhesive layer 205a covers the exposed pad 202 and part of the first passivation layer 203, and its cross-sectional width is d1 _; The layer 204 covers the first passivation layer 203 and part of the adhesion layer 205a; the barrier layer 205b, the buffer layer 205c and the wetting layer 205d successively cover the exposed part of the adhesion layer 205a, the barrier layer 205b, the buffer layer 205c and the wetting layer. The cross-sectional width of the layer 205d is also d ₂ , and d ₂ is smaller than d ₁ ; the indium bump 206 covers the wetting layer 205d.

The material of the semiconductor substrate is Si.

The material of the first passivation layer 203 is SiO ₂ or Si ₃ N ₄ , the material of the second passivation layer 204 is SiO ₂ or Si ₃ N ₄ , and the first passivation layer 203 and the second passivation layer 204 are made of the same material.

The pad 202 is made of metal Al or Cu.

The material of the adhesion layer 205a is metal Ti, Ni, Cr or Ta.

The material of the barrier layer 205b is metal Pt, Pd, Ni.

The buffer layer 205c and the wetting layer 205d are made of the same material, both being metal Au.

The material of the indium bumps 206 is metal indium; the indium bumps 206 can also be columnar.

A semiconductor substrate 201 having pads 202 is provided in FIG. 3A. The first passivation layer 203 covers the semiconductor substrate 201 and part of the pads 202 . The first passivation layer 203 is SiO ₂ or Si ₃ N ₄ , and the pad 202 is metal Al or Cu. The structure of the first passivation layer 203 can be realized through a series of processes such as plasma enhanced chemical vapor deposition (PECVD), photolithography and etching.

In Fig. 3B, the first photolithographic mask layer 207 has a _first cross-sectional opening 208 with a size of d1, and the adhesion layer 205a is deposited into the first cross-sectional opening 208, covering the exposed pad 202 and part of the first passivation layer 203. The first photolithography mask layer 207 can be realized through a series of processes such as coating photoresist, photolithography and development. The adhesion layer 205a is metal Ti, Ta, Cr, and the deposition of the adhesion layer 205a can be realized by means of sputtering, thermal evaporation, etc., and the first photolithography mask layer 207 can be removed by using acetone, and finally the cross-sectional size is d ₁ , the adhesive layer 205a covers the exposed pad 202 and part of the first passivation layer 203, as shown in FIG. 3C.

In FIG. 3D, the second passivation layer 204 covers the first passivation layer 203 and part of the adhesion layer 205a. The second passivation layer 204 is SiO ₂ , Si ₃ N ₄ , and the structure of the second passivation layer 204 can be realized through a series of processes such as plasma enhanced chemical vapor deposition (PECVD), photolithography and etching.

In Fig. 3E, the second photolithographic mask layer 209 has a second cross-sectional opening 210 with a size _d2 , and the barrier layer 205b, the buffer layer 205c and the wetting layer 205d are sequentially deposited into the second cross-sectional opening 210, that is, sequentially deposited on the exposed Adhesive layer 205a. The barrier layer 205b is made of Pt, Pd and Ni, and the buffer layer 205c and the wetting layer 205d are both made of metal Au. The barrier layer 205b, the buffer layer 205c and the wetting layer 205d can be deposited by means of sputtering, thermal evaporation and the like. The second photolithography mask layer 209 can be realized through a series of processes such as coating photoresist, photolithography and development. The second photolithographic mask layer 209 can be removed with acetone to obtain a barrier layer 205b, a buffer layer 205c and a wetting layer 205d with a cross-sectional dimension of _d2 , as shown in FIG. 3F, in particular, _d2 is smaller than the adhesion layer 205a The cross-sectional dimension d ₁ .

In FIG. 3G , there is a third photolithography mask layer 211 with a third cross-sectional opening 212 , and metal indium is deposited into the third cross-sectional opening 212 . The third photolithography mask layer 211 can be realized through a series of processes such as coating photoresist, photolithography and development, and the deposition of metal indium can be realized by means such as sputtering and thermal evaporation, and then the third photolithography mask layer 211 Acetone is used to remove the indium column 213 finally, as shown in FIG. 3H .

The indium bumps 206 in FIG. 3I can be obtained by reflowing the indium pillars 213 . During the reflow process, the melted indium pillars 213 form the indium bumps 206 by using surface tension (indium balls are formed in this embodiment). In addition, the molten indium column 213 will react with the Au of the wetting layer 205d at the bottom thereof to form an Au-In metal compound, and the generation of the Au-In metal compound will change the internal stress between the UBM metal layer 205 and the semiconductor substrate 201, but In the UBM metal layer 205 in the present invention, there is a buffer layer 205c of metal Au. The existence of the buffer layer 205c greatly reduces the variation of the internal stress between the UBM metal layer 205 and the semiconductor substrate 201, thereby preventing indium bumps. The dots 206 are detached from the surface of the wetting layer 205d.

In addition, in the present invention, the structure composed of the first passivation layer 203, the adhesion layer 205a and the second passivation layer 204 has high structural strength, so that when the device is subjected to high-temperature thermal shock, it can prevent the As a result, the structure 214 composed of the UBM metal layer 205 and the indium bump 206 falls off along the interface of the adhesion layer 205 a and the first passivation layer 203 .

Therefore, compared with the traditional device structure, the indium bump device structure provided by the present invention has higher stability and greatly improves the service life of the device.

The basic principles, main features and advantages of the present invention have been shown and described above. Those skilled in the industry should understand that the present invention is not limited by the above-mentioned embodiments, and what described in the above-mentioned embodiments and the description only illustrates the principles of the present invention, and the present invention will also have other functions without departing from the spirit and scope of the present invention. Variations and improvements all fall within the scope of the claimed invention. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (9)

1. An indium bump device structure, characterized in that it comprises a semiconductor substrate, a pad, a first passivation layer, a second passivation layer, a UBM metal layer and an indium bump; The UBM metal layer includes an adhesion layer, a barrier layer, a buffer layer and a wetting layer arranged sequentially from bottom to top; The pad is placed on the surface of the semiconductor substrate, the first passivation layer is covered on the surface of the semiconductor substrate and the pad, and a first opening is provided at the overlap between the first passivation layer and the pad, and the surface of the pad is separated from the first opening exposed; The adhesive layer covers the surface of the pad exposed at the first opening, and the peripheral portion of the adhesive layer is located on the surface of the first passivation layer, so that the adhesive layer partially overlaps with the first passivation layer; The second passivation layer is covered on the surface of the first passivation layer and the surface of the adhesion layer, and a second opening is provided at the overlap between the second passivation layer and the adhesion layer, exposing the adhesion layer through the second opening; the cross-sectional width of the second opening is greater than the cross-sectional width of the first opening; The barrier layer is arranged on the surface of the adhesive layer exposed at the second opening, the buffer layer covers the surface of the barrier layer, the wetting layer covers the surface of the buffer layer, and the indium bump covers the surface of the wetting layer; And, the barrier layer, the buffer layer and the wetting layer are not in contact with the second passivation layer; The cross-sectional widths of the barrier layer, the buffer layer and the wetting layer are all the same; the cross-sectional width of the adhesive layer is greater than that of the barrier layer. 2 . The indium bump device structure according to claim 1 , wherein the semiconductor substrate is made of Si. 3 . 3. The indium bump device structure according to claim 1, wherein the material of the first passivation layer is SiO ₂ or Si ₃ N ₄ , and the material of the second passivation layer is SiO ₂ or Si ₃ N ₄ , and the material of the first passivation layer and the second passivation layer are the same. 4 . The indium bump device structure according to claim 1 , wherein the pad is made of metal Al or Cu. 5 . The indium bump device structure according to claim 1 , wherein the material of the adhesion layer is metal Ti, Ni, Cr or Ta. 6 . The indium bump device structure according to claim 1 , wherein the material of the barrier layer is metal Pt, Pd, or Ni. 7. The indium bump device structure according to claim 1, wherein the buffer layer and the wetting layer are made of the same material, which is Au metal. 8 . The device structure with indium bumps according to claim 1 , wherein the material of the indium bumps is metal indium; the indium bumps are spherical or columnar. 9. The method for preparing the indium bump device structure according to claims 1-8, comprising the following steps: Step (1), taking a semiconductor substrate with a pad, covering the substrate and the pad with a first passivation layer, and then obtaining a first opening by photolithography and etching to expose part of the pad; Step (2), covering the surface of the pad exposed at the first opening with an adhesive layer, and partially covering the first passivation layer; Step (3), coating the second passivation layer on the surface of the first passivation layer and the surface of the adhesion layer, and then obtaining a second opening by photolithography and etching to expose part of the adhesion layer; Step (4), depositing a barrier layer on the surface of the adhesive layer exposed at the second opening, then covering the barrier layer with a buffer layer, and then covering the buffer layer with a wetting layer; In step (5), metal indium is deposited on the wetting layer to form indium pillars, and then reflowed so that the indium pillars become indium balls.